[llvm] [BOLT][AArch64] Add support for LDR relaxtion on LDRSl/LDRDl/LDRQl (PR #196983)

[Shanzhi Chen via llvm-commits]

chenshanzhi wrote:

For robustness, use the stack push/pop method in the latest commit.

Using x16/x17 may be a good idea. All I know about x16 and x17 is that they are commonly used in PLT code. But [aapcs64.rst](https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst) says that they may be used as caller-saved registers at other times. So I'm not fully understand this statement:

> ... code generators won't use x16/x17 across blocks, and the only thing we need to check is that we won't clobber a definition inside the same block, ...

Must this assumption necessarily hold? Will the compiler/linker use x16/x17 as ordinary caller-saved registers in current mainstream implementations?

https://github.com/llvm/llvm-project/pull/196983