[llvm] [AMDGPU] gfx1251 cost model (PR #203682)
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llvm-commits at lists.llvm.org
Sat Jun 13 00:49:04 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-analysis
Author: Stanislav Mekhanoshin (rampitec)
<details>
<summary>Changes</summary>
---
Patch is 219.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203682.diff
10 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp (+18-4)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll (+90-14)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/fadd.ll (+192-16)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/fma.ll (+145-9)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/fmul.ll (+135)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll (+367-59)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll (+407-35)
- (added) llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll (+24)
- (added) llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll (+107)
- (added) llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll (+44)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 7631bb2dc6828..3c7d60daebdd6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -334,7 +334,10 @@ GCNTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
case TargetTransformInfo::RGK_Scalar:
return TypeSize::getFixed(32);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(ST->hasPackedFP32Ops() ? 64 : 32);
+ return TypeSize::getFixed((ST->hasPackedFP64Ops() || ST->hasPackedU64Ops())
+ ? 128
+ : ST->hasPackedFP32Ops() ? 64
+ : 32);
case TargetTransformInfo::RGK_ScalableVector:
return TypeSize::getScalable(0);
}
@@ -353,7 +356,10 @@ unsigned GCNTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
return (ElemWidth == 8 && ST->has16BitInsts()) ? 4
: (ElemWidth == 16 && ST->has16BitInsts()) ? 2
: (ElemWidth == 32 && ST->hasPackedFP32Ops()) ? 2
- : 1;
+ : (ElemWidth == 64 &&
+ (ST->hasPackedFP64Ops() || ST->hasPackedU64Ops()))
+ ? 2
+ : 1;
}
bool GCNTTIImpl::preferSLPInstCountCheck() const {
@@ -566,6 +572,9 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
return getFullRateInstrCost() * LT.first * NElts;
case ISD::ADD:
case ISD::SUB:
+ if (SLT == MVT::i64 && ST->hasPackedU64Ops())
+ NElts = (NElts + 1) / 2;
+ [[fallthrough]];
case ISD::AND:
case ISD::OR:
case ISD::XOR:
@@ -618,8 +627,11 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
NElts = (NElts + 1) / 2;
if (ST->hasBF16PackedInsts() && SLT == MVT::bf16)
NElts = (NElts + 1) / 2;
- if (SLT == MVT::f64)
+ if (SLT == MVT::f64) {
+ if (ST->hasPackedFP64Ops())
+ NElts = (NElts + 1) / 2;
return LT.first * NElts * get64BitInstrCost(CostKind);
+ }
if (ST->has16BitInsts() && SLT == MVT::f16)
NElts = (NElts + 1) / 2;
@@ -882,7 +894,9 @@ GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
if ((ST->hasVOP3PInsts() &&
(SLT == MVT::f16 || SLT == MVT::i16 ||
(SLT == MVT::bf16 && ST->hasBF16PackedInsts()))) ||
- (ST->hasPackedFP32Ops() && SLT == MVT::f32))
+ (ST->hasPackedFP32Ops() && SLT == MVT::f32) ||
+ (ST->hasPackedFP64Ops() && SLT == MVT::f64) ||
+ (ST->hasPackedU64Ops() && SLT == MVT::i64))
NElts = (NElts + 1) / 2;
// TODO: Get more refined intrinsic costs?
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll b/llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
index 2a966b4ea178f..5f984ab9c3c63 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=ALL,FAST16 %s
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=ALL,SLOW16 %s
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1251 < %s | FileCheck -check-prefixes=ALL,FAST64 %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=ALL-SIZE,FAST16-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=ALL-SIZE,SLOW16-SIZE %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1251 < %s | FileCheck -check-prefixes=ALL-SIZE,FAST64-SIZE %s
; END.
define amdgpu_kernel void @add_i32() #0 {
@@ -43,21 +45,53 @@ define amdgpu_kernel void @add_i32() #0 {
}
define amdgpu_kernel void @add_i64() #0 {
-; ALL-LABEL: 'add_i64'
-; ALL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
-; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = add <2 x i64> undef, undef
-; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = add <3 x i64> undef, undef
-; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = add <4 x i64> undef, undef
-; ALL-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = add <5 x i64> undef, undef
-; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+; FAST16-LABEL: 'add_i64'
+; FAST16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
+; FAST16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = add <2 x i64> undef, undef
+; FAST16-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = add <3 x i64> undef, undef
+; FAST16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = add <4 x i64> undef, undef
+; FAST16-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = add <5 x i64> undef, undef
+; FAST16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
-; ALL-SIZE-LABEL: 'add_i64'
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = add <2 x i64> undef, undef
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = add <3 x i64> undef, undef
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = add <4 x i64> undef, undef
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = add <5 x i64> undef, undef
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+; SLOW16-LABEL: 'add_i64'
+; SLOW16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
+; SLOW16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = add <2 x i64> undef, undef
+; SLOW16-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = add <3 x i64> undef, undef
+; SLOW16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = add <4 x i64> undef, undef
+; SLOW16-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = add <5 x i64> undef, undef
+; SLOW16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+;
+; FAST64-LABEL: 'add_i64'
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i64 = add <2 x i64> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i64 = add <3 x i64> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i64 = add <4 x i64> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v5i64 = add <5 x i64> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+;
+; FAST16-SIZE-LABEL: 'add_i64'
+; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
+; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = add <2 x i64> undef, undef
+; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = add <3 x i64> undef, undef
+; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = add <4 x i64> undef, undef
+; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = add <5 x i64> undef, undef
+; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; SLOW16-SIZE-LABEL: 'add_i64'
+; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
+; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = add <2 x i64> undef, undef
+; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = add <3 x i64> undef, undef
+; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = add <4 x i64> undef, undef
+; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = add <5 x i64> undef, undef
+; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; FAST64-SIZE-LABEL: 'add_i64'
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = add i64 undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i64 = add <2 x i64> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i64 = add <3 x i64> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i64 = add <4 x i64> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v5i64 = add <5 x i64> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%i64 = add i64 undef, undef
%v2i64 = add <2 x i64> undef, undef
@@ -90,6 +124,17 @@ define amdgpu_kernel void @add_i16() #0 {
; SLOW16-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17i16 = add <17 x i16> undef, undef
; SLOW16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
+; FAST64-LABEL: 'add_i16'
+; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = add i16 undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = add <2 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = add <3 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = add <4 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = add <5 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v6i16 = add <6 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i16 = add <16 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v17i16 = add <17 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+;
; FAST16-SIZE-LABEL: 'add_i16'
; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = add i16 undef, undef
; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = add <2 x i16> undef, undef
@@ -111,6 +156,17 @@ define amdgpu_kernel void @add_i16() #0 {
; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16i16 = add <16 x i16> undef, undef
; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17i16 = add <17 x i16> undef, undef
; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; FAST64-SIZE-LABEL: 'add_i16'
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = add i16 undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = add <2 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = add <3 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = add <4 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = add <5 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v6i16 = add <6 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i16 = add <16 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v17i16 = add <17 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%i16 = add i16 undef, undef
%v2i16 = add <2 x i16> undef, undef
@@ -178,6 +234,16 @@ define amdgpu_kernel void @sub() #0 {
; SLOW16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = sub <4 x i16> undef, undef
; SLOW16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
+; FAST64-LABEL: 'sub'
+; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = sub i8 undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = sub i16 undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = sub i32 undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = sub i64 undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = sub <2 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = sub <3 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = sub <4 x i16> undef, undef
+; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+;
; FAST16-SIZE-LABEL: 'sub'
; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = sub i8 undef, undef
; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = sub i16 undef, undef
@@ -197,6 +263,16 @@ define amdgpu_kernel void @sub() #0 {
; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = sub <3 x i16> undef, undef
; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = sub <4 x i16> undef, undef
; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; FAST64-SIZE-LABEL: 'sub'
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = sub i8 undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = sub i16 undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = sub i32 undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = sub i64 undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = sub <2 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = sub <3 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = sub <4 x i16> undef, undef
+; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%i8 = sub i8 undef, undef
%i16 = sub i16 undef, undef
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fadd.ll b/llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
index 9b1495b35a89d..703f4b0933cdc 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
@@ -3,10 +3,12 @@
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32,FASTF16,FASTF64 %s
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32,SLOWF64 %s
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1251 < %s | FileCheck -check-prefixes=GFX1251 %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FASTF16-SIZE,GFX90A-FASTF64-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32-SIZE,FASTF16-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32-SIZE,SLOWF64-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250-SIZE %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1251 < %s | FileCheck -check-prefixes=GFX1251-SIZE %s
; END.
define amdgpu_kernel void @fadd_f32() #0 {
@@ -30,6 +32,26 @@ define amdgpu_kernel void @fadd_f32() #0 {
; NOPACKEDF32-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v9f32 = fadd <9 x float> poison, poison
; NOPACKEDF32-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
+; GFX1250-LABEL: 'fadd_f32'
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = fadd float poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = fadd <2 x float> poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3f32 = fadd <3 x float> poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32 = fadd <4 x float> poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v5f32 = fadd <5 x float> poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8f32 = fadd <8 x float> poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v9f32 = fadd <9 x float> poison, poison
+; GFX1250-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+;
+; GFX1251-LABEL: 'fadd_f32'
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = fadd float poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = fadd <2 x float> poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3f32 = fadd <3 x float> poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32 = fadd <4 x float> poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v5f32 = fadd <5 x float> poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8f32 = fadd <8 x float> poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v9f32 = fadd <9 x float> poison, poison
+; GFX1251-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
+;
; GFX90A-FASTF64-SIZE-LABEL: 'fadd_f32'
; GFX90A-FASTF64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = fadd float poison, poison
; GFX90A-FASTF64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = fadd <2 x float> poison, poison
@@ -49,6 +71,26 @@ define amdgpu_kernel void @fadd_f32() #0 {
; NOPACKEDF32-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8f32 = fadd <8 x float> poison, poison
; NOPACKEDF32-SIZE-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v9f32 = fadd <9 x float> poison, poison
; NOPACKEDF32-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; GFX1250-SIZE-LABEL: 'fadd_f32'
+; GFX1250-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203682
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