[llvm] [1/3][AMDGPU][NFC] Add virtual prefix to GCN trackers (PR #203667)
Dhruva Chakrabarti via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 21:29:42 PDT 2026
https://github.com/dhruvachak created https://github.com/llvm/llvm-project/pull/203667
The renames are to clarify that these fields capture virtual register attributes and are in preparation for physical register support.
Replaces https://github.com/llvm/llvm-project/pull/183673.
>From c52901405768fadd816cca99c7bbac46e1a3611c Mon Sep 17 00:00:00 2001
From: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: Thu, 26 Feb 2026 18:01:13 -0600
Subject: [PATCH 1/3] [AMDGPU][NFC] Add virtual prefix to GCN LiveRegs and
Pressure.
The renames are to clarify that these fields capture virtual register
attributes and are in preparation for upcoming physical register
support.
---
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 135 ++++++++++----------
llvm/lib/Target/AMDGPU/GCNRegPressure.h | 41 +++---
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 4 +-
llvm/lib/Target/AMDGPU/GCNSchedStrategy.h | 6 +-
4 files changed, 94 insertions(+), 92 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index 54e67d9d2a808..571ca3475305c 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -492,7 +492,7 @@ GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
const LiveIntervals &LIS,
const MachineRegisterInfo &MRI,
GCNRegPressure::RegKind RegKind) {
- GCNRPTracker::LiveRegSet LiveRegs;
+ GCNRPTracker::LiveRegSet VirtLiveRegs;
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
auto Reg = Register::index2VirtReg(I);
if (RegKind != GCNRegPressure::TOTAL_KINDS &&
@@ -502,33 +502,32 @@ GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
continue;
auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
if (LiveMask.any())
- LiveRegs[Reg] = LiveMask;
+ VirtLiveRegs[Reg] = LiveMask;
}
- return LiveRegs;
+ return VirtLiveRegs;
}
void GCNRPTracker::reset(const MachineInstr &MI,
- const LiveRegSet *LiveRegsCopy,
- bool After) {
+ const LiveRegSet *VirtLiveRegsCopy, bool After) {
const MachineFunction &MF = *MI.getMF();
MRI = &MF.getRegInfo();
- if (LiveRegsCopy) {
- if (&LiveRegs != LiveRegsCopy)
- LiveRegs = *LiveRegsCopy;
+ if (VirtLiveRegsCopy) {
+ if (&VirtLiveRegs != VirtLiveRegsCopy)
+ VirtLiveRegs = *VirtLiveRegsCopy;
} else {
- LiveRegs = After ? getLiveRegsAfter(MI, LIS)
- : getLiveRegsBefore(MI, LIS);
+ VirtLiveRegs =
+ After ? getLiveRegsAfter(MI, LIS) : getLiveRegsBefore(MI, LIS);
}
- MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
+ MaxVirtPressure = CurVirtPressure = getRegPressure(*MRI, VirtLiveRegs);
}
-void GCNRPTracker::reset(const MachineRegisterInfo &MRI_,
- const LiveRegSet &LiveRegs_) {
- MRI = &MRI_;
- LiveRegs = LiveRegs_;
+void GCNRPTracker::reset(const MachineRegisterInfo &MRInfo,
+ const LiveRegSet &VirtLiveRegsSet) {
+ MRI = &MRInfo;
+ VirtLiveRegs = VirtLiveRegsSet;
LastTrackedMI = nullptr;
- MaxPressure = CurPressure = getRegPressure(MRI_, LiveRegs_);
+ MaxVirtPressure = CurVirtPressure = getRegPressure(MRInfo, VirtLiveRegsSet);
}
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
@@ -569,46 +568,47 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
} else
DefPressure.inc(Reg, LaneBitmask::getNone(), DefMask, *MRI);
- auto I = LiveRegs.find(Reg);
- if (I == LiveRegs.end())
+ auto I = VirtLiveRegs.find(Reg);
+ if (I == VirtLiveRegs.end())
continue;
LaneBitmask &LiveMask = I->second;
LaneBitmask PrevMask = LiveMask;
LiveMask &= ~DefMask;
- CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
+ CurVirtPressure.inc(Reg, PrevMask, LiveMask, *MRI);
if (LiveMask.none())
- LiveRegs.erase(I);
+ VirtLiveRegs.erase(I);
}
- // Update MaxPressure with defs pressure.
- DefPressure += CurPressure;
+ // Update MaxVirtPressure with defs pressure.
+ DefPressure += CurVirtPressure;
if (HasECDefs)
DefPressure += ECDefPressure;
- MaxPressure = max(DefPressure, MaxPressure);
+ MaxVirtPressure = max(DefPressure, MaxVirtPressure);
// Make uses alive.
SmallVector<VRegMaskOrUnit, 8> RegUses;
collectVirtualRegUses(RegUses, MI, LIS, *MRI);
for (const VRegMaskOrUnit &U : RegUses) {
- LaneBitmask &LiveMask = LiveRegs[U.VRegOrUnit.asVirtualReg()];
+ LaneBitmask &LiveMask = VirtLiveRegs[U.VRegOrUnit.asVirtualReg()];
LaneBitmask PrevMask = LiveMask;
LiveMask |= U.LaneMask;
- CurPressure.inc(U.VRegOrUnit.asVirtualReg(), PrevMask, LiveMask, *MRI);
+ CurVirtPressure.inc(U.VRegOrUnit.asVirtualReg(), PrevMask, LiveMask, *MRI);
}
- // Update MaxPressure with uses plus early-clobber defs pressure.
- MaxPressure = HasECDefs ? max(CurPressure + ECDefPressure, MaxPressure)
- : max(CurPressure, MaxPressure);
+ // Update MaxVirtPressure with uses plus early-clobber defs pressure.
+ MaxVirtPressure = HasECDefs
+ ? max(CurVirtPressure + ECDefPressure, MaxVirtPressure)
+ : max(CurVirtPressure, MaxVirtPressure);
- assert(CurPressure == getRegPressure(*MRI, LiveRegs));
+ assert(CurVirtPressure == getRegPressure(*MRI, VirtLiveRegs));
}
////////////////////////////////////////////////////////////////////////////////
// GCNDownwardRPTracker
bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
- const LiveRegSet *LiveRegsCopy) {
+ const LiveRegSet *VirtLiveRegsCopy) {
MRI = &MI.getMF()->getRegInfo();
LastTrackedMI = nullptr;
MBBEnd = MI.getParent()->end();
@@ -616,7 +616,7 @@ bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
if (NextMI == MBBEnd)
return false;
- GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
+ GCNRPTracker::reset(*NextMI, VirtLiveRegsCopy, false);
return true;
}
@@ -655,31 +655,32 @@ bool GCNDownwardRPTracker::advanceBeforeNext(MachineInstr *MI,
continue;
const LiveInterval &LI = LIS.getInterval(MO.getReg());
if (LI.hasSubRanges()) {
- auto It = LiveRegs.end();
+ auto It = VirtLiveRegs.end();
for (const auto &S : LI.subranges()) {
if (!S.liveAt(SI)) {
- if (It == LiveRegs.end()) {
- It = LiveRegs.find(MO.getReg());
- if (It == LiveRegs.end())
+ if (It == VirtLiveRegs.end()) {
+ It = VirtLiveRegs.find(MO.getReg());
+ if (It == VirtLiveRegs.end())
llvm_unreachable("register isn't live");
}
auto PrevMask = It->second;
It->second &= ~S.LaneMask;
- CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
+ CurVirtPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
}
}
- if (It != LiveRegs.end() && It->second.none())
- LiveRegs.erase(It);
+ if (It != VirtLiveRegs.end() && It->second.none())
+ VirtLiveRegs.erase(It);
} else if (!LI.liveAt(SI)) {
- auto It = LiveRegs.find(MO.getReg());
- if (It == LiveRegs.end())
+ auto It = VirtLiveRegs.find(MO.getReg());
+ if (It == VirtLiveRegs.end())
llvm_unreachable("register isn't live");
- CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
- LiveRegs.erase(It);
+ CurVirtPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(),
+ *MRI);
+ VirtLiveRegs.erase(It);
}
}
- MaxPressure = max(MaxPressure, CurPressure);
+ MaxVirtPressure = max(MaxVirtPressure, CurVirtPressure);
LastTrackedMI = nullptr;
@@ -702,13 +703,13 @@ void GCNDownwardRPTracker::advanceToNext(MachineInstr *MI,
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
- auto &LiveMask = LiveRegs[Reg];
+ auto &LiveMask = VirtLiveRegs[Reg];
auto PrevMask = LiveMask;
LiveMask |= getDefRegMask(MO, *MRI);
- CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
+ CurVirtPressure.inc(Reg, PrevMask, LiveMask, *MRI);
}
- MaxPressure = max(MaxPressure, CurPressure);
+ MaxVirtPressure = max(MaxVirtPressure, CurVirtPressure);
}
bool GCNDownwardRPTracker::advance(MachineInstr *MI, bool UseInternalIterator) {
@@ -732,8 +733,8 @@ bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator End) {
bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator Begin,
MachineBasicBlock::const_iterator End,
- const LiveRegSet *LiveRegsCopy) {
- reset(*Begin, LiveRegsCopy);
+ const LiveRegSet *VirtLiveRegsCopy) {
+ reset(*Begin, VirtLiveRegsCopy);
return advance(End);
}
@@ -774,7 +775,7 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, *MRI, true, /*IgnoreDead=*/false);
RegOpers.adjustLaneLiveness(LIS, *MRI, SlotIdx);
- GCNRegPressure TempPressure = CurPressure;
+ GCNRegPressure TempPressure = CurVirtPressure;
for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
if (!Use.VRegOrUnit.isVirtualReg())
@@ -803,8 +804,9 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
if (LastUseMask.none())
continue;
- auto It = LiveRegs.find(Reg);
- LaneBitmask LiveMask = It != LiveRegs.end() ? It->second : LaneBitmask(0);
+ auto It = VirtLiveRegs.find(Reg);
+ LaneBitmask LiveMask =
+ It != VirtLiveRegs.end() ? It->second : LaneBitmask(0);
LaneBitmask NewMask = LiveMask & ~LastUseMask;
TempPressure.inc(Reg, LiveMask, NewMask, *MRI);
}
@@ -814,8 +816,9 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
if (!Def.VRegOrUnit.isVirtualReg())
continue;
Register Reg = Def.VRegOrUnit.asVirtualReg();
- auto It = LiveRegs.find(Reg);
- LaneBitmask LiveMask = It != LiveRegs.end() ? It->second : LaneBitmask(0);
+ auto It = VirtLiveRegs.find(Reg);
+ LaneBitmask LiveMask =
+ It != VirtLiveRegs.end() ? It->second : LaneBitmask(0);
LaneBitmask NewMask = LiveMask | Def.LaneMask;
TempPressure.inc(Reg, LiveMask, NewMask, *MRI);
}
@@ -826,7 +829,7 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
bool GCNUpwardRPTracker::isValid() const {
const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
- const auto &TrackedLR = LiveRegs;
+ const auto &TrackedLR = VirtLiveRegs;
if (!isEqual(LISLR, TrackedLR)) {
dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
@@ -837,22 +840,22 @@ bool GCNUpwardRPTracker::isValid() const {
}
auto LISPressure = getRegPressure(*MRI, LISLR);
- if (LISPressure != CurPressure) {
+ if (LISPressure != CurVirtPressure) {
dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
- << print(CurPressure) << "LIS rpt: " << print(LISPressure);
+ << print(CurVirtPressure) << "LIS rpt: " << print(LISPressure);
return false;
}
return true;
}
-Printable llvm::print(const GCNRPTracker::LiveRegSet &LiveRegs,
+Printable llvm::print(const GCNRPTracker::LiveRegSet &VirtLiveRegs,
const MachineRegisterInfo &MRI) {
- return Printable([&LiveRegs, &MRI](raw_ostream &OS) {
+ return Printable([&VirtLiveRegs, &MRI](raw_ostream &OS) {
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I);
- auto It = LiveRegs.find(Reg);
- if (It != LiveRegs.end() && It->second.any())
+ auto It = VirtLiveRegs.find(Reg);
+ if (It != VirtLiveRegs.end() && It->second.any())
OS << ' ' << printReg(Reg, TRI) << ':' << PrintLaneMask(It->second);
}
OS << '\n';
@@ -1032,7 +1035,7 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
const char *RegName = GCNRegPressure::getName(Kind);
unsigned MaxNumRegs = 0;
- const MachineInstr *MaxPressureMI = nullptr;
+ const MachineInstr *MaxVirtPressureMI = nullptr;
GCNUpwardRPTracker RPT(LIS);
for (const MachineBasicBlock &MBB : MF) {
RPT.reset(MRI, LIS.getSlotIndexes()->getMBBEndIdx(&MBB).getPrevSlot());
@@ -1041,12 +1044,12 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
unsigned NumRegs = RPT.getMaxPressure().getNumRegs(Kind);
if (NumRegs > MaxNumRegs) {
MaxNumRegs = NumRegs;
- MaxPressureMI = &MI;
+ MaxVirtPressureMI = &MI;
}
}
}
- SlotIndex MISlot = LIS.getInstructionIndex(*MaxPressureMI);
+ SlotIndex MISlot = LIS.getInstructionIndex(*MaxVirtPressureMI);
// Max pressure can occur at either the early-clobber or register slot.
// Choose the maximum liveset between both slots. This is ugly but this is
@@ -1059,7 +1062,7 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
unsigned RNumRegs = getRegPressure(MRI, RLiveSet).getNumRegs(Kind);
GCNRPTracker::LiveRegSet *LiveSet =
ECNumRegs > RNumRegs ? &ECLiveSet : &RLiveSet;
- SlotIndex MaxPressureSlot = ECNumRegs > RNumRegs ? ECSlot : RSlot;
+ SlotIndex MaxVirtPressureSlot = ECNumRegs > RNumRegs ? ECSlot : RSlot;
assert(getRegPressure(MRI, *LiveSet).getNumRegs(Kind) == MaxNumRegs);
// Split live registers into single-def and multi-def sets.
@@ -1121,8 +1124,8 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
OS << "\n*** Register pressure info (" << RegName << "s) for " << MF.getName()
<< " ***\n";
OS << "Max pressure is " << MaxNumRegs << ' ' << RegName << "s at "
- << printLoc(MaxPressureMI->getParent(), MaxPressureSlot) << ": "
- << *MaxPressureMI;
+ << printLoc(MaxVirtPressureMI->getParent(), MaxVirtPressureSlot) << ": "
+ << *MaxVirtPressureMI;
OS << "\nLive registers with single definition (" << SDefNumRegs << ' '
<< RegName << "s):\n";
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.h b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
index 52064dca1c3af..4dba6a4e2d71d 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.h
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
@@ -320,14 +320,14 @@ class GCNRPTracker {
protected:
const LiveIntervals &LIS;
- LiveRegSet LiveRegs;
- GCNRegPressure CurPressure, MaxPressure;
+ LiveRegSet VirtLiveRegs;
+ GCNRegPressure CurVirtPressure, MaxVirtPressure;
const MachineInstr *LastTrackedMI = nullptr;
mutable const MachineRegisterInfo *MRI = nullptr;
GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
- void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy,
+ void reset(const MachineInstr &MI, const LiveRegSet *VirtLiveRegsCopy,
bool After);
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
@@ -337,18 +337,17 @@ class GCNRPTracker {
public:
// reset tracker and set live register set to the specified value.
- void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_);
+ void reset(const MachineRegisterInfo &MRInfo,
+ const LiveRegSet &VirtLiveRegsSet);
// live regs for the current state
- const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
+ const decltype(VirtLiveRegs) &getLiveRegs() const { return VirtLiveRegs; }
const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
- void clearMaxPressure() { MaxPressure.clear(); }
+ void clearMaxPressure() { MaxVirtPressure.clear(); }
- GCNRegPressure getPressure() const { return CurPressure; }
+ GCNRegPressure getPressure() const { return CurVirtPressure; }
- decltype(LiveRegs) moveLiveRegs() {
- return std::move(LiveRegs);
- }
+ decltype(VirtLiveRegs) moveLiveRegs() { return std::move(VirtLiveRegs); }
};
GCNRPTracker::LiveRegSet
@@ -361,7 +360,7 @@ getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
class GCNUpwardRPTracker : public GCNRPTracker {
public:
- GCNUpwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
+ GCNUpwardRPTracker(const LiveIntervals &LIS) : GCNRPTracker(LIS) {}
using GCNRPTracker::reset;
@@ -390,12 +389,12 @@ class GCNUpwardRPTracker : public GCNRPTracker {
/// to reported by LIS.
bool isValid() const;
- const GCNRegPressure &getMaxPressure() const { return MaxPressure; }
+ const GCNRegPressure &getMaxPressure() const { return MaxVirtPressure; }
- void resetMaxPressure() { MaxPressure = CurPressure; }
+ void resetMaxPressure() { MaxVirtPressure = CurVirtPressure; }
GCNRegPressure getMaxPressureAndReset() {
- GCNRegPressure RP = MaxPressure;
+ GCNRegPressure RP = MaxVirtPressure;
resetMaxPressure();
return RP;
}
@@ -419,15 +418,15 @@ class GCNDownwardRPTracker : public GCNRPTracker {
/// \p return MaxPressure and clear it.
GCNRegPressure moveMaxPressure() {
- auto Res = MaxPressure;
- MaxPressure.clear();
+ auto Res = MaxVirtPressure;
+ MaxVirtPressure.clear();
return Res;
}
/// Reset tracker to the point before the \p MI
- /// filling \p LiveRegs upon this point using LIS.
+ /// filling \p VirtLiveRegs upon this point using LIS.
/// \p returns false if block is empty except debug values.
- bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
+ bool reset(const MachineInstr &MI, const LiveRegSet *VirtLiveRegs = nullptr);
/// Move to the state right before the next MI or after the end of MBB.
/// \p returns false if reached end of the block.
@@ -464,10 +463,10 @@ class GCNDownwardRPTracker : public GCNRPTracker {
/// Reset to \p Begin and advance to \p End.
bool advance(MachineBasicBlock::const_iterator Begin,
MachineBasicBlock::const_iterator End,
- const LiveRegSet *LiveRegsCopy = nullptr);
+ const LiveRegSet *VirtLiveRegsCopy = nullptr);
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
- /// Calculate the impact \p MI will have on CurPressure and \return the
+ /// Calculate the impact \p MI will have on CurVirtPressure and \return the
/// speculated pressure. In order to support RP Speculation, this does not
/// rely on the implicit program ordering in the LiveIntervals.
GCNRegPressure bumpDownwardPressure(const MachineInstr *MI,
@@ -558,7 +557,7 @@ bool isEqual(const GCNRPTracker::LiveRegSet &S1,
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr,
unsigned DynamicVGPRBlockSize = 0);
-Printable print(const GCNRPTracker::LiveRegSet &LiveRegs,
+Printable print(const GCNRPTracker::LiveRegSet &VirtLiveRegs,
const MachineRegisterInfo &MRI);
Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 77c322eb3178e..8b548c609e759 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -3114,10 +3114,10 @@ void PreRARematStage::finalizeGCNSchedStage() {
}
// Revert re-scheduling in all affected regions.
- for (const auto &[RegionIdx, OrigMIOrder, MaxPressure] : RegionReverts) {
+ for (const auto &[RegionIdx, OrigMIOrder, MaxVirtPressure] : RegionReverts) {
REMAT_DEBUG(dbgs() << "Reverting re-scheduling in region " << RegionIdx
<< '\n');
- DAG.Pressure[RegionIdx] = MaxPressure;
+ DAG.Pressure[RegionIdx] = MaxVirtPressure;
modifyRegionSchedule(RegionIdx, RegionBB[RegionIdx], OrigMIOrder);
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 99fd55db33285..b28cdcffa5d64 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -703,12 +703,12 @@ class PreRARematStage : public GCNSchedStage {
/// Original instruction order (both debug and non-debug MIs).
std::vector<MachineInstr *> OrigMIOrder;
/// Maximum pressure recorded in the region.
- GCNRegPressure MaxPressure;
+ GCNRegPressure MaxVirtPressure;
RegionSchedRevert(unsigned RegionIdx, ArrayRef<MachineInstr *> OrigMIOrder,
- const GCNRegPressure &MaxPressure)
+ const GCNRegPressure &MaxVirtPressure)
: RegionIdx(RegionIdx), OrigMIOrder(OrigMIOrder),
- MaxPressure(MaxPressure) {}
+ MaxVirtPressure(MaxVirtPressure) {}
};
/// After re-scheduling, contains pre-re-scheduling data for all re-scheduled
/// regions.
>From f7bae175480318a88b259688beba8d1b43506e9d Mon Sep 17 00:00:00 2001
From: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: Thu, 23 Apr 2026 12:18:07 -0500
Subject: [PATCH 2/3] Remove virtual prefix from GCNPressure objects.
---
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 52 ++++++++++-----------
llvm/lib/Target/AMDGPU/GCNRegPressure.h | 18 +++----
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 4 +-
llvm/lib/Target/AMDGPU/GCNSchedStrategy.h | 6 +--
4 files changed, 39 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index 571ca3475305c..dcf8ee416eda0 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -519,7 +519,7 @@ void GCNRPTracker::reset(const MachineInstr &MI,
After ? getLiveRegsAfter(MI, LIS) : getLiveRegsBefore(MI, LIS);
}
- MaxVirtPressure = CurVirtPressure = getRegPressure(*MRI, VirtLiveRegs);
+ MaxPressure = CurPressure = getRegPressure(*MRI, VirtLiveRegs);
}
void GCNRPTracker::reset(const MachineRegisterInfo &MRInfo,
@@ -527,7 +527,7 @@ void GCNRPTracker::reset(const MachineRegisterInfo &MRInfo,
MRI = &MRInfo;
VirtLiveRegs = VirtLiveRegsSet;
LastTrackedMI = nullptr;
- MaxVirtPressure = CurVirtPressure = getRegPressure(MRInfo, VirtLiveRegsSet);
+ MaxPressure = CurPressure = getRegPressure(MRInfo, VirtLiveRegsSet);
}
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
@@ -575,16 +575,16 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
LaneBitmask &LiveMask = I->second;
LaneBitmask PrevMask = LiveMask;
LiveMask &= ~DefMask;
- CurVirtPressure.inc(Reg, PrevMask, LiveMask, *MRI);
+ CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
if (LiveMask.none())
VirtLiveRegs.erase(I);
}
- // Update MaxVirtPressure with defs pressure.
- DefPressure += CurVirtPressure;
+ // Update MaxPressure with defs pressure.
+ DefPressure += CurPressure;
if (HasECDefs)
DefPressure += ECDefPressure;
- MaxVirtPressure = max(DefPressure, MaxVirtPressure);
+ MaxPressure = max(DefPressure, MaxPressure);
// Make uses alive.
SmallVector<VRegMaskOrUnit, 8> RegUses;
@@ -593,15 +593,14 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
LaneBitmask &LiveMask = VirtLiveRegs[U.VRegOrUnit.asVirtualReg()];
LaneBitmask PrevMask = LiveMask;
LiveMask |= U.LaneMask;
- CurVirtPressure.inc(U.VRegOrUnit.asVirtualReg(), PrevMask, LiveMask, *MRI);
+ CurPressure.inc(U.VRegOrUnit.asVirtualReg(), PrevMask, LiveMask, *MRI);
}
- // Update MaxVirtPressure with uses plus early-clobber defs pressure.
- MaxVirtPressure = HasECDefs
- ? max(CurVirtPressure + ECDefPressure, MaxVirtPressure)
- : max(CurVirtPressure, MaxVirtPressure);
+ // Update MaxPressure with uses plus early-clobber defs pressure.
+ MaxPressure = HasECDefs ? max(CurPressure + ECDefPressure, MaxPressure)
+ : max(CurPressure, MaxPressure);
- assert(CurVirtPressure == getRegPressure(*MRI, VirtLiveRegs));
+ assert(CurPressure == getRegPressure(*MRI, VirtLiveRegs));
}
////////////////////////////////////////////////////////////////////////////////
@@ -665,7 +664,7 @@ bool GCNDownwardRPTracker::advanceBeforeNext(MachineInstr *MI,
}
auto PrevMask = It->second;
It->second &= ~S.LaneMask;
- CurVirtPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
+ CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
}
}
if (It != VirtLiveRegs.end() && It->second.none())
@@ -674,13 +673,12 @@ bool GCNDownwardRPTracker::advanceBeforeNext(MachineInstr *MI,
auto It = VirtLiveRegs.find(MO.getReg());
if (It == VirtLiveRegs.end())
llvm_unreachable("register isn't live");
- CurVirtPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(),
- *MRI);
+ CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
VirtLiveRegs.erase(It);
}
}
- MaxVirtPressure = max(MaxVirtPressure, CurVirtPressure);
+ MaxPressure = max(MaxPressure, CurPressure);
LastTrackedMI = nullptr;
@@ -706,10 +704,10 @@ void GCNDownwardRPTracker::advanceToNext(MachineInstr *MI,
auto &LiveMask = VirtLiveRegs[Reg];
auto PrevMask = LiveMask;
LiveMask |= getDefRegMask(MO, *MRI);
- CurVirtPressure.inc(Reg, PrevMask, LiveMask, *MRI);
+ CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
}
- MaxVirtPressure = max(MaxVirtPressure, CurVirtPressure);
+ MaxPressure = max(MaxPressure, CurPressure);
}
bool GCNDownwardRPTracker::advance(MachineInstr *MI, bool UseInternalIterator) {
@@ -775,7 +773,7 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, *MRI, true, /*IgnoreDead=*/false);
RegOpers.adjustLaneLiveness(LIS, *MRI, SlotIdx);
- GCNRegPressure TempPressure = CurVirtPressure;
+ GCNRegPressure TempPressure = CurPressure;
for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
if (!Use.VRegOrUnit.isVirtualReg())
@@ -840,9 +838,9 @@ bool GCNUpwardRPTracker::isValid() const {
}
auto LISPressure = getRegPressure(*MRI, LISLR);
- if (LISPressure != CurVirtPressure) {
+ if (LISPressure != CurPressure) {
dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
- << print(CurVirtPressure) << "LIS rpt: " << print(LISPressure);
+ << print(CurPressure) << "LIS rpt: " << print(LISPressure);
return false;
}
return true;
@@ -1035,7 +1033,7 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
const char *RegName = GCNRegPressure::getName(Kind);
unsigned MaxNumRegs = 0;
- const MachineInstr *MaxVirtPressureMI = nullptr;
+ const MachineInstr *MaxPressureMI = nullptr;
GCNUpwardRPTracker RPT(LIS);
for (const MachineBasicBlock &MBB : MF) {
RPT.reset(MRI, LIS.getSlotIndexes()->getMBBEndIdx(&MBB).getPrevSlot());
@@ -1044,12 +1042,12 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
unsigned NumRegs = RPT.getMaxPressure().getNumRegs(Kind);
if (NumRegs > MaxNumRegs) {
MaxNumRegs = NumRegs;
- MaxVirtPressureMI = &MI;
+ MaxPressureMI = &MI;
}
}
}
- SlotIndex MISlot = LIS.getInstructionIndex(*MaxVirtPressureMI);
+ SlotIndex MISlot = LIS.getInstructionIndex(*MaxPressureMI);
// Max pressure can occur at either the early-clobber or register slot.
// Choose the maximum liveset between both slots. This is ugly but this is
@@ -1062,7 +1060,7 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
unsigned RNumRegs = getRegPressure(MRI, RLiveSet).getNumRegs(Kind);
GCNRPTracker::LiveRegSet *LiveSet =
ECNumRegs > RNumRegs ? &ECLiveSet : &RLiveSet;
- SlotIndex MaxVirtPressureSlot = ECNumRegs > RNumRegs ? ECSlot : RSlot;
+ SlotIndex MaxPressureSlot = ECNumRegs > RNumRegs ? ECSlot : RSlot;
assert(getRegPressure(MRI, *LiveSet).getNumRegs(Kind) == MaxNumRegs);
// Split live registers into single-def and multi-def sets.
@@ -1124,8 +1122,8 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
OS << "\n*** Register pressure info (" << RegName << "s) for " << MF.getName()
<< " ***\n";
OS << "Max pressure is " << MaxNumRegs << ' ' << RegName << "s at "
- << printLoc(MaxVirtPressureMI->getParent(), MaxVirtPressureSlot) << ": "
- << *MaxVirtPressureMI;
+ << printLoc(MaxPressureMI->getParent(), MaxPressureSlot) << ": "
+ << *MaxPressureMI;
OS << "\nLive registers with single definition (" << SDefNumRegs << ' '
<< RegName << "s):\n";
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.h b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
index 4dba6a4e2d71d..9ebab3f34c8aa 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.h
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
@@ -321,7 +321,7 @@ class GCNRPTracker {
protected:
const LiveIntervals &LIS;
LiveRegSet VirtLiveRegs;
- GCNRegPressure CurVirtPressure, MaxVirtPressure;
+ GCNRegPressure CurPressure, MaxPressure;
const MachineInstr *LastTrackedMI = nullptr;
mutable const MachineRegisterInfo *MRI = nullptr;
@@ -343,9 +343,9 @@ class GCNRPTracker {
const decltype(VirtLiveRegs) &getLiveRegs() const { return VirtLiveRegs; }
const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
- void clearMaxPressure() { MaxVirtPressure.clear(); }
+ void clearMaxPressure() { MaxPressure.clear(); }
- GCNRegPressure getPressure() const { return CurVirtPressure; }
+ GCNRegPressure getPressure() const { return CurPressure; }
decltype(VirtLiveRegs) moveLiveRegs() { return std::move(VirtLiveRegs); }
};
@@ -389,12 +389,12 @@ class GCNUpwardRPTracker : public GCNRPTracker {
/// to reported by LIS.
bool isValid() const;
- const GCNRegPressure &getMaxPressure() const { return MaxVirtPressure; }
+ const GCNRegPressure &getMaxPressure() const { return MaxPressure; }
- void resetMaxPressure() { MaxVirtPressure = CurVirtPressure; }
+ void resetMaxPressure() { MaxPressure = CurPressure; }
GCNRegPressure getMaxPressureAndReset() {
- GCNRegPressure RP = MaxVirtPressure;
+ GCNRegPressure RP = MaxPressure;
resetMaxPressure();
return RP;
}
@@ -418,8 +418,8 @@ class GCNDownwardRPTracker : public GCNRPTracker {
/// \p return MaxPressure and clear it.
GCNRegPressure moveMaxPressure() {
- auto Res = MaxVirtPressure;
- MaxVirtPressure.clear();
+ auto Res = MaxPressure;
+ MaxPressure.clear();
return Res;
}
@@ -466,7 +466,7 @@ class GCNDownwardRPTracker : public GCNRPTracker {
const LiveRegSet *VirtLiveRegsCopy = nullptr);
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
- /// Calculate the impact \p MI will have on CurVirtPressure and \return the
+ /// Calculate the impact \p MI will have on CurPressure and \return the
/// speculated pressure. In order to support RP Speculation, this does not
/// rely on the implicit program ordering in the LiveIntervals.
GCNRegPressure bumpDownwardPressure(const MachineInstr *MI,
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 8b548c609e759..77c322eb3178e 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -3114,10 +3114,10 @@ void PreRARematStage::finalizeGCNSchedStage() {
}
// Revert re-scheduling in all affected regions.
- for (const auto &[RegionIdx, OrigMIOrder, MaxVirtPressure] : RegionReverts) {
+ for (const auto &[RegionIdx, OrigMIOrder, MaxPressure] : RegionReverts) {
REMAT_DEBUG(dbgs() << "Reverting re-scheduling in region " << RegionIdx
<< '\n');
- DAG.Pressure[RegionIdx] = MaxVirtPressure;
+ DAG.Pressure[RegionIdx] = MaxPressure;
modifyRegionSchedule(RegionIdx, RegionBB[RegionIdx], OrigMIOrder);
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index b28cdcffa5d64..99fd55db33285 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -703,12 +703,12 @@ class PreRARematStage : public GCNSchedStage {
/// Original instruction order (both debug and non-debug MIs).
std::vector<MachineInstr *> OrigMIOrder;
/// Maximum pressure recorded in the region.
- GCNRegPressure MaxVirtPressure;
+ GCNRegPressure MaxPressure;
RegionSchedRevert(unsigned RegionIdx, ArrayRef<MachineInstr *> OrigMIOrder,
- const GCNRegPressure &MaxVirtPressure)
+ const GCNRegPressure &MaxPressure)
: RegionIdx(RegionIdx), OrigMIOrder(OrigMIOrder),
- MaxVirtPressure(MaxVirtPressure) {}
+ MaxPressure(MaxPressure) {}
};
/// After re-scheduling, contains pre-re-scheduling data for all re-scheduled
/// regions.
>From 553115f0b684f817d0df381854ae70e7e2403a1a Mon Sep 17 00:00:00 2001
From: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: Fri, 12 Jun 2026 10:08:09 -0500
Subject: [PATCH 3/3] Renamed members and local vars to include Virt prefix.
---
.../Target/AMDGPU/GCNIterativeScheduler.cpp | 8 +-
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 60 +++++-----
llvm/lib/Target/AMDGPU/GCNRegPressure.h | 36 +++---
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 107 +++++++++---------
llvm/lib/Target/AMDGPU/GCNSchedStrategy.h | 23 ++--
.../lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 2 +-
6 files changed, 121 insertions(+), 115 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
index dff153cebdd4c..f2e91e9c1be70 100644
--- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
@@ -80,12 +80,12 @@ static void printLivenessInfo(raw_ostream &OS,
auto *const BB = Begin->getParent();
const auto &MRI = BB->getParent()->getRegInfo();
- const auto LiveIns = getLiveRegsBefore(*Begin, *LIS);
- OS << "LIn RP: " << print(getRegPressure(MRI, LiveIns));
+ const auto LiveIns = getVirtLiveRegsBefore(*Begin, *LIS);
+ OS << "LIn RP: " << print(getVirtRegPressure(MRI, LiveIns));
const auto BottomMI = End == BB->end() ? std::prev(End) : End;
- const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS);
- OS << "LOt RP: " << print(getRegPressure(MRI, LiveOuts));
+ const auto LiveOuts = getVirtLiveRegsAfter(*BottomMI, *LIS);
+ OS << "LOt RP: " << print(getVirtRegPressure(MRI, LiveOuts));
}
LLVM_DUMP_METHOD
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index dcf8ee416eda0..c05e37ed44f4e 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -488,10 +488,10 @@ LaneBitmask llvm::getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
return LiveMask;
}
-GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
- const LiveIntervals &LIS,
- const MachineRegisterInfo &MRI,
- GCNRegPressure::RegKind RegKind) {
+GCNRPTracker::LiveRegSet
+llvm::getVirtLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
+ const MachineRegisterInfo &MRI,
+ GCNRegPressure::RegKind RegKind) {
GCNRPTracker::LiveRegSet VirtLiveRegs;
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
auto Reg = Register::index2VirtReg(I);
@@ -516,10 +516,10 @@ void GCNRPTracker::reset(const MachineInstr &MI,
VirtLiveRegs = *VirtLiveRegsCopy;
} else {
VirtLiveRegs =
- After ? getLiveRegsAfter(MI, LIS) : getLiveRegsBefore(MI, LIS);
+ After ? getVirtLiveRegsAfter(MI, LIS) : getVirtLiveRegsBefore(MI, LIS);
}
- MaxPressure = CurPressure = getRegPressure(*MRI, VirtLiveRegs);
+ MaxPressure = CurPressure = getVirtRegPressure(*MRI, VirtLiveRegs);
}
void GCNRPTracker::reset(const MachineRegisterInfo &MRInfo,
@@ -527,7 +527,7 @@ void GCNRPTracker::reset(const MachineRegisterInfo &MRInfo,
MRI = &MRInfo;
VirtLiveRegs = VirtLiveRegsSet;
LastTrackedMI = nullptr;
- MaxPressure = CurPressure = getRegPressure(MRInfo, VirtLiveRegsSet);
+ MaxPressure = CurPressure = getVirtRegPressure(MRInfo, VirtLiveRegsSet);
}
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
@@ -600,7 +600,7 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
MaxPressure = HasECDefs ? max(CurPressure + ECDefPressure, MaxPressure)
: max(CurPressure, MaxPressure);
- assert(CurPressure == getRegPressure(*MRI, VirtLiveRegs));
+ assert(CurPressure == getVirtRegPressure(*MRI, VirtLiveRegs));
}
////////////////////////////////////////////////////////////////////////////////
@@ -826,7 +826,7 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
bool GCNUpwardRPTracker::isValid() const {
const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
- const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
+ const auto LISLR = llvm::getVirtLiveRegs(SI, LIS, *MRI);
const auto &TrackedLR = VirtLiveRegs;
if (!isEqual(LISLR, TrackedLR)) {
@@ -837,7 +837,7 @@ bool GCNUpwardRPTracker::isValid() const {
return false;
}
- auto LISPressure = getRegPressure(*MRI, LISLR);
+ auto LISPressure = getVirtRegPressure(*MRI, LISLR);
if (LISPressure != CurPressure) {
dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
<< print(CurPressure) << "LIS rpt: " << print(LISPressure);
@@ -941,18 +941,18 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
SlotIndex MBBStartSlot = LIS.getSlotIndexes()->getMBBStartIdx(&MBB);
SlotIndex MBBLastSlot = LIS.getSlotIndexes()->getMBBLastIdx(&MBB);
- GCNRPTracker::LiveRegSet LiveIn, LiveOut;
+ GCNRPTracker::LiveRegSet VirtLiveIn, VirtLiveOut;
GCNRegPressure RPAtMBBEnd;
if (UseDownwardTracker) {
if (MBB.empty()) {
- LiveIn = LiveOut = getLiveRegs(MBBStartSlot, LIS, MRI);
- RPAtMBBEnd = getRegPressure(MRI, LiveIn);
+ VirtLiveIn = VirtLiveOut = getVirtLiveRegs(MBBStartSlot, LIS, MRI);
+ RPAtMBBEnd = getVirtRegPressure(MRI, VirtLiveIn);
} else {
GCNDownwardRPTracker RPT(LIS);
RPT.reset(MBB.front());
- LiveIn = RPT.getLiveRegs();
+ VirtLiveIn = RPT.getVirtLiveRegs();
while (!RPT.advanceBeforeNext()) {
GCNRegPressure RPBeforeMI = RPT.getPressure();
@@ -960,14 +960,14 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
RP.emplace_back(RPBeforeMI, RPT.getPressure());
}
- LiveOut = RPT.getLiveRegs();
+ VirtLiveOut = RPT.getVirtLiveRegs();
RPAtMBBEnd = RPT.getPressure();
}
} else {
GCNUpwardRPTracker RPT(LIS);
RPT.reset(MRI, MBBLastSlot);
- LiveOut = RPT.getLiveRegs();
+ VirtLiveOut = RPT.getVirtLiveRegs();
RPAtMBBEnd = RPT.getPressure();
for (auto &MI : reverse(MBB)) {
@@ -977,12 +977,13 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
RP.emplace_back(RPT.getPressure(), RPT.getMaxPressure());
}
- LiveIn = RPT.getLiveRegs();
+ VirtLiveIn = RPT.getVirtLiveRegs();
}
- OS << PFX " Live-in: " << llvm::print(LiveIn, MRI);
+ OS << PFX " Live-in: " << llvm::print(VirtLiveIn, MRI);
if (!UseDownwardTracker)
- ReportLISMismatchIfAny(LiveIn, getLiveRegs(MBBStartSlot, LIS, MRI));
+ ReportLISMismatchIfAny(VirtLiveIn,
+ getVirtLiveRegs(MBBStartSlot, LIS, MRI));
OS << PFX " SGPR VGPR\n";
int I = 0;
@@ -998,13 +999,14 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
}
OS << printRP(RPAtMBBEnd) << '\n';
- OS << PFX " Live-out:" << llvm::print(LiveOut, MRI);
+ OS << PFX " Live-out:" << llvm::print(VirtLiveOut, MRI);
if (UseDownwardTracker)
- ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBLastSlot, LIS, MRI));
+ ReportLISMismatchIfAny(VirtLiveOut,
+ getVirtLiveRegs(MBBLastSlot, LIS, MRI));
GCNRPTracker::LiveRegSet LiveThrough;
- for (auto [Reg, Mask] : LiveIn) {
- LaneBitmask MaskIntersection = Mask & LiveOut.lookup(Reg);
+ for (auto [Reg, Mask] : VirtLiveIn) {
+ LaneBitmask MaskIntersection = Mask & VirtLiveOut.lookup(Reg);
if (MaskIntersection.any()) {
LaneBitmask LTMask = getRegLiveThroughMask(
MRI, LIS, Reg, MBBStartSlot, MBBLastSlot, MaskIntersection);
@@ -1013,7 +1015,7 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
}
}
OS << PFX " Live-thr:" << llvm::print(LiveThrough, MRI);
- OS << printRP(getRegPressure(MRI, LiveThrough)) << '\n';
+ OS << printRP(getVirtRegPressure(MRI, LiveThrough)) << '\n';
}
OS << "...\n";
return false;
@@ -1054,14 +1056,14 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
// diagnostic code.
SlotIndex ECSlot = MISlot.getRegSlot(true);
SlotIndex RSlot = MISlot.getRegSlot(false);
- GCNRPTracker::LiveRegSet ECLiveSet = getLiveRegs(ECSlot, LIS, MRI, Kind);
- GCNRPTracker::LiveRegSet RLiveSet = getLiveRegs(RSlot, LIS, MRI, Kind);
- unsigned ECNumRegs = getRegPressure(MRI, ECLiveSet).getNumRegs(Kind);
- unsigned RNumRegs = getRegPressure(MRI, RLiveSet).getNumRegs(Kind);
+ GCNRPTracker::LiveRegSet ECLiveSet = getVirtLiveRegs(ECSlot, LIS, MRI, Kind);
+ GCNRPTracker::LiveRegSet RLiveSet = getVirtLiveRegs(RSlot, LIS, MRI, Kind);
+ unsigned ECNumRegs = getVirtRegPressure(MRI, ECLiveSet).getNumRegs(Kind);
+ unsigned RNumRegs = getVirtRegPressure(MRI, RLiveSet).getNumRegs(Kind);
GCNRPTracker::LiveRegSet *LiveSet =
ECNumRegs > RNumRegs ? &ECLiveSet : &RLiveSet;
SlotIndex MaxPressureSlot = ECNumRegs > RNumRegs ? ECSlot : RSlot;
- assert(getRegPressure(MRI, *LiveSet).getNumRegs(Kind) == MaxNumRegs);
+ assert(getVirtRegPressure(MRI, *LiveSet).getNumRegs(Kind) == MaxNumRegs);
// Split live registers into single-def and multi-def sets.
GCNRegPressure SDefPressure, MDefPressure;
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.h b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
index 9ebab3f34c8aa..d7aff50822b50 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.h
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
@@ -340,20 +340,20 @@ class GCNRPTracker {
void reset(const MachineRegisterInfo &MRInfo,
const LiveRegSet &VirtLiveRegsSet);
// live regs for the current state
- const decltype(VirtLiveRegs) &getLiveRegs() const { return VirtLiveRegs; }
+ const decltype(VirtLiveRegs) &getVirtLiveRegs() const { return VirtLiveRegs; }
const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
void clearMaxPressure() { MaxPressure.clear(); }
GCNRegPressure getPressure() const { return CurPressure; }
- decltype(VirtLiveRegs) moveLiveRegs() { return std::move(VirtLiveRegs); }
+ decltype(VirtLiveRegs) moveVirtLiveRegs() { return std::move(VirtLiveRegs); }
};
GCNRPTracker::LiveRegSet
-getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
- const MachineRegisterInfo &MRI,
- GCNRegPressure::RegKind RegKind = GCNRegPressure::TOTAL_KINDS);
+getVirtLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
+ const MachineRegisterInfo &MRI,
+ GCNRegPressure::RegKind RegKind = GCNRegPressure::TOTAL_KINDS);
////////////////////////////////////////////////////////////////////////////////
// GCNUpwardRPTracker
@@ -366,7 +366,7 @@ class GCNUpwardRPTracker : public GCNRPTracker {
/// reset tracker at the specified slot index \p SI.
void reset(const MachineRegisterInfo &MRI, SlotIndex SI) {
- GCNRPTracker::reset(MRI, llvm::getLiveRegs(SI, LIS, MRI));
+ GCNRPTracker::reset(MRI, llvm::getVirtLiveRegs(SI, LIS, MRI));
}
/// reset tracker to the end of the \p MBB.
@@ -492,8 +492,8 @@ LaneBitmask getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
/// Note: there is no entry in the map for instructions with empty live reg set
/// Complexity = O(NumVirtRegs * averageLiveRangeSegmentsPerReg * lg(R))
template <typename Range>
-DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
-getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
+DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
+getVirtLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
std::vector<SlotIndex> Indexes;
Indexes.reserve(llvm::size(R));
auto &SII = *LIS.getSlotIndexes();
@@ -530,21 +530,21 @@ getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
return LiveRegMap;
}
-inline GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI,
- const LiveIntervals &LIS) {
- return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
- MI.getMF()->getRegInfo());
+inline GCNRPTracker::LiveRegSet getVirtLiveRegsAfter(const MachineInstr &MI,
+ const LiveIntervals &LIS) {
+ return getVirtLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
+ MI.getMF()->getRegInfo());
}
-inline GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI,
- const LiveIntervals &LIS) {
- return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
- MI.getMF()->getRegInfo());
+inline GCNRPTracker::LiveRegSet
+getVirtLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS) {
+ return getVirtLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
+ MI.getMF()->getRegInfo());
}
template <typename Range>
-GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
- Range &&LiveRegs) {
+GCNRegPressure getVirtRegPressure(const MachineRegisterInfo &MRI,
+ Range &&LiveRegs) {
GCNRegPressure Res;
for (const auto &RM : LiveRegs)
Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 77c322eb3178e..ad7104ceb0305 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -940,7 +940,7 @@ GCNScheduleDAGMILive::GCNScheduleDAGMILive(
: ScheduleDAGMILive(C, std::move(S)), ST(MF.getSubtarget<GCNSubtarget>()),
MFI(*MF.getInfo<SIMachineFunctionInfo>()),
StartingOccupancy(MFI.getOccupancy()), MinOccupancy(StartingOccupancy),
- RegionLiveOuts(this, /*IsLiveOut=*/true) {
+ RegionVirtLiveOuts(this, /*IsLiveOut=*/true) {
// We want regions with a single MI to be scheduled so that we can reason
// about them correctly during scheduling stages that move MIs between regions
@@ -987,10 +987,10 @@ void GCNScheduleDAGMILive::schedule() {
GCNRegPressure
GCNScheduleDAGMILive::getRealRegPressure(unsigned RegionIdx) const {
if (Regions[RegionIdx].first == Regions[RegionIdx].second)
- return llvm::getRegPressure(MRI, LiveIns[RegionIdx]);
+ return llvm::getVirtRegPressure(MRI, VirtLiveIns[RegionIdx]);
GCNDownwardRPTracker RPTracker(*LIS);
RPTracker.advance(Regions[RegionIdx].first, Regions[RegionIdx].second,
- &LiveIns[RegionIdx]);
+ &VirtLiveIns[RegionIdx]);
return RPTracker.moveMaxPressure();
}
@@ -1030,27 +1030,27 @@ void GCNScheduleDAGMILive::computeBlockPressure(unsigned RegionIdx,
--CurRegion;
auto I = MBB->begin();
- auto LiveInIt = MBBLiveIns.find(MBB);
+ auto VirtLiveInIt = MBBVirtLiveIns.find(MBB);
auto &Rgn = Regions[CurRegion];
auto *NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second);
- if (LiveInIt != MBBLiveIns.end()) {
- auto LiveIn = std::move(LiveInIt->second);
- RPTracker.reset(*MBB->begin(), &LiveIn);
- MBBLiveIns.erase(LiveInIt);
+ if (VirtLiveInIt != MBBVirtLiveIns.end()) {
+ auto VirtLiveIn = std::move(VirtLiveInIt->second);
+ RPTracker.reset(*MBB->begin(), &VirtLiveIn);
+ MBBVirtLiveIns.erase(VirtLiveInIt);
} else {
I = Rgn.first;
- auto LRS = BBLiveInMap.lookup(NonDbgMI);
+ auto VirtLiveInSet = BBVirtLiveInMap.lookup(NonDbgMI);
#ifdef EXPENSIVE_CHECKS
- assert(isEqual(getLiveRegsBefore(*NonDbgMI, *LIS), LRS));
+ assert(isEqual(getVirtLiveRegsBefore(*NonDbgMI, *LIS), VirtLiveInSet));
#endif
- RPTracker.reset(*I, &LRS);
+ RPTracker.reset(*I, &VirtLiveInSet);
}
for (;;) {
I = RPTracker.getNext();
if (Regions[CurRegion].first == I || NonDbgMI == I) {
- LiveIns[CurRegion] = RPTracker.getLiveRegs();
+ VirtLiveIns[CurRegion] = RPTracker.getVirtLiveRegs();
RPTracker.clearMaxPressure();
}
@@ -1071,12 +1071,12 @@ void GCNScheduleDAGMILive::computeBlockPressure(unsigned RegionIdx,
RPTracker.advanceToNext();
RPTracker.advance(MBB->end());
}
- MBBLiveIns[OnlySucc] = RPTracker.moveLiveRegs();
+ MBBVirtLiveIns[OnlySucc] = RPTracker.moveVirtLiveRegs();
}
}
DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
-GCNScheduleDAGMILive::getRegionLiveInMap() const {
+GCNScheduleDAGMILive::getRegionVirtLiveInMap() const {
assert(!Regions.empty());
std::vector<MachineInstr *> RegionFirstMIs;
RegionFirstMIs.reserve(Regions.size());
@@ -1084,11 +1084,11 @@ GCNScheduleDAGMILive::getRegionLiveInMap() const {
RegionFirstMIs.push_back(
&*skipDebugInstructionsForward(RegionBegin, RegionEnd));
- return getLiveRegMap(RegionFirstMIs, /*After=*/false, *LIS);
+ return getVirtLiveRegMap(RegionFirstMIs, /*After=*/false, *LIS);
}
DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
-GCNScheduleDAGMILive::getRegionLiveOutMap() const {
+GCNScheduleDAGMILive::getRegionVirtLiveOutMap() const {
assert(!Regions.empty());
std::vector<MachineInstr *> RegionLastMIs;
RegionLastMIs.reserve(Regions.size());
@@ -1098,14 +1098,14 @@ GCNScheduleDAGMILive::getRegionLiveOutMap() const {
continue;
RegionLastMIs.push_back(getLastMIForRegion(RegionBegin, RegionEnd));
}
- return getLiveRegMap(RegionLastMIs, /*After=*/true, *LIS);
+ return getVirtLiveRegMap(RegionLastMIs, /*After=*/true, *LIS);
}
-void RegionPressureMap::buildLiveRegMap() {
+void RegionPressureMap::buildVirtLiveRegMap() {
IdxToInstruction.clear();
- RegionLiveRegMap =
- IsLiveOut ? DAG->getRegionLiveOutMap() : DAG->getRegionLiveInMap();
+ RegionVirtLiveRegMap = IsLiveOut ? DAG->getRegionVirtLiveOutMap()
+ : DAG->getRegionVirtLiveInMap();
for (unsigned I = 0; I < DAG->Regions.size(); I++) {
auto &[RegionBegin, RegionEnd] = DAG->Regions[I];
// Skip empty regions.
@@ -1121,7 +1121,7 @@ void GCNScheduleDAGMILive::finalizeSchedule() {
// Start actual scheduling here. This function is called by the base
// MachineScheduler after all regions have been recorded by
// GCNScheduleDAGMILive::schedule().
- LiveIns.resize(Regions.size());
+ VirtLiveIns.resize(Regions.size());
Pressure.resize(Regions.size());
RegionsWithHighRP.resize(Regions.size());
RegionsWithExcessRP.resize(Regions.size());
@@ -1137,9 +1137,9 @@ void GCNScheduleDAGMILive::runSchedStages() {
LLVM_DEBUG(dbgs() << "All regions recorded, starting actual scheduling.\n");
if (!Regions.empty()) {
- BBLiveInMap = getRegionLiveInMap();
+ BBVirtLiveInMap = getRegionVirtLiveInMap();
if (GCNTrackers)
- RegionLiveOuts.buildLiveRegMap();
+ RegionVirtLiveOuts.buildVirtLiveRegMap();
}
#ifdef DUMP_MAX_REG_PRESSURE
@@ -1169,13 +1169,13 @@ void GCNScheduleDAGMILive::runSchedStages() {
if (GCNTrackers) {
GCNDownwardRPTracker *DownwardTracker = S.getDownwardTracker();
GCNUpwardRPTracker *UpwardTracker = S.getUpwardTracker();
- GCNRPTracker::LiveRegSet *RegionLiveIns =
- &LiveIns[Stage->getRegionIdx()];
+ GCNRPTracker::LiveRegSet *RegionVirtLiveIns =
+ &VirtLiveIns[Stage->getRegionIdx()];
reinterpret_cast<GCNRPTracker *>(DownwardTracker)
- ->reset(MRI, *RegionLiveIns);
+ ->reset(MRI, *RegionVirtLiveIns);
reinterpret_cast<GCNRPTracker *>(UpwardTracker)
- ->reset(MRI, RegionLiveOuts.getLiveRegsForRegionIdx(
+ ->reset(MRI, RegionVirtLiveOuts.getVirtLiveRegsForRegionIdx(
Stage->getRegionIdx()));
}
@@ -1405,9 +1405,9 @@ Printable PreRARematStage::ScoredRemat::print() const {
#endif
bool PreRARematStage::initGCNSchedStage() {
- // FIXME: This pass will invalidate cached BBLiveInMap and MBBLiveIns for
- // regions inbetween the defs and region we sinked the def to. Will need to be
- // fixed if there is another pass after this pass.
+ // FIXME: This pass will invalidate cached BBVirtLiveInMap and MBBVirtLiveIns
+ // for regions inbetween the defs and region we sinked the def to. Will need
+ // to be fixed if there is another pass after this pass.
assert(!S.hasNextStage());
if (!GCNSchedStage::initGCNSchedStage() || DAG.Regions.size() <= 1)
@@ -1712,12 +1712,12 @@ bool GCNSchedStage::initGCNRegion() {
PressureBefore = DAG.Pressure[RegionIdx];
- LLVM_DEBUG(
- dbgs() << "Pressure before scheduling:\nRegion live-ins:"
- << print(DAG.LiveIns[RegionIdx], DAG.MRI)
- << "Region live-in pressure: "
- << print(llvm::getRegPressure(DAG.MRI, DAG.LiveIns[RegionIdx]))
- << "Region register pressure: " << print(PressureBefore));
+ LLVM_DEBUG(dbgs() << "Pressure before scheduling:\nRegion live-ins:"
+ << print(DAG.VirtLiveIns[RegionIdx], DAG.MRI)
+ << "Region live-in pressure: "
+ << print(llvm::getVirtRegPressure(
+ DAG.MRI, DAG.VirtLiveIns[RegionIdx]))
+ << "Region register pressure: " << print(PressureBefore));
S.HasHighPressure = false;
S.KnownExcessRP = isRegionWithExcessRP();
@@ -2724,11 +2724,12 @@ bool RewriteMFMAFormStage::rewrite(
// Bulk update the LIS.
DAG.LIS->reanalyze(DAG.MF);
// Liveins may have been modified for cross RC copies
- RegionPressureMap LiveInUpdater(&DAG, false);
- LiveInUpdater.buildLiveRegMap();
+ RegionPressureMap VirtLiveInUpdater(&DAG, false);
+ VirtLiveInUpdater.buildVirtLiveRegMap();
for (unsigned Region = 0; Region < DAG.Regions.size(); Region++)
- DAG.LiveIns[Region] = LiveInUpdater.getLiveRegsForRegionIdx(Region);
+ DAG.VirtLiveIns[Region] =
+ VirtLiveInUpdater.getVirtLiveRegsForRegionIdx(Region);
DAG.Pressure[RegionIdx] = DAG.getRealRegPressure(RegionIdx);
@@ -2779,7 +2780,7 @@ bool PreRARematStage::collectRematRegs(
const DenseMap<MachineInstr *, unsigned> &MIRegion) {
// We need up-to-date live-out info. to query live-out register masks in
// regions containing rematerializable instructions.
- DAG.RegionLiveOuts.buildLiveRegMap();
+ DAG.RegionVirtLiveOuts.buildVirtLiveRegMap();
// Set of registers already marked for potential remterialization; used to
// avoid rematerialization chains.
@@ -2853,16 +2854,18 @@ PreRARematStage::RematReg::RematReg(
// Mark regions in which the rematerializable register is live.
Register Reg = getReg();
for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) {
- auto LiveInIt = DAG.LiveIns[I].find(Reg);
- if (LiveInIt != DAG.LiveIns[I].end())
+ auto VirtLiveInIt = DAG.VirtLiveIns[I].find(Reg);
+ if (VirtLiveInIt != DAG.VirtLiveIns[I].end())
LiveIn.set(I);
- const auto &LiveOuts = DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I);
- if (auto LiveOutIt = LiveOuts.find(Reg); LiveOutIt != LiveOuts.end())
+ const auto &VirtLiveOuts =
+ DAG.RegionVirtLiveOuts.getVirtLiveRegsForRegionIdx(I);
+ if (auto VirtLiveOutIt = VirtLiveOuts.find(Reg);
+ VirtLiveOutIt != VirtLiveOuts.end())
LiveOut.set(I);
}
Live |= LiveIn;
Live |= LiveOut;
- Mask = DAG.RegionLiveOuts.getLiveRegsForRegionIdx(DefRegion).at(Reg);
+ Mask = DAG.RegionVirtLiveOuts.getVirtLiveRegsForRegionIdx(DefRegion).at(Reg);
}
bool PreRARematStage::RematReg::maybeBeneficial(
@@ -3003,9 +3006,9 @@ MachineInstr *PreRARematStage::ScoredRemat::rematerialize(
if (LI.hasSubRanges() && MO.getSubReg())
LM = DAG.TRI->getSubRegIndexLaneMask(MO.getSubReg());
- LaneBitmask LiveInMask = DAG.LiveIns[Remat->UseRegion].at(UseReg);
- LaneBitmask UncoveredLanes = LM & ~(LiveInMask & LM);
- // If this register has lanes not covered by the LiveIns, be sure they
+ LaneBitmask VirtLiveInMask = DAG.VirtLiveIns[Remat->UseRegion].at(UseReg);
+ LaneBitmask UncoveredLanes = LM & ~(VirtLiveInMask & LM);
+ // If this register has lanes not covered by the VirtLiveIns, be sure they
// do not map to any subrange. ref:
// machine-scheduler-sink-trivial-remats.mir::omitted_subrange
if (UncoveredLanes.any()) {
@@ -3022,8 +3025,8 @@ MachineInstr *PreRARematStage::ScoredRemat::rematerialize(
// where the register is live.
for (unsigned I : Remat->Live.set_bits()) {
RPTargets[I].saveRP(RPSave);
- DAG.LiveIns[I].erase(Reg);
- DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I).erase(Reg);
+ DAG.VirtLiveIns[I].erase(Reg);
+ DAG.RegionVirtLiveOuts.getVirtLiveRegsForRegionIdx(I).erase(Reg);
if (!Remat->isUnusedLiveThrough(I))
RecomputeRP.set(I);
}
@@ -3151,9 +3154,9 @@ void PreRARematStage::finalizeGCNSchedStage() {
// to be one in.
std::pair<Register, LaneBitmask> LiveReg(OriginalReg, Remat->Mask);
for (unsigned I : Remat->LiveIn.set_bits())
- DAG.LiveIns[I].insert(LiveReg);
+ DAG.VirtLiveIns[I].insert(LiveReg);
for (unsigned I : Remat->LiveOut.set_bits())
- DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I).insert(LiveReg);
+ DAG.RegionVirtLiveOuts.getVirtLiveRegsForRegionIdx(I).insert(LiveReg);
RecomputeRP |= Rollback.Remat->Live;
// Regenerate intervals for all register operands of rematerialized MIs as
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 99fd55db33285..968f81b60e25c 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -213,7 +213,7 @@ class RegionPressureMap {
GCNScheduleDAGMILive *DAG;
// The live in/out pressure as indexed by the first or last MI in the region
// before scheduling.
- DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> RegionLiveRegMap;
+ DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> RegionVirtLiveRegMap;
// The mapping of RegionIDx to key instruction
DenseMap<unsigned, MachineInstr *> IdxToInstruction;
// Whether we are calculating LiveOuts or LiveIns
@@ -224,13 +224,13 @@ class RegionPressureMap {
RegionPressureMap(GCNScheduleDAGMILive *GCNDAG, bool LiveOut)
: DAG(GCNDAG), IsLiveOut(LiveOut) {}
// Build the Instr->LiveReg and RegionIdx->Instr maps
- void buildLiveRegMap();
+ void buildVirtLiveRegMap();
// Retrieve the LiveReg for a given RegionIdx
- GCNRPTracker::LiveRegSet &getLiveRegsForRegionIdx(unsigned RegionIdx) {
+ GCNRPTracker::LiveRegSet &getVirtLiveRegsForRegionIdx(unsigned RegionIdx) {
assert(IdxToInstruction.contains(RegionIdx));
MachineInstr *Key = IdxToInstruction[RegionIdx];
- return RegionLiveRegMap[Key];
+ return RegionVirtLiveRegMap[Key];
}
};
@@ -273,30 +273,31 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive {
BitVector RegionsWithIGLPInstrs;
// Region live-in cache.
- SmallVector<GCNRPTracker::LiveRegSet, 32> LiveIns;
+ SmallVector<GCNRPTracker::LiveRegSet, 32> VirtLiveIns;
// Region pressure cache.
SmallVector<GCNRegPressure, 32> Pressure;
// Temporary basic block live-in cache.
- DenseMap<const MachineBasicBlock *, GCNRPTracker::LiveRegSet> MBBLiveIns;
+ DenseMap<const MachineBasicBlock *, GCNRPTracker::LiveRegSet> MBBVirtLiveIns;
// The map of the initial first region instruction to region live in registers
- DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> BBLiveInMap;
+ DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> BBVirtLiveInMap;
// Calculate the map of the initial first region instruction to region live in
// registers
- DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> getRegionLiveInMap() const;
+ DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
+ getRegionVirtLiveInMap() const;
// Calculate the map of the initial last region instruction to region live out
// registers
DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
- getRegionLiveOutMap() const;
+ getRegionVirtLiveOutMap() const;
// The live out registers per region. These are internally stored as a map of
// the initial last region instruction to region live out registers, but can
- // be retreived with the regionIdx by calls to getLiveRegsForRegionIdx.
- RegionPressureMap RegionLiveOuts;
+ // be retreived with the regionIdx by calls to getVirtLiveRegsForRegionIdx.
+ RegionPressureMap RegionVirtLiveOuts;
// Return current region pressure.
GCNRegPressure getRealRegPressure(unsigned RegionIdx) const;
diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
index 982034189892c..a44b28de507fc 100644
--- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
@@ -296,7 +296,7 @@ bool SIFormMemoryClausesImpl::run(MachineFunction &MF) {
RPT.advanceBeforeNext();
}
- const GCNRPTracker::LiveRegSet LiveRegsCopy(RPT.getLiveRegs());
+ const GCNRPTracker::LiveRegSet LiveRegsCopy(RPT.getVirtLiveRegs());
RegUse Defs, Uses;
if (!processRegUses(MI, Defs, Uses, RPT)) {
RPT.reset(MI, &LiveRegsCopy);
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