[llvm] [SPIRV] Sign-extend operands of sign-sensitive ops on sub-pow2 widths (PR #203661)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 594e58761..f485a6b99 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -577,8 +577,8 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
       case TargetOpcode::G_SREM:
         return true;
       case TargetOpcode::G_ICMP:
-        return CmpInst::isSigned(static_cast<CmpInst::Predicate>(
-            MI.getOperand(1).getPredicate()));
+        return CmpInst::isSigned(
+            static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
       default:
         return false;
       }
@@ -605,8 +605,8 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
       if (!MOP.isReg())
         return;
       Register Reg = MOP.getReg();
-      auto [OWIt, OWInserted] = OrigWidth.try_emplace(
-          Reg, MRI.getType(Reg).getScalarSizeInBits());
+      auto [OWIt, OWInserted] =
+          OrigWidth.try_emplace(Reg, MRI.getType(Reg).getScalarSizeInBits());
       unsigned OldW = OWIt->second;
       unsigned NewW = widenBitWidthToNextPow2(OldW);
       if (NewW == OldW)

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https://github.com/llvm/llvm-project/pull/203661