[llvm] e3e2fd6 - [RISCV] Add PseudoClearGPR to the special cases in RISCVInstrInfo::getInstSizeInBytes. (#203637)

[via llvm-commits]

Author: Craig Topper
Date: 2026-06-12T18:08:45-07:00
New Revision: e3e2fd630f5969a6ee845a57e3be380331405e2e

URL: https://github.com/llvm/llvm-project/commit/e3e2fd630f5969a6ee845a57e3be380331405e2e
DIFF: https://github.com/llvm/llvm-project/commit/e3e2fd630f5969a6ee845a57e3be380331405e2e.diff

LOG: [RISCV] Add PseudoClearGPR to the special cases in RISCVInstrInfo::getInstSizeInBytes. (#203637)

This instruction is expanded to an ADDI with immediate of 0 and should
then be compressed to c.li with Zca. The compression code doesn't know
this due to the Pseudo so manually give a size of 2 for Zca.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9076cbbc82ed9..b31a3a7760d3b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2007,6 +2007,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   switch (Opcode) {
   case RISCV::PseudoMV_FPR16INX:
   case RISCV::PseudoMV_FPR32INX:
+  case RISCV::PseudoClearGPR:
     // MV is always compressible to either c.mv or c.li rd, 0.
     return STI.hasStdExtZca() ? 2 : 4;
   // Below cases are for short forward branch pseudos

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 2f58b43dfacbf..f25654de03183 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2162,8 +2162,7 @@ def SetFCSRImm : SetSysRegImm<SysRegFCSR, [FRM, FFLAGS]>;
 /// Other pseudo-instructions
 
 // Used by -fzero-call-used-regs to zero out registers.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
-    isCodeGenOnly = true in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def PseudoClearGPR : Pseudo<(outs GPR:$rd), (ins), []>,
                      PseudoInstExpansion<(ADDI GPR:$rd, X0, 0)>;