[llvm] [AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64 (PR #203607)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 11:52:16 PDT 2026
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/203607
>From 312c1b731a1a8742b6384782934d5f563fdbf28d Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Fri, 12 Jun 2026 11:46:21 -0700
Subject: [PATCH] [AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 5 +
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 11 +-
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 8 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 15 +-
.../Disassembler/AMDGPUDisassembler.cpp | 2 +
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 1 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 1 +
llvm/lib/Target/AMDGPU/SIDefines.h | 1 +
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 1 +
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 1 +
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 4 +
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 1 +
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 17 +-
llvm/test/CodeGen/AMDGPU/packed-u64.ll | 1313 +++++++++++++++++
llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s | 96 ++
llvm/test/MC/AMDGPU/gfx1251_err.s | 58 +
.../AMDGPU/gfx1251_dasm_vop3p.txt | 72 +
19 files changed, 1622 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/packed-u64.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index b91091e97ca9d..5884b9edf57c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -701,6 +701,10 @@ defm PackedFP64Ops : AMDGPUSubtargetFeature<"packed-fp64-ops",
"Support packed fp64 instructions"
>;
+defm PackedU64Ops : AMDGPUSubtargetFeature<"packed-u64-ops",
+ "Support packed uint64 instructions"
+>;
+
defm R128A16 : AMDGPUSubtargetFeature<"r128-a16",
"Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image "
"operands, where a16 is aliased with r128"
@@ -2228,6 +2232,7 @@ def FeatureISAVersion12_51 : FeatureSet<
FeatureVOP3PX2IncrementsVaVdstTwice,
FeatureDPALU_DPP,
FeaturePackedFP64Ops,
+ FeaturePackedU64Ops,
FeatureGFX1251GEMMInsts,
FeatureGFX125xLowestRateWMMA,
FeatureCubeInsts,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 0ad3fbe9400ad..3c8f81ea5b11e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -760,7 +760,16 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.hasVOP3PInsts() && ST.hasAddNoCarryInsts() && ST.hasIntClamp()) {
// Full set of gfx9 features.
- if (ST.hasScalarAddSub64()) {
+ if (ST.hasPackedU64Ops()) {
+ getActionDefinitionsBuilder({G_ADD, G_SUB})
+ .legalFor({S64, S32, S16, V2S16, V2S64})
+ .clampMaxNumElementsStrict(0, S16, 2)
+ .clampMaxNumElementsStrict(0, S64, 2)
+ .scalarize(0)
+ .minScalar(0, S16)
+ .widenScalarToNextMultipleOf(0, 32)
+ .maxScalar(0, S32);
+ } else if (ST.hasScalarAddSub64()) {
getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({S64, S32, S16, V2S16})
.clampMaxNumElementsStrict(0, S16, 2)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index db8fc149df1f6..200234c23c886 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4063,8 +4063,14 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_UBFX:
case AMDGPU::G_AMDGPU_S_MUL_I64_I32:
case AMDGPU::G_AMDGPU_S_MUL_U64_U32:
- if (isSALUMapping(MI))
+ if (isSALUMapping(MI)) {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ unsigned Size = Ty.getSizeInBits();
+ // Packed add and sub are VALU only.
+ if (Subtarget.hasPackedU64Ops() && Ty.isVector() && Size == 128)
+ return getDefaultMappingVOP(MI);
return getDefaultMappingSOP(MI);
+ }
return getDefaultMappingVOP(MI);
case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 21214e9e25162..7fe14d8433257 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -617,6 +617,11 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isVSrc_b64() const { return isVCSrc_f64() || isLiteralImm(MVT::i64); }
+ bool isVSrc_v2b64() const {
+ return isRegOrInlineNoMods(AMDGPU::VS_128RegClassID, MVT::i64) ||
+ isLiteralImm(MVT::i64);
+ }
+
bool isVSrc_v2f64() const {
return isRegOrInlineNoMods(AMDGPU::VS_128RegClassID, MVT::f64) ||
isLiteralImm(MVT::f64);
@@ -2086,6 +2091,7 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
case AMDGPU::OPERAND_KIMM64:
return &APFloat::IEEEdouble();
case AMDGPU::OPERAND_REG_IMM_FP16:
@@ -2407,6 +2413,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
if (Lit == LitModifier::None &&
AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
AsmParser->hasInv2PiInlineImm())) {
@@ -2540,6 +2547,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
if (Lit == LitModifier::None &&
AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
@@ -5187,8 +5195,11 @@ bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
Desc.operands()[OpIdx].OperandType == AMDGPU::OPERAND_KIMM64 ||
(Desc.operands()[OpIdx].OperandType == AMDGPU::OPERAND_REG_IMM_FP64 &&
HasMandatoryLiteral);
- bool IsFP64 = (IsForcedFP64 || AMDGPU::isSISrcFPOperand(Desc, OpIdx)) &&
- AMDGPU::getOperandSize(Desc.operands()[OpIdx]) == 8;
+ unsigned OpTy = Desc.operands()[OpIdx].OperandType;
+ bool IsFP64 =
+ (IsForcedFP64 || (AMDGPU::isSISrcFPOperand(Desc, OpIdx) &&
+ OpTy != AMDGPU::OPERAND_REG_IMM_V2INT64)) &&
+ AMDGPU::getOperandSize(Desc.operands()[OpIdx]) == 8;
bool IsValid32Op =
IsForcedLit || AMDGPU::isValid32BitLiteral(Value, IsFP64);
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 44eee6d7c8af4..d57c06e689008 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -552,6 +552,7 @@ void AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
Imm = getInlineImmVal64(Imm);
break;
default:
@@ -1687,6 +1688,7 @@ AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
break;
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
UseLit = AMDGPU::isInlinableLiteral64(Val, HasInv2Pi);
break;
case MCOI::OPERAND_REGISTER:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 866fb3f3e3788..f6d30f64e224e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -873,6 +873,7 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
break;
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
printImmediate64(Op.getImm(), STI, O, false);
break;
case AMDGPU::OPERAND_REG_IMM_FP64:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 69ec3baba9380..b3fdf38b9a688 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -314,6 +314,7 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, false);
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 2e9ca0783362a..6a5d82af41fb3 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -213,6 +213,7 @@ enum OperandType : unsigned {
OPERAND_REG_IMM_V2FP16,
OPERAND_REG_IMM_V2FP16_SPLAT,
OPERAND_REG_IMM_V2INT16,
+ OPERAND_REG_IMM_V2INT64,
OPERAND_REG_IMM_NOINLINE_V2FP16,
OPERAND_REG_IMM_V2INT32,
OPERAND_REG_IMM_V2FP32,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index cf2c55cc360f8..f4f2f9e3632d8 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -918,6 +918,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
ISD::FMAXIMUMNUM, ISD::FCANONICALIZE},
{MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64}, Custom);
}
+
+ if (Subtarget->hasPackedU64Ops()) {
+ setOperationAction({ISD::ADD, ISD::SUB}, MVT::v2i64, Legal);
+ setOperationAction({ISD::ADD, ISD::SUB},
+ {MVT::v4i64, MVT::v8i64, MVT::v16i64, MVT::v32i64},
+ Custom);
+ }
}
setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v4f16, Custom);
@@ -7492,7 +7499,14 @@ SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode();
EVT VT = Op.getValueType();
- assert(VT.isVector() && VT.getVectorElementCount().isKnownEven());
+ assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16 ||
+ VT == MVT::v4f32 || VT == MVT::v8i16 || VT == MVT::v8f16 ||
+ VT == MVT::v8bf16 || VT == MVT::v16i16 || VT == MVT::v16f16 ||
+ VT == MVT::v16bf16 || VT == MVT::v8f32 || VT == MVT::v16f32 ||
+ VT == MVT::v32f32 || VT == MVT::v32i16 || VT == MVT::v32f16 ||
+ VT == MVT::v32bf16 || VT == MVT::v4f64 || VT == MVT::v8f64 ||
+ VT == MVT::v16f64 || VT == MVT::v32f64 || VT == MVT::v4i64 ||
+ VT == MVT::v8i64 || VT == MVT::v16i64 || VT == MVT::v32i64);
auto [Lo0, Hi0] = DAG.SplitVectorOperand(Op.getNode(), 0);
auto [Lo1, Hi1] = DAG.SplitVectorOperand(Op.getNode(), 1);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a5198cce50e0f..ba1f1b2effe9f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4823,6 +4823,7 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
return AMDGPU::isInlinableLiteral64(Imm, ST.hasInv2PiInlineImm());
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
@@ -5313,6 +5314,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
case AMDGPU::OPERAND_REG_IMM_V2INT16:
case AMDGPU::OPERAND_REG_IMM_V2BF16:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
break;
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
@@ -6651,7 +6653,8 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
bool Is64BitOp = Is64BitFPOp ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2INT32 ||
- OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP32;
+ OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP32 ||
+ OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2INT64;
if (Is64BitOp &&
!AMDGPU::isInlinableLiteral64(Imm, ST.hasInv2PiInlineImm())) {
if (!AMDGPU::isValid32BitLiteral(Imm, Is64BitFPOp) &&
@@ -10026,6 +10029,7 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
LiteralSize = 8;
break;
case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
// A 32-bit literal is only valid when the value fits in BOTH signed
// and unsigned 32-bit ranges [0, 2^31-1], matching the MC code
// emitter's getLit64Encoding logic. This is because of the lack of
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index dd159354c421a..b3fffba0bd1a3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3185,6 +3185,7 @@ def VOP_V16F32_V4I16_V4I16_V16F32 : VOPProfile <[v16f32, v4i16, v4i16, v16f32]>;
def VOP_V32F32_V4I16_V4I16_V32F32 : VOPProfile <[v32f32, v4i16, v4i16, v32f32]>;
def VOP_V2F64_V2F64_V2F64 : VOPProfile <[v2f64, v2f64, v2f64, untyped]>;
def VOP_V2F64_V2F64_V2F64_V2F64 : VOPProfile <[v2f64, v2f64, v2f64, v2f64]>;
+def VOP_V2I64_V2I64_V2I64 : VOPProfile <[v2i64, v2i64, v2i64, untyped]>;
def VOP_V4I32_I64_I64_V4I32 : VOPProfile <[v4i32, i64, i64, v4i32]>;
def VOP_V16I32_I64_I64_V16I32 : VOPProfile <[v16i32, i64, i64, v16i32]>;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 75ac25c1c22d7..31f927709e682 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1445,6 +1445,7 @@ def VSrc_f64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_FP64"> {
}
def VSrc_v2b32 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_V2INT32">;
def VSrc_v2f32 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_V2FP32">;
+def VSrc_v2b64 : SrcRegOrImm9 <VS_128, "OPERAND_REG_IMM_V2INT64">;
def VSrc_v2f64 : SrcRegOrImm9 <VS_128, "OPERAND_REG_IMM_V2FP64">;
def VSrc_NoInline_v2f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_NOINLINE_V2FP16">;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 7c515172791e3..c1e9bc6336eb6 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -3853,6 +3853,10 @@ bool isPacked64BitInst(unsigned Opc) {
case AMDGPU::V_PK_MAX_NUM_F64_gfx1250:
case AMDGPU::V_PK_MIN_NUM_F64:
case AMDGPU::V_PK_MIN_NUM_F64_gfx1250:
+ case AMDGPU::V_PK_ADD_NC_U64:
+ case AMDGPU::V_PK_ADD_NC_U64_gfx1250:
+ case AMDGPU::V_PK_SUB_NC_U64:
+ case AMDGPU::V_PK_SUB_NC_U64_gfx1250:
return true;
default:
return false;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 4b754fa6e36b6..6f45f6482ca9a 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1687,6 +1687,7 @@ inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
+ case AMDGPU::OPERAND_REG_IMM_V2INT64:
case AMDGPU::OPERAND_KIMM64:
return 8;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 7acd2a08a3886..d6eb02d9c9c36 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -142,6 +142,12 @@ def V_PK_VOP3_F64_Profile : VOP3P_Profile<VOP_V2F64_V2F64_V2F64_V2F64, VOP3_PACK
let Src2RC64 = VSrc_v2f64;
}
+def V_PK_VOP2_I64_Profile : VOP3P_Profile<VOP_V2I64_V2I64_V2I64, VOP3_PACKED> {
+ let HasOpSel = 0;
+ let Src0RC64 = VSrc_v2b64;
+ let Src1RC64 = VSrc_v2b64;
+}
+
let isReMaterializable = 1 in {
let isCommutable = 1 in {
defm V_PK_MAD_I16 : VOP3PInst<"v_pk_mad_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>;
@@ -169,11 +175,14 @@ defm V_PK_MAX_NUM_F64 : VOP3PInst<"v_pk_max_num_f64", V_PK_VOP2_F64_Profile, fma
defm V_PK_MIN_NUM_F64 : VOP3PInst<"v_pk_min_num_f64", V_PK_VOP2_F64_Profile, fminnum_like>;
}
+let SubtargetPredicate = HasPackedU64Ops, SchedRW = [Write64Bit] in
+defm V_PK_ADD_NC_U64 : VOP3PInst<"v_pk_add_nc_u64", V_PK_VOP2_I64_Profile, add>;
+
let SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0 in {
defm V_PK_MAXIMUM_F16 : VOP3PInst<"v_pk_maximum_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16, VOP3_PACKED>, fmaximum>;
defm V_PK_MINIMUM_F16 : VOP3PInst<"v_pk_minimum_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16, VOP3_PACKED>, fminimum>;
} // End SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0
-}
+} // End isCommutable = 1
defm V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>>;
defm V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, sub>;
@@ -181,6 +190,10 @@ defm V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I1
defm V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshl_rev_16>;
defm V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, cashr_rev_16>;
defm V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshr_rev_16>;
+
+let SubtargetPredicate = HasPackedU64Ops, SchedRW = [Write64Bit] in {
+defm V_PK_SUB_NC_U64 : VOP3PInst<"v_pk_sub_nc_u64", V_PK_VOP2_I64_Profile, sub>;
+} // End SubtargetPredicate = HasPackedU64Ops, , SchedRW = [Write64Bit]
} // End isReMaterializable = 1
let SubtargetPredicate = HasVOP3PInsts in {
@@ -2710,6 +2723,8 @@ let PostEncoderMethod = "postEncodeVOP3<true, true, false>" in {
defm V_PK_FMA_F64 : VOP3P_Real_gfx1250<0x3b>;
defm V_PK_MUL_F64 : VOP3P_Real_gfx1250<0x3c>;
defm V_PK_ADD_F64 : VOP3P_Real_gfx1250<0x4b>;
+defm V_PK_ADD_NC_U64 : VOP3P_Real_gfx1250<0x4c>;
+defm V_PK_SUB_NC_U64 : VOP3P_Real_gfx1250<0x4d>;
defm V_PK_MAX_NUM_F64 : VOP3P_Real_gfx1250<0x4e>;
defm V_PK_MIN_NUM_F64 : VOP3P_Real_gfx1250<0x4f>;
diff --git a/llvm/test/CodeGen/AMDGPU/packed-u64.ll b/llvm/test/CodeGen/AMDGPU/packed-u64.ll
new file mode 100644
index 0000000000000..f9efda624d52a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/packed-u64.ll
@@ -0,0 +1,1313 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-GISEL %s
+
+define amdgpu_kernel void @add_v2_vv(ptr addrspace(1) %a) {
+; GFX1251-LABEL: add_v2_vv:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-NEXT: v_and_b32_e32 v4, 0x3ff, v0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: global_load_b128 v[0:3], v4, s[0:1] scale_offset
+; GFX1251-NEXT: s_wait_loadcnt 0x0
+; GFX1251-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[0:3]
+; GFX1251-NEXT: global_store_b128 v4, v[0:3], s[0:1] scale_offset
+; GFX1251-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, %load
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_vs(ptr addrspace(1) %a, <2 x i64> %x) {
+; GFX1251-LABEL: add_v2_vs:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-NEXT: s_clause 0x1
+; GFX1251-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX1251-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-NEXT: s_wait_loadcnt 0x0
+; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, %x
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_ss(ptr addrspace(1) %a, <2 x i64> %x, <2 x i64> %y) {
+; GFX1251-SDAG-LABEL: add_v2_ss:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s8
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v3, s11 :: v_dual_mov_b32 v4, s12
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, s13 :: v_dual_mov_b32 v6, s14
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v7, s15
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1]
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_ss:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: s_endpgm
+ %add = add <2 x i64> %x, %y
+ store <2 x i64> %add, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v4_vs(ptr addrspace(1) %a, <4 x i64> %x) {
+; GFX1251-SDAG-LABEL: add_v4_vs:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x44 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_lshlrev_b32 v16, 5, v0 :: v_dual_mov_b32 v8, s12
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v16, s[0:1]
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v16, s[0:1] offset:16
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v11, s15
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[12:15]
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[4:7], v[4:7], v[8:11]
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: global_store_b128 v16, v[0:3], s[0:1]
+; GFX1251-SDAG-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v4_vs:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x44 nv
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_lshlrev_b32_e32 v16, 5, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v16, s[0:1]
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v16, s[0:1] offset:16
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[8:11]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[4:7], v[4:7], v[12:15]
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: global_store_b128 v16, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <4 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <4 x i64>, ptr addrspace(1) %gep, align 16
+ %add = add <4 x i64> %load, %x
+ store <4 x i64> %add, ptr addrspace(1) %gep, align 16
+ ret void
+}
+
+define amdgpu_kernel void @add_v32_vs(ptr addrspace(1) %a, <32 x i64> %x) {
+; GFX1251-SDAG-LABEL: add_v32_vs:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x4
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[68:83], s[4:5], 0x1a4 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[52:67], s[4:5], 0x1e4 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x124 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0x164 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_lshlrev_b32 v44, 8, v0 :: v_dual_mov_b32 v66, s72
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v67, s73 :: v_dual_mov_b32 v68, s74
+; GFX1251-SDAG-NEXT: s_clause 0xf
+; GFX1251-SDAG-NEXT: global_load_b128 v[40:43], v44, s[0:1] offset:144
+; GFX1251-SDAG-NEXT: global_load_b128 v[36:39], v44, s[0:1] offset:128
+; GFX1251-SDAG-NEXT: global_load_b128 v[32:35], v44, s[0:1] offset:176
+; GFX1251-SDAG-NEXT: global_load_b128 v[28:31], v44, s[0:1] offset:160
+; GFX1251-SDAG-NEXT: global_load_b128 v[24:27], v44, s[0:1] offset:208
+; GFX1251-SDAG-NEXT: global_load_b128 v[20:23], v44, s[0:1] offset:192
+; GFX1251-SDAG-NEXT: global_load_b128 v[16:19], v44, s[0:1] offset:240
+; GFX1251-SDAG-NEXT: global_load_b128 v[12:15], v44, s[0:1] offset:224
+; GFX1251-SDAG-NEXT: global_load_b128 v[8:11], v44, s[0:1] offset:16
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v44, s[0:1]
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v44, s[0:1] offset:48
+; GFX1251-SDAG-NEXT: global_load_b128 v[46:49], v44, s[0:1] offset:64
+; GFX1251-SDAG-NEXT: global_load_b128 v[50:53], v44, s[0:1] offset:112
+; GFX1251-SDAG-NEXT: global_load_b128 v[54:57], v44, s[0:1] offset:96
+; GFX1251-SDAG-NEXT: global_load_b128 v[58:61], v44, s[0:1] offset:80
+; GFX1251-SDAG-NEXT: global_load_b128 v[62:65], v44, s[0:1] offset:32
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v69, s75 :: v_dual_mov_b32 v70, s68
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v71, s69 :: v_dual_mov_b32 v72, s70
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v73, s71
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xf
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[40:43], v[40:43], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s80 :: v_dual_mov_b32 v67, s81
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s82 :: v_dual_mov_b32 v69, s83
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xe
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[36:39], v[36:39], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s76 :: v_dual_mov_b32 v71, s77
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s78 :: v_dual_mov_b32 v73, s79
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xd
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[32:35], v[32:35], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s56 :: v_dual_mov_b32 v67, s57
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s58 :: v_dual_mov_b32 v69, s59
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xc
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[28:31], v[28:31], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s52 :: v_dual_mov_b32 v71, s53
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s54 :: v_dual_mov_b32 v73, s55
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xb
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[24:27], v[24:27], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s64 :: v_dual_mov_b32 v67, s65
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s66 :: v_dual_mov_b32 v69, s67
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xa
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[20:23], v[20:23], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s60 :: v_dual_mov_b32 v71, s61
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s62 :: v_dual_mov_b32 v73, s63
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x9
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[16:19], v[16:19], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s12 :: v_dual_mov_b32 v67, s13
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s14 :: v_dual_mov_b32 v69, s15
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x8
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[12:15], v[12:15], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s8 :: v_dual_mov_b32 v71, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s10 :: v_dual_mov_b32 v73, s11
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x7
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[8:11], v[8:11], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s20 :: v_dual_mov_b32 v67, s21
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s22 :: v_dual_mov_b32 v69, s23
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x6
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[4:7], v[4:7], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s36 :: v_dual_mov_b32 v71, s37
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s38 :: v_dual_mov_b32 v73, s39
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x5
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s48 :: v_dual_mov_b32 v67, s49
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s50 :: v_dual_mov_b32 v69, s51
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x4
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[46:49], v[46:49], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s44 :: v_dual_mov_b32 v71, s45
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s46 :: v_dual_mov_b32 v73, s47
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x3
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[50:53], v[50:53], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s40 :: v_dual_mov_b32 v67, s41
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s42 :: v_dual_mov_b32 v69, s43
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x2
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[54:57], v[54:57], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s16 :: v_dual_mov_b32 v71, s17
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s18 :: v_dual_mov_b32 v73, s19
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x1
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[58:61], v[58:61], v[66:69]
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[62:65], v[62:65], v[70:73]
+; GFX1251-SDAG-NEXT: s_clause 0xf
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[54:57], s[0:1] offset:96
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[50:53], s[0:1] offset:112
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[46:49], s[0:1] offset:64
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[58:61], s[0:1] offset:80
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[62:65], s[0:1] offset:32
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[0:3], s[0:1] offset:48
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[4:7], s[0:1]
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[8:11], s[0:1] offset:16
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[12:15], s[0:1] offset:224
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[16:19], s[0:1] offset:240
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[20:23], s[0:1] offset:192
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[24:27], s[0:1] offset:208
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[28:31], s[0:1] offset:160
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[32:35], s[0:1] offset:176
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[36:39], s[0:1] offset:128
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[40:43], s[0:1] offset:144
+; GFX1251-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v32_vs:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: s_load_b512 s[16:31], s[4:5], 0x124 nv
+; GFX1251-GISEL-NEXT: s_load_b512 s[44:59], s[4:5], 0x164 nv
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_lshlrev_b32_e32 v72, 8, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: s_clause 0xf
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v72, s[0:1]
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v72, s[0:1] offset:16
+; GFX1251-GISEL-NEXT: global_load_b128 v[8:11], v72, s[0:1] offset:32
+; GFX1251-GISEL-NEXT: global_load_b128 v[12:15], v72, s[0:1] offset:48
+; GFX1251-GISEL-NEXT: global_load_b128 v[16:19], v72, s[0:1] offset:64
+; GFX1251-GISEL-NEXT: global_load_b128 v[20:23], v72, s[0:1] offset:80
+; GFX1251-GISEL-NEXT: global_load_b128 v[24:27], v72, s[0:1] offset:96
+; GFX1251-GISEL-NEXT: global_load_b128 v[28:31], v72, s[0:1] offset:112
+; GFX1251-GISEL-NEXT: global_load_b128 v[32:35], v72, s[0:1] offset:128
+; GFX1251-GISEL-NEXT: global_load_b128 v[36:39], v72, s[0:1] offset:144
+; GFX1251-GISEL-NEXT: global_load_b128 v[40:43], v72, s[0:1] offset:160
+; GFX1251-GISEL-NEXT: global_load_b128 v[44:47], v72, s[0:1] offset:176
+; GFX1251-GISEL-NEXT: global_load_b128 v[48:51], v72, s[0:1] offset:192
+; GFX1251-GISEL-NEXT: global_load_b128 v[52:55], v72, s[0:1] offset:208
+; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
+; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
+; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[4:7], v[4:7], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[8:11], v[8:11], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[12:15], v[12:15], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
+; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[16:19], v[16:19], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[20:23], v[20:23], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[24:27], v[24:27], v[64:67]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[28:31], v[28:31], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[32:35], v[32:35], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[36:39], v[36:39], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[40:43], v[40:43], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[44:47], v[44:47], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[48:51], v[48:51], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[52:55], v[52:55], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[56:59], v[56:59], v[64:67]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[60:63], v[60:63], v[68:71]
+; GFX1251-GISEL-NEXT: s_clause 0xf
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[4:7], s[0:1] offset:16
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[8:11], s[0:1] offset:32
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[12:15], s[0:1] offset:48
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[16:19], s[0:1] offset:64
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[20:23], s[0:1] offset:80
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[24:27], s[0:1] offset:96
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[28:31], s[0:1] offset:112
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[32:35], s[0:1] offset:128
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[36:39], s[0:1] offset:144
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[40:43], s[0:1] offset:160
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[44:47], s[0:1] offset:176
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[48:51], s[0:1] offset:192
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[52:55], s[0:1] offset:208
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[56:59], s[0:1] offset:224
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[60:63], s[0:1] offset:240
+; GFX1251-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <32 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <32 x i64>, ptr addrspace(1) %gep, align 128
+ %add = add <32 x i64> %load, %x
+ store <32 x i64> %add, ptr addrspace(1) %gep, align 128
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_v_imm(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: add_v2_v_imm:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0x64 :: v_dual_mov_b32 v5, 0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_v_imm:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0x64
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, <i64 100, i64 100>
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_v_v_splat(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: add_v2_v_v_splat:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v0
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v0, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[2:5], v[4:7], v[0:3]
+; GFX1251-SDAG-NEXT: global_store_b128 v0, v[2:5], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_v_v_splat:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v0, s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[2:5], v[4:7], v[0:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v0, v[2:5], s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %id.1 = zext i32 %id to i64
+ %fid = bitcast i64 %id.1 to i64
+ %tmp1 = insertelement <2 x i64> poison, i64 %fid, i64 0
+ %k = insertelement <2 x i64> %tmp1, i64 %fid, i64 1
+ %add = add <2 x i64> %load, %k
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+; TODO: splat literal can be folded, but it is a REG_SEQUENCE which we do not match
+
+define amdgpu_kernel void @add_v2_v_lit_splat(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: add_v2_v_lit_splat:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_v_lit_splat:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, <i64 1, i64 1>
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_v_lit_hi0(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: add_v2_v_lit_hi0:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_v_lit_hi0:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 1
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, <i64 1, i64 0>
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_v_lit_lo0(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: add_v2_v_lit_lo0:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v6, 1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v7, v4
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_v_lit_lo0:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 1
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, <i64 0, i64 1>
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @add_v2_v_unfoldable_lit(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: add_v2_v_unfoldable_lit:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: add_v2_v_unfoldable_lit:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 2
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 1
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %add = add <2 x i64> %load, <i64 1, i64 2>
+ store <2 x i64> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_vv(ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX1251-LABEL: sub_v2_vv:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1251-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: s_clause 0x1
+; GFX1251-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-NEXT: global_load_b128 v[4:7], v8, s[2:3] scale_offset
+; GFX1251-NEXT: s_wait_loadcnt 0x0
+; GFX1251-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep.a = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load.a = load <2 x i64>, ptr addrspace(1) %gep.a, align 8
+ %gep.b = getelementptr inbounds <2 x i64>, ptr addrspace(1) %b, i32 %id
+ %load.b = load <2 x i64>, ptr addrspace(1) %gep.b, align 8
+ %sub = sub <2 x i64> %load.a, %load.b
+ store <2 x i64> %sub, ptr addrspace(1) %gep.a, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_vs(ptr addrspace(1) %a, <2 x i64> %x) {
+; GFX1251-LABEL: sub_v2_vs:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-NEXT: s_clause 0x1
+; GFX1251-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX1251-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-NEXT: s_wait_loadcnt 0x0
+; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> %load, %x
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_ss(ptr addrspace(1) %a, <2 x i64> %x, <2 x i64> %y) {
+; GFX1251-SDAG-LABEL: sub_v2_ss:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s8
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v3, s11 :: v_dual_mov_b32 v4, s12
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, s13 :: v_dual_mov_b32 v6, s14
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v7, s15
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1]
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_ss:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: s_endpgm
+ %sub = sub <2 x i64> %x, %y
+ store <2 x i64> %sub, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v4_vs(ptr addrspace(1) %a, <4 x i64> %x) {
+; GFX1251-SDAG-LABEL: sub_v4_vs:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x44 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_lshlrev_b32 v16, 5, v0 :: v_dual_mov_b32 v8, s12
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v16, s[0:1]
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v16, s[0:1] offset:16
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v11, s15
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[12:15]
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[4:7], v[4:7], v[8:11]
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: global_store_b128 v16, v[0:3], s[0:1]
+; GFX1251-SDAG-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v4_vs:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x44 nv
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_lshlrev_b32_e32 v16, 5, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v16, s[0:1]
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v16, s[0:1] offset:16
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[8:11]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[4:7], v[4:7], v[12:15]
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: global_store_b128 v16, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <4 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <4 x i64>, ptr addrspace(1) %gep, align 16
+ %sub = sub <4 x i64> %load, %x
+ store <4 x i64> %sub, ptr addrspace(1) %gep, align 16
+ ret void
+}
+
+define amdgpu_kernel void @sub_v32_vs(ptr addrspace(1) %a, <32 x i64> %x) {
+; GFX1251-SDAG-LABEL: sub_v32_vs:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x4
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[68:83], s[4:5], 0x1a4 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[52:67], s[4:5], 0x1e4 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x124 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0x164 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_lshlrev_b32 v44, 8, v0 :: v_dual_mov_b32 v66, s72
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v67, s73 :: v_dual_mov_b32 v68, s74
+; GFX1251-SDAG-NEXT: s_clause 0xf
+; GFX1251-SDAG-NEXT: global_load_b128 v[40:43], v44, s[0:1] offset:144
+; GFX1251-SDAG-NEXT: global_load_b128 v[36:39], v44, s[0:1] offset:128
+; GFX1251-SDAG-NEXT: global_load_b128 v[32:35], v44, s[0:1] offset:176
+; GFX1251-SDAG-NEXT: global_load_b128 v[28:31], v44, s[0:1] offset:160
+; GFX1251-SDAG-NEXT: global_load_b128 v[24:27], v44, s[0:1] offset:208
+; GFX1251-SDAG-NEXT: global_load_b128 v[20:23], v44, s[0:1] offset:192
+; GFX1251-SDAG-NEXT: global_load_b128 v[16:19], v44, s[0:1] offset:240
+; GFX1251-SDAG-NEXT: global_load_b128 v[12:15], v44, s[0:1] offset:224
+; GFX1251-SDAG-NEXT: global_load_b128 v[8:11], v44, s[0:1] offset:16
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v44, s[0:1]
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v44, s[0:1] offset:48
+; GFX1251-SDAG-NEXT: global_load_b128 v[46:49], v44, s[0:1] offset:64
+; GFX1251-SDAG-NEXT: global_load_b128 v[50:53], v44, s[0:1] offset:112
+; GFX1251-SDAG-NEXT: global_load_b128 v[54:57], v44, s[0:1] offset:96
+; GFX1251-SDAG-NEXT: global_load_b128 v[58:61], v44, s[0:1] offset:80
+; GFX1251-SDAG-NEXT: global_load_b128 v[62:65], v44, s[0:1] offset:32
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v69, s75 :: v_dual_mov_b32 v70, s68
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v71, s69 :: v_dual_mov_b32 v72, s70
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v73, s71
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xf
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[40:43], v[40:43], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s80 :: v_dual_mov_b32 v67, s81
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s82 :: v_dual_mov_b32 v69, s83
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xe
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[36:39], v[36:39], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s76 :: v_dual_mov_b32 v71, s77
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s78 :: v_dual_mov_b32 v73, s79
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xd
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[32:35], v[32:35], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s56 :: v_dual_mov_b32 v67, s57
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s58 :: v_dual_mov_b32 v69, s59
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xc
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[28:31], v[28:31], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s52 :: v_dual_mov_b32 v71, s53
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s54 :: v_dual_mov_b32 v73, s55
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xb
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[24:27], v[24:27], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s64 :: v_dual_mov_b32 v67, s65
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s66 :: v_dual_mov_b32 v69, s67
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xa
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[20:23], v[20:23], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s60 :: v_dual_mov_b32 v71, s61
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s62 :: v_dual_mov_b32 v73, s63
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x9
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[16:19], v[16:19], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s12 :: v_dual_mov_b32 v67, s13
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s14 :: v_dual_mov_b32 v69, s15
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x8
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[12:15], v[12:15], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s8 :: v_dual_mov_b32 v71, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s10 :: v_dual_mov_b32 v73, s11
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x7
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[8:11], v[8:11], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s20 :: v_dual_mov_b32 v67, s21
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s22 :: v_dual_mov_b32 v69, s23
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x6
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[4:7], v[4:7], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s36 :: v_dual_mov_b32 v71, s37
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s38 :: v_dual_mov_b32 v73, s39
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x5
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s48 :: v_dual_mov_b32 v67, s49
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s50 :: v_dual_mov_b32 v69, s51
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x4
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[46:49], v[46:49], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s44 :: v_dual_mov_b32 v71, s45
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s46 :: v_dual_mov_b32 v73, s47
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x3
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[50:53], v[50:53], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s40 :: v_dual_mov_b32 v67, s41
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s42 :: v_dual_mov_b32 v69, s43
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x2
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[54:57], v[54:57], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s16 :: v_dual_mov_b32 v71, s17
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s18 :: v_dual_mov_b32 v73, s19
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x1
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[58:61], v[58:61], v[66:69]
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[62:65], v[62:65], v[70:73]
+; GFX1251-SDAG-NEXT: s_clause 0xf
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[54:57], s[0:1] offset:96
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[50:53], s[0:1] offset:112
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[46:49], s[0:1] offset:64
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[58:61], s[0:1] offset:80
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[62:65], s[0:1] offset:32
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[0:3], s[0:1] offset:48
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[4:7], s[0:1]
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[8:11], s[0:1] offset:16
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[12:15], s[0:1] offset:224
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[16:19], s[0:1] offset:240
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[20:23], s[0:1] offset:192
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[24:27], s[0:1] offset:208
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[28:31], s[0:1] offset:160
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[32:35], s[0:1] offset:176
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[36:39], s[0:1] offset:128
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[40:43], s[0:1] offset:144
+; GFX1251-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v32_vs:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: s_load_b512 s[16:31], s[4:5], 0x124 nv
+; GFX1251-GISEL-NEXT: s_load_b512 s[44:59], s[4:5], 0x164 nv
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_lshlrev_b32_e32 v72, 8, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: s_clause 0xf
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v72, s[0:1]
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v72, s[0:1] offset:16
+; GFX1251-GISEL-NEXT: global_load_b128 v[8:11], v72, s[0:1] offset:32
+; GFX1251-GISEL-NEXT: global_load_b128 v[12:15], v72, s[0:1] offset:48
+; GFX1251-GISEL-NEXT: global_load_b128 v[16:19], v72, s[0:1] offset:64
+; GFX1251-GISEL-NEXT: global_load_b128 v[20:23], v72, s[0:1] offset:80
+; GFX1251-GISEL-NEXT: global_load_b128 v[24:27], v72, s[0:1] offset:96
+; GFX1251-GISEL-NEXT: global_load_b128 v[28:31], v72, s[0:1] offset:112
+; GFX1251-GISEL-NEXT: global_load_b128 v[32:35], v72, s[0:1] offset:128
+; GFX1251-GISEL-NEXT: global_load_b128 v[36:39], v72, s[0:1] offset:144
+; GFX1251-GISEL-NEXT: global_load_b128 v[40:43], v72, s[0:1] offset:160
+; GFX1251-GISEL-NEXT: global_load_b128 v[44:47], v72, s[0:1] offset:176
+; GFX1251-GISEL-NEXT: global_load_b128 v[48:51], v72, s[0:1] offset:192
+; GFX1251-GISEL-NEXT: global_load_b128 v[52:55], v72, s[0:1] offset:208
+; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
+; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
+; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[4:7], v[4:7], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[8:11], v[8:11], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[12:15], v[12:15], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
+; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[16:19], v[16:19], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[20:23], v[20:23], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[24:27], v[24:27], v[64:67]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[28:31], v[28:31], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[32:35], v[32:35], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[36:39], v[36:39], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[40:43], v[40:43], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[44:47], v[44:47], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[48:51], v[48:51], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[52:55], v[52:55], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[56:59], v[56:59], v[64:67]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[60:63], v[60:63], v[68:71]
+; GFX1251-GISEL-NEXT: s_clause 0xf
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[4:7], s[0:1] offset:16
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[8:11], s[0:1] offset:32
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[12:15], s[0:1] offset:48
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[16:19], s[0:1] offset:64
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[20:23], s[0:1] offset:80
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[24:27], s[0:1] offset:96
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[28:31], s[0:1] offset:112
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[32:35], s[0:1] offset:128
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[36:39], s[0:1] offset:144
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[40:43], s[0:1] offset:160
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[44:47], s[0:1] offset:176
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[48:51], s[0:1] offset:192
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[52:55], s[0:1] offset:208
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[56:59], s[0:1] offset:224
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[60:63], s[0:1] offset:240
+; GFX1251-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <32 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <32 x i64>, ptr addrspace(1) %gep, align 128
+ %sub = sub <32 x i64> %load, %x
+ store <32 x i64> %sub, ptr addrspace(1) %gep, align 128
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_v_imm(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_v_imm:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0x64 :: v_dual_mov_b32 v5, 0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_v_imm:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0x64
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> %load, <i64 100, i64 100>
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_imm_v(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_imm_v:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0x64 :: v_dual_mov_b32 v5, 0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[4:7], v[0:3]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_imm_v:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0x64
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[4:7], v[0:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> <i64 100, i64 100>, %load
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_v_v_splat(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_v_v_splat:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v0
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v0, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[2:5], v[4:7], v[0:3]
+; GFX1251-SDAG-NEXT: global_store_b128 v0, v[2:5], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_v_v_splat:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v0, s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[2:5], v[4:7], v[0:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v0, v[2:5], s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %id.1 = zext i32 %id to i64
+ %fid = bitcast i64 %id.1 to i64
+ %tmp1 = insertelement <2 x i64> poison, i64 %fid, i64 0
+ %k = insertelement <2 x i64> %tmp1, i64 %fid, i64 1
+ %sub = sub <2 x i64> %load, %k
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+; TODO: splat literal can be folded, but it is a REG_SEQUENCE which we do not match
+
+define amdgpu_kernel void @sub_v2_v_lit_splat(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_v_lit_splat:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_v_lit_splat:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> %load, <i64 1, i64 1>
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_v_lit_hi0(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_v_lit_hi0:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_v_lit_hi0:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 1
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> %load, <i64 1, i64 0>
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_v_lit_lo0(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_v_lit_lo0:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v6, 1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v7, v4
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_v_lit_lo0:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 1
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> %load, <i64 0, i64 1>
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @sub_v2_v_unfoldable_lit(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: sub_v2_v_unfoldable_lit:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: sub_v2_v_unfoldable_lit:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 2
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 1
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x i64>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x i64>, ptr addrspace(1) %gep, align 8
+ %sub = sub <2 x i64> %load, <i64 1, i64 2>
+ store <2 x i64> %sub, ptr addrspace(1) %gep, align 8
+ ret void
+}
diff --git a/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
index 2ad0ea88d420a..24ffbb59c985d 100644
--- a/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
+++ b/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
@@ -253,3 +253,99 @@ v_pk_min_num_f64 v[4:7], 101.0, v[8:11]
v_pk_min_num_f64 v[4:7], v[8:11], 101.0
// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
// GFX1251: v_pk_min_num_f64 v[4:7], v[8:11], 0x40594000 ; encoding: [0x04,0x40,0x4f,0xcc,0x08,0xff,0x01,0x1a,0x00,0x40,0x59,0x40]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x19,0x02,0x1a]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x04,0x41,0x4c,0xcc,0x08,0x19,0x02,0x3a]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x04,0x42,0x4c,0xcc,0x08,0x19,0x02,0x5a]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] clamp
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] clamp ; encoding: [0x04,0xc0,0x4c,0xcc,0x08,0x19,0x02,0x1a]
+
+v_pk_add_nc_u64 v[4:7], s[8:11], s[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], s[8:11], s[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x18,0x00,0x1a]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], s[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], s[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x19,0x00,0x1a]
+
+v_pk_add_nc_u64 v[4:7], s[8:11], v[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], s[8:11], v[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x18,0x02,0x1a]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], null
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], null ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0xf9,0x00,0x1a]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], 1
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], 1 ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x03,0x01,0x1a]
+
+v_pk_add_nc_u64 v[4:7], 1.0, v[8:11]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], 1.0, v[8:11] ; encoding: [0x04,0x40,0x4c,0xcc,0xf2,0x10,0x02,0x1a]
+
+v_pk_add_nc_u64 v[4:7], 101, v[8:11]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], 0x65, v[8:11] ; encoding: [0x04,0x40,0x4c,0xcc,0xff,0x10,0x02,0x1a,0x65,0x00,0x00,0x00]
+
+v_pk_add_nc_u64 v[4:7], v[8:11], 101
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], 0x65 ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0xff,0x01,0x1a,0x65,0x00,0x00,0x00]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x19,0x02,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x04,0x41,0x4d,0xcc,0x08,0x19,0x02,0x3a]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x04,0x42,0x4d,0xcc,0x08,0x19,0x02,0x5a]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] clamp
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] clamp ; encoding: [0x04,0xc0,0x4d,0xcc,0x08,0x19,0x02,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], s[8:11], s[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], s[8:11], s[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x18,0x00,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], s[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], s[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x19,0x00,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], s[8:11], v[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], s[8:11], v[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x18,0x02,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], null
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], null ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0xf9,0x00,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], 1
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], 1 ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x03,0x01,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], 1.0, v[8:11]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], 1.0, v[8:11] ; encoding: [0x04,0x40,0x4d,0xcc,0xf2,0x10,0x02,0x1a]
+
+v_pk_sub_nc_u64 v[4:7], 101, v[8:11]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], 0x65, v[8:11] ; encoding: [0x04,0x40,0x4d,0xcc,0xff,0x10,0x02,0x1a,0x65,0x00,0x00,0x00]
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], 101
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], 0x65 ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0xff,0x01,0x1a,0x65,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx1251_err.s b/llvm/test/MC/AMDGPU/gfx1251_err.s
index 5b5e1448dea9c..63b5cc5b09c2c 100644
--- a/llvm/test/MC/AMDGPU/gfx1251_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1251_err.s
@@ -194,3 +194,61 @@ v_pk_min_num_f64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
v_pk_min_num_f64 v[4:7], v[5:8], null
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
// GFX1251-ERR: v_pk_min_num_f64 v[4:7], v[5:8], null
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] row_share:2
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] row_share:2
+// GFX1251-ERR: ^
+
+v_pk_add_nc_u64 v[4:7], lit64(0x12345678a), v[8:11]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX1251-ERR: v_pk_add_nc_u64 v[4:7], lit64(0x12345678a), v[8:11]
+// GFX1251-ERR: ^
+
+v_pk_add_nc_u64 v[4:7], v[8:11], lit64(0x12345678a)
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX1251-ERR: v_pk_add_nc_u64 v[4:7], v[8:11], lit64(0x12345678a)
+// GFX1251-ERR: ^
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] op_sel:[1,0]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] op_sel:[1,0]
+// GFX1251-ERR: ^
+
+v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
+// GFX1251-ERR: ^
+
+v_pk_add_nc_u64 v[4:7], v[5:8], null
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
+// GFX1251-ERR: v_pk_add_nc_u64 v[4:7], v[5:8], null
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] row_share:2
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] row_share:2
+// GFX1251-ERR: ^
+
+v_pk_sub_nc_u64 v[4:7], lit64(0x12345678a), v[8:11]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX1251-ERR: v_pk_sub_nc_u64 v[4:7], lit64(0x12345678a), v[8:11]
+// GFX1251-ERR: ^
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], lit64(0x12345678a)
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX1251-ERR: v_pk_sub_nc_u64 v[4:7], v[8:11], lit64(0x12345678a)
+// GFX1251-ERR: ^
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] op_sel:[1,0]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] op_sel:[1,0]
+// GFX1251-ERR: ^
+
+v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
+// GFX1251-ERR: ^
+
+v_pk_sub_nc_u64 v[4:7], v[5:8], null
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
+// GFX1251-ERR: v_pk_sub_nc_u64 v[4:7], v[5:8], null
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
index 3804c0422121c..51ec116464398 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
@@ -189,3 +189,75 @@
0x04,0x40,0x4f,0xcc,0x08,0xff,0x01,0x18,0x00,0x40,0x59,0x40
# GFX1251: v_pk_min_num_f64 v[4:7], v[8:11], 0x40594000 ; encoding: [0x04,0x40,0x4f,0xcc,0x08,0xff,0x01,0x1a,0x00,0x40,0x59,0x40]
+
+0x04,0x40,0x4c,0xcc,0x08,0x19,0x02,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x19,0x02,0x1a]
+
+0x04,0x41,0x4c,0xcc,0x08,0x19,0x02,0x38
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x04,0x41,0x4c,0xcc,0x08,0x19,0x02,0x3a]
+
+0x04,0x42,0x4c,0xcc,0x08,0x19,0x02,0x58
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x04,0x42,0x4c,0xcc,0x08,0x19,0x02,0x5a]
+
+0x04,0xc0,0x4c,0xcc,0x08,0x19,0x02,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], v[12:15] clamp ; encoding: [0x04,0xc0,0x4c,0xcc,0x08,0x19,0x02,0x1a]
+
+0x04,0x40,0x4c,0xcc,0x08,0x18,0x00,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], s[8:11], s[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x18,0x00,0x1a]
+
+0x04,0x40,0x4c,0xcc,0x08,0x19,0x00,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], s[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x19,0x00,0x1a]
+
+0x04,0x40,0x4c,0xcc,0x08,0x18,0x02,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], s[8:11], v[12:15] ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x18,0x02,0x1a]
+
+0x04,0x40,0x4c,0xcc,0x08,0xf9,0x00,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], null ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0xf9,0x00,0x1a]
+
+0x04,0x40,0x4c,0xcc,0x08,0x03,0x01,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], 1 ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0x03,0x01,0x1a]
+
+0x04,0x40,0x4c,0xcc,0xf2,0x10,0x02,0x18
+# GFX1251: v_pk_add_nc_u64 v[4:7], 1.0, v[8:11] ; encoding: [0x04,0x40,0x4c,0xcc,0xf2,0x10,0x02,0x1a]
+
+0x04,0x40,0x4c,0xcc,0xff,0x10,0x02,0x18,0x65,0x00,0x00,0x00
+# GFX1251: v_pk_add_nc_u64 v[4:7], 0x65, v[8:11] ; encoding: [0x04,0x40,0x4c,0xcc,0xff,0x10,0x02,0x1a,0x65,0x00,0x00,0x00]
+
+0x04,0x40,0x4c,0xcc,0x08,0xff,0x01,0x18,0x65,0x00,0x00,0x00
+# GFX1251: v_pk_add_nc_u64 v[4:7], v[8:11], 0x65 ; encoding: [0x04,0x40,0x4c,0xcc,0x08,0xff,0x01,0x1a,0x65,0x00,0x00,0x00]
+
+0x04,0x40,0x4d,0xcc,0x08,0x19,0x02,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x19,0x02,0x1a]
+
+0x04,0x41,0x4d,0xcc,0x08,0x19,0x02,0x38
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x04,0x41,0x4d,0xcc,0x08,0x19,0x02,0x3a]
+
+0x04,0x42,0x4d,0xcc,0x08,0x19,0x02,0x58
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x04,0x42,0x4d,0xcc,0x08,0x19,0x02,0x5a]
+
+0x04,0xc0,0x4d,0xcc,0x08,0x19,0x02,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], v[12:15] clamp ; encoding: [0x04,0xc0,0x4d,0xcc,0x08,0x19,0x02,0x1a]
+
+0x04,0x40,0x4d,0xcc,0x08,0x18,0x00,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], s[8:11], s[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x18,0x00,0x1a]
+
+0x04,0x40,0x4d,0xcc,0x08,0x19,0x00,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], s[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x19,0x00,0x1a]
+
+0x04,0x40,0x4d,0xcc,0x08,0x18,0x02,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], s[8:11], v[12:15] ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x18,0x02,0x1a]
+
+0x04,0x40,0x4d,0xcc,0x08,0xf9,0x00,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], null ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0xf9,0x00,0x1a]
+
+0x04,0x40,0x4d,0xcc,0x08,0x03,0x01,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], 1 ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0x03,0x01,0x1a]
+
+0x04,0x40,0x4d,0xcc,0xf2,0x10,0x02,0x18
+# GFX1251: v_pk_sub_nc_u64 v[4:7], 1.0, v[8:11] ; encoding: [0x04,0x40,0x4d,0xcc,0xf2,0x10,0x02,0x1a]
+
+0x04,0x40,0x4d,0xcc,0xff,0x10,0x02,0x18,0x65,0x00,0x00,0x00
+# GFX1251: v_pk_sub_nc_u64 v[4:7], 0x65, v[8:11] ; encoding: [0x04,0x40,0x4d,0xcc,0xff,0x10,0x02,0x1a,0x65,0x00,0x00,0x00]
+
+0x04,0x40,0x4d,0xcc,0x08,0xff,0x01,0x18,0x65,0x00,0x00,0x00
+# GFX1251: v_pk_sub_nc_u64 v[4:7], v[8:11], 0x65 ; encoding: [0x04,0x40,0x4d,0xcc,0x08,0xff,0x01,0x1a,0x65,0x00,0x00,0x00]
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