[llvm] [AMDGPU][true16] extract 16bit for scratch_load_ubyte_st when spilling (PR #203589)

[Guo Chen via llvm-commits]

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@@ -1939,7 +1939,8 @@ void SIRegisterInfo::buildSpillLoadStore(
     }
 
     Register FinalValueReg = ValueReg;
-    if (LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_SADDR) {
+    if (LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_SADDR ||
+        LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_ST) {
       // If we are loading 16-bit value with SRAMECC endabled we need a temp
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broxigarchen wrote:

getFlatScratchSpillOpcodecan guard size > 4. It's triggered here https://github.com/broxigarchen/llvm-project/blob/98abafa00dbfb838deff370c288f2eab7a5e8125/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp#L1786

In theory it could return a sv form, but do we really triger SCRATCH_LOAD_USHORT for spill? I've never seen that in any test. Also @rampitec 

https://github.com/llvm/llvm-project/pull/203589