[llvm] [AMGDPU] Add gfx1251 V_PK_MIN/MAX_NUM_F64 (PR #203596)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 12 10:59:08 PDT 2026 

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

<details>
<summary>Changes</summary>

Also legalizes v2f64 fcanonicalize.


---

Patch is 401.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203596.diff


11 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+11-4) 
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+6) 
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+4) 
- (modified) llvm/lib/Target/AMDGPU/VOP3PInstructions.td (+7) 
- (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.ll (+2762-229) 
- (modified) llvm/test/CodeGen/AMDGPU/maximumnum.ll (+1357) 
- (modified) llvm/test/CodeGen/AMDGPU/minimumnum.ll (+1317) 
- (modified) llvm/test/CodeGen/AMDGPU/packed-fp64.ll (+552) 
- (modified) llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s (+96) 
- (modified) llvm/test/MC/AMDGPU/gfx1251_err.s (+78) 
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt (+72) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 30950f8f5d9e5..cf2c55cc360f8 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -905,11 +905,18 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
                          Custom);
     }
     if (Subtarget->hasPackedFP64Ops()) {
-      setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG},
+      setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG,
+                          ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
+                          ISD::FCANONICALIZE},
                          MVT::v2f64, Legal);
-      setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG},
-                         {MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64},
-                         Custom);
+      setOperationAction(
+          {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+          MVT::v2f64, Custom);
+      setOperationAction(
+          {ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG, ISD::FMINNUM_IEEE,
+           ISD::FMAXNUM_IEEE, ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM,
+           ISD::FMAXIMUMNUM, ISD::FCANONICALIZE},
+          {MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64}, Custom);
     }
   }
 
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 6b09faba5ddcc..a00f526919b90 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3801,6 +3801,12 @@ multiclass SelectCanonicalizeAsMax<
     // FIXME: Should have VOP3P subtarget predicate
     let OtherPredicates = f16_preds;
   }
+
+  def : GCNPat<
+    (fcanonicalize (v2f64 (VOP3PMods v2f64:$src, i32:$src_mods))),
+    (V_PK_MAX_NUM_F64 $src_mods, $src, $src_mods, $src)> {
+    let OtherPredicates = !listconcat(f64_preds, [HasPackedFP64Ops]);
+  }
 }
 
 // On pre-gfx9 targets, v_max_*/v_min_* did not respect the denormal
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index d134f5020096c..7c515172791e3 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -3849,6 +3849,10 @@ bool isPacked64BitInst(unsigned Opc) {
   case AMDGPU::V_PK_MUL_F64_gfx1250:
   case AMDGPU::V_PK_FMA_F64:
   case AMDGPU::V_PK_FMA_F64_gfx1250:
+  case AMDGPU::V_PK_MAX_NUM_F64:
+  case AMDGPU::V_PK_MAX_NUM_F64_gfx1250:
+  case AMDGPU::V_PK_MIN_NUM_F64:
+  case AMDGPU::V_PK_MIN_NUM_F64_gfx1250:
     return true;
   default:
     return false;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index d44fab6046ac7..7acd2a08a3886 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -164,6 +164,11 @@ defm V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I1
 defm V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smax>;
 defm V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umax>;
 
+let SubtargetPredicate = HasPackedFP64Ops, SchedRW = [WriteDouble] in {
+defm V_PK_MAX_NUM_F64 : VOP3PInst<"v_pk_max_num_f64", V_PK_VOP2_F64_Profile, fmaxnum_like>;
+defm V_PK_MIN_NUM_F64 : VOP3PInst<"v_pk_min_num_f64", V_PK_VOP2_F64_Profile, fminnum_like>;
+}
+
 let SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0 in {
 defm V_PK_MAXIMUM_F16 : VOP3PInst<"v_pk_maximum_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16, VOP3_PACKED>, fmaximum>;
 defm V_PK_MINIMUM_F16 : VOP3PInst<"v_pk_minimum_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16, VOP3_PACKED>, fminimum>;
@@ -2705,6 +2710,8 @@ let PostEncoderMethod = "postEncodeVOP3<true, true, false>" in {
 defm V_PK_FMA_F64      : VOP3P_Real_gfx1250<0x3b>;
 defm V_PK_MUL_F64      : VOP3P_Real_gfx1250<0x3c>;
 defm V_PK_ADD_F64      : VOP3P_Real_gfx1250<0x4b>;
+defm V_PK_MAX_NUM_F64  : VOP3P_Real_gfx1250<0x4e>;
+defm V_PK_MIN_NUM_F64  : VOP3P_Real_gfx1250<0x4f>;
 
 let AssemblerPredicate = isGFX1250Plus in
 def : AMDGPUMnemonicAlias<"v_fma_mix_f32_f16",  "v_fma_mix_f32">;
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
index 6b7ddd9a49087..fe29690466184 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
@@ -13,6 +13,10 @@
 ; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-TRUE16,GFX12-GISEL-TRUE16 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-FAKE16,GFX12-SDAG-FAKE16 %s
 ; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-FAKE16,GFX12-GISEL-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX1251,GFX12-TRUE16,GFX1251-TRUE16,GFX1251-SDAG-TRUE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX1251,GFX12-TRUE16,GFX1251-TRUE16,GFX1251-GISEL-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX1251,GFX12-FAKE16,GFX1251-FAKE16,GFX1251-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX1251,GFX12-FAKE16,GFX1251-FAKE16,GFX1251-GISEL-FAKE16 %s
 
 declare float @llvm.fabs.f32(float) #0
 declare float @llvm.canonicalize.f32(float) #0
@@ -125,6 +129,54 @@ define amdgpu_kernel void @v_test_canonicalize_var_f32(ptr addrspace(1) %out) #1
 ; GFX12-GISEL-NEXT:    v_max_num_f32_e64 v0, s2, s2
 ; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-TRUE16-LABEL: v_test_canonicalize_var_f32:
+; GFX1251-SDAG-TRUE16:       ; %bb.0:
+; GFX1251-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    v_max_num_f32_e32 v1, v1, v1
+; GFX1251-SDAG-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-TRUE16-LABEL: v_test_canonicalize_var_f32:
+; GFX1251-GISEL-TRUE16:       ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    v_max_num_f32_e64 v0, s2, s2
+; GFX1251-GISEL-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-FAKE16-LABEL: v_test_canonicalize_var_f32:
+; GFX1251-SDAG-FAKE16:       ; %bb.0:
+; GFX1251-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    v_max_num_f32_e32 v1, v1, v1
+; GFX1251-SDAG-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-FAKE16-LABEL: v_test_canonicalize_var_f32:
+; GFX1251-GISEL-FAKE16:       ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    v_max_num_f32_e64 v0, s2, s2
+; GFX1251-GISEL-FAKE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-FAKE16-NEXT:    s_endpgm
   %val = load float, ptr addrspace(1) %out
   %canonicalized = call float @llvm.canonicalize.f32(float %val)
   store float %canonicalized, ptr addrspace(1) %out
@@ -247,6 +299,46 @@ define amdgpu_kernel void @s_test_canonicalize_var_f32(ptr addrspace(1) %out, fl
 ; GFX12-GISEL-NEXT:    v_max_num_f32_e64 v0, s2, s2
 ; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-TRUE16-LABEL: s_test_canonicalize_var_f32:
+; GFX1251-SDAG-TRUE16:       ; %bb.0:
+; GFX1251-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-TRUE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
+; GFX1251-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    v_max_num_f32_e64 v1, s2, s2
+; GFX1251-SDAG-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-TRUE16-LABEL: s_test_canonicalize_var_f32:
+; GFX1251-GISEL-TRUE16:       ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
+; GFX1251-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    v_max_num_f32_e64 v0, s2, s2
+; GFX1251-GISEL-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-FAKE16-LABEL: s_test_canonicalize_var_f32:
+; GFX1251-SDAG-FAKE16:       ; %bb.0:
+; GFX1251-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
+; GFX1251-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    v_max_num_f32_e64 v1, s2, s2
+; GFX1251-SDAG-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-FAKE16-LABEL: s_test_canonicalize_var_f32:
+; GFX1251-GISEL-FAKE16:       ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
+; GFX1251-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    v_max_num_f32_e64 v0, s2, s2
+; GFX1251-GISEL-FAKE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-FAKE16-NEXT:    s_endpgm
   %canonicalized = call float @llvm.canonicalize.f32(float %val)
   store float %canonicalized, ptr addrspace(1) %out
   ret void
@@ -348,6 +440,54 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_f32(ptr addrspace(1) %ou
 ; GFX12-GISEL-NEXT:    v_max_num_f32_e64 v0, |s2|, |s2|
 ; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-TRUE16-LABEL: v_test_canonicalize_fabs_var_f32:
+; GFX1251-SDAG-TRUE16:       ; %bb.0:
+; GFX1251-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    v_max_num_f32_e64 v1, |v1|, |v1|
+; GFX1251-SDAG-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-TRUE16-LABEL: v_test_canonicalize_fabs_var_f32:
+; GFX1251-GISEL-TRUE16:       ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    v_max_num_f32_e64 v0, |s2|, |s2|
+; GFX1251-GISEL-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-FAKE16-LABEL: v_test_canonicalize_fabs_var_f32:
+; GFX1251-SDAG-FAKE16:       ; %bb.0:
+; GFX1251-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    v_max_num_f32_e64 v1, |v1|, |v1|
+; GFX1251-SDAG-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-FAKE16-LABEL: v_test_canonicalize_fabs_var_f32:
+; GFX1251-GISEL-FAKE16:       ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    v_max_num_f32_e64 v0, |s2|, |s2|
+; GFX1251-GISEL-FAKE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-FAKE16-NEXT:    s_endpgm
   %val = load float, ptr addrspace(1) %out
   %val.fabs = call float @llvm.fabs.f32(float %val)
   %canonicalized = call float @llvm.canonicalize.f32(float %val.fabs)
@@ -451,6 +591,54 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_f32(ptr addrspace(1
 ; GFX12-GISEL-NEXT:    v_max_num_f32_e64 v0, -|s2|, -|s2|
 ; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-TRUE16-LABEL: v_test_canonicalize_fneg_fabs_var_f32:
+; GFX1251-SDAG-TRUE16:       ; %bb.0:
+; GFX1251-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    v_max_num_f32_e64 v1, -|v1|, -|v1|
+; GFX1251-SDAG-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-TRUE16-LABEL: v_test_canonicalize_fneg_fabs_var_f32:
+; GFX1251-GISEL-TRUE16:       ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    v_max_num_f32_e64 v0, -|s2|, -|s2|
+; GFX1251-GISEL-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-FAKE16-LABEL: v_test_canonicalize_fneg_fabs_var_f32:
+; GFX1251-SDAG-FAKE16:       ; %bb.0:
+; GFX1251-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    v_max_num_f32_e64 v1, -|v1|, -|v1|
+; GFX1251-SDAG-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-FAKE16-LABEL: v_test_canonicalize_fneg_fabs_var_f32:
+; GFX1251-GISEL-FAKE16:       ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    v_max_num_f32_e64 v0, -|s2|, -|s2|
+; GFX1251-GISEL-FAKE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-FAKE16-NEXT:    s_endpgm
   %val = load float, ptr addrspace(1) %out
   %val.fabs = call float @llvm.fabs.f32(float %val)
   %val.fabs.fneg = fneg float %val.fabs
@@ -555,6 +743,54 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_f32(ptr addrspace(1) %ou
 ; GFX12-GISEL-NEXT:    v_max_num_f32_e64 v0, -s2, -s2
 ; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-TRUE16-LABEL: v_test_canonicalize_fneg_var_f32:
+; GFX1251-SDAG-TRUE16:       ; %bb.0:
+; GFX1251-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-TRUE16-NEXT:    v_max_num_f32_e64 v1, -v1, -v1
+; GFX1251-SDAG-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-TRUE16-LABEL: v_test_canonicalize_fneg_var_f32:
+; GFX1251-GISEL-TRUE16:       ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-TRUE16-NEXT:    v_max_num_f32_e64 v0, -s2, -s2
+; GFX1251-GISEL-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX1251-SDAG-FAKE16-LABEL: v_test_canonicalize_fneg_var_f32:
+; GFX1251-SDAG-FAKE16:       ; %bb.0:
+; GFX1251-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1251-SDAG-FAKE16-NEXT:    v_max_num_f32_e64 v1, -v1, -v1
+; GFX1251-SDAG-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1251-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX1251-GISEL-FAKE16-LABEL: v_test_canonicalize_fneg_var_f32:
+; GFX1251-GISEL-FAKE16:       ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
+; GFX1251-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_load_b32 s2, s[0:1], 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1251-GISEL-FAKE16-NEXT:    v_max_num_f32_e64 v0, -s2, -s2
+; GFX1251-GISEL-FAKE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX1251-GISEL-FAKE16-NEXT:    s_endpgm
   %val = load float, ptr addrspace(1) %out
   %val.fneg = fneg float %val
   %canonicalized = call float @llvm.canonicalize.f32(float %val.fneg)
@@ -592,13 +828,37 @@ de...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/203596

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