[llvm] [AMDGPU] Select uniform (shl, or) to a scalar S_LSHL_OR_B32 pseudo (PR #202585)

[Barbara Mitic via llvm-commits]

barbara-amd wrote:

> This new change now handles the unfortune uniform (or (shl x, y), z) case that is visible as such in the SelectionDAG (single-use shift).
> It may be worth noting that it does not cover the high-half packing idiom case, where the value is bitcast(BUILD_VECTOR<2 x i16>{0, hi}) rather than an shl node - there is no (or (shl …)) in the DAG to match, so that case can't be reached by an ISel pattern.
> The earlier (reverted) attempt was a post-RA peephole which works on the materialized instructions, so it could cover both this uniform case and the packing case in one place. I tried to move the uniform case to ISel here since it's cleanly expressible as a pattern; the packing case is left out and likely wants a different so

The motivation for this uniform-value-in-VGPR fix was a bit indirect I think.
In the pipeline I originally looked at, the missed v_lshlrev_b32 + v_or_b32 pairs are almost entirely the high-half 16-bit packing idiom, not a uniform/divergence problem - by ISel the shl is already a bitcast(BUILD_VECTOR <2 x i16>), so there's no (shl …) left for a pattern to match.
The initial attempt was a late post-RA peephole that works on the already-materialized v_lshlrev_b32 + v_or_b32, so it doesn't "see" any of the ISel-side reasons fusion was blocked and just fuses the pair.
The uniform-value-in-VGPR case isn't something I set out to fix - it surfaced while validating that peephole against the LLVM tests. On the real shader I was testing this uniform path doesn't trigger. I'll try to find some other real pipeline where this patch actually fuses and changes codegen.

https://github.com/llvm/llvm-project/pull/202585