[llvm] [ARM] Add missing optimize compare candidates to isOptimizeCompareCandidate (PR #191906)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 09:22:08 PDT 2026
https://github.com/mike-goutokuji updated https://github.com/llvm/llvm-project/pull/191906
>From 7a115a091f1e19ae5e16fa551b5bd3fde1ed5403 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 12:50:30 -0400
Subject: [PATCH 1/2] Pre-commit tests (NFC)
---
...phole-opt-optimize-compare-adc-shifted.mir | 116 ++++++++++++++++++
.../peephole-opt-optimize-compare-t2adcrs.mir | 64 ++++++++++
llvm/test/CodeGen/ARM/peephole-rsb.ll | 20 +++
3 files changed, 200 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir
create mode 100644 llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir
create mode 100644 llvm/test/CodeGen/ARM/peephole-rsb.ll
diff --git a/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir
new file mode 100644
index 0000000000000..41d7e81be9449
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir
@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=armv7-none-eabi -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=armv7-none-eabi -passes=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+
+# Hand-written MIR for ARMBaseInstrInfo::optimizeCompareInstr / isOptimizeCompareCandidate:
+# folded compare-with-zero after ADCrsi / ADCrsr (optional CPSR slot toggled on the ADC).
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "armv7-none-eabi"
+
+ define void @arm_adcrsi_cmp_fold() { ret void }
+ define void @arm_adcrsr_cmp_fold() { ret void }
+...
+---
+name: arm_adcrsi_cmp_fold
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: arm_adcrsi_cmp_fold
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ADCrsi:%[0-9]+]]:gpr = ADCrsi [[COPY]], [[COPY1]], 234, 14 /* CC::al */, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
+ ; CHECK-NEXT: CMPri [[ADCrsi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: Bcc %bb.1, 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVi]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVi1]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ bb.0:
+ liveins: $r0, $r1, $cpsr
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+ %0:gpr = COPY $r0
+ %1:gpr = COPY $r1
+ %2:gpr = ADCrsi %0, %1, 234, 14, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
+ CMPri %2, 0, 14, $noreg, implicit-def $cpsr
+ Bcc %bb.1, 0, $cpsr
+ B %bb.2
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ %3:gpr = MOVi 1, 14, $noreg, $noreg
+ $r0 = COPY %3
+ BX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %4:gpr = MOVi 0, 14, $noreg, $noreg
+ $r0 = COPY %4
+ BX_RET 14, $noreg, implicit $r0
+
+...
+---
+name: arm_adcrsr_cmp_fold
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: arm_adcrsr_cmp_fold
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2
+ ; CHECK-NEXT: [[ADCrsr:%[0-9]+]]:gprnopc = ADCrsr [[COPY]], [[COPY1]], [[COPY2]], 2, 14 /* CC::al */, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
+ ; CHECK-NEXT: CMPri [[ADCrsr]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: Bcc %bb.1, 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVi]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVi1]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ bb.0:
+ liveins: $r0, $r1, $r2, $cpsr
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+ %0:gprnopc = COPY $r0
+ %1:gprnopc = COPY $r1
+ %2:gprnopc = COPY $r2
+ %3:gprnopc = ADCrsr %0, %1, %2, 2, 14, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
+ CMPri %3, 0, 14, $noreg, implicit-def $cpsr
+ Bcc %bb.1, 0, $cpsr
+ B %bb.2
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ %4:gpr = MOVi 1, 14, $noreg, $noreg
+ $r0 = COPY %4
+ BX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %5:gpr = MOVi 0, 14, $noreg, $noreg
+ $r0 = COPY %5
+ BX_RET 14, $noreg, implicit $r0
+
+...
diff --git a/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir
new file mode 100644
index 0000000000000..844d53397e1c1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=thumbv8m.main-none-eabi -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=thumbv8m.main-none-eabi -passes=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+
+# Hand-written MIR for ARMBaseInstrInfo::optimizeCompareInstr / isOptimizeCompareCandidate:
+# folded compare-with-zero after t2ADCrs (Thumb2 shifted-register ADC).
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv8m.main-none-eabi"
+
+ define void @thumb2_t2adcrs_cmp_fold() { ret void }
+...
+---
+name: thumb2_t2adcrs_cmp_fold
+alignment: 2
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: thumb2_t2adcrs_cmp_fold
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2ADCrs:%[0-9]+]]:rgpr = t2ADCrs [[COPY]], [[COPY1]], 19, 14 /* CC::al */, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
+ ; CHECK-NEXT: t2CMPri [[t2ADCrs]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2Bcc %bb.1, 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2MOVi]]
+ ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[t2MOVi1:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2MOVi1]]
+ ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ bb.0:
+ liveins: $r0, $r1, $cpsr
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+ %0:rgpr = COPY $r0
+ %1:rgpr = COPY $r1
+ %2:rgpr = t2ADCrs %0, %1, 19, 14, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
+ t2CMPri %2, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.1, 0, $cpsr
+ t2B %bb.2, 14, $noreg
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ %3:rgpr = t2MOVi 1, 14, $noreg, $noreg
+ $r0 = COPY %3
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %4:rgpr = t2MOVi 0, 14, $noreg, $noreg
+ $r0 = COPY %4
+ tBX_RET 14, $noreg, implicit $r0
+
+...
diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
new file mode 100644
index 0000000000000..7e5ba56a2f7ca
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -verify-machineinstrs | FileCheck %s
+
+define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_ext_i8_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: lsl r1, r1, #24
+; CHECK-NEXT: asr r0, r0, #24
+; CHECK-NEXT: sub r0, r0, r1, asr #24
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: rsbmi r0, r0, #0
+; CHECK-NEXT: bx lr
+ %aext = sext i8 %a to i64
+ %bext = sext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i8
+ ret i8 %trunc
+}
>From f52d1984224304984142acaa9861d3cd5d9873e8 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 13 Apr 2026 19:11:18 -0400
Subject: [PATCH 2/2] [ARM] Add missing optimize compare candidates to
isOptimizeCompareCandidate
I noticed some were missing when one of the IR I was working on did not optimize it.
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 18 ++++++++++++++++++
...ephole-opt-optimize-compare-adc-shifted.mir | 6 ++----
.../peephole-opt-optimize-compare-t2adcrs.mir | 3 +--
llvm/test/CodeGen/ARM/peephole-rsb.ll | 3 +--
4 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 3b1b8673e56a0..55b409dc7b4fb 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2767,25 +2767,43 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
[[fallthrough]];
case ARM::RSBrr:
case ARM::RSBri:
+ case ARM::RSBrsi:
+ case ARM::RSBrsr:
case ARM::RSCrr:
case ARM::RSCri:
+ case ARM::RSCrsr:
+ case ARM::RSCrsi:
case ARM::ADDrr:
case ARM::ADDri:
+ case ARM::ADDrsi:
+ case ARM::ADDrsr:
case ARM::ADCrr:
case ARM::ADCri:
+ case ARM::ADCrsi:
+ case ARM::ADCrsr:
case ARM::SUBrr:
case ARM::SUBri:
+ case ARM::SUBrsr:
+ case ARM::SUBrsi:
case ARM::SBCrr:
case ARM::SBCri:
+ case ARM::SBCrsi:
+ case ARM::SBCrsr:
case ARM::t2RSBri:
+ case ARM::t2RSBrr:
+ case ARM::t2RSBrs:
case ARM::t2ADDrr:
case ARM::t2ADDri:
+ case ARM::t2ADDrs:
case ARM::t2ADCrr:
case ARM::t2ADCri:
+ case ARM::t2ADCrs:
case ARM::t2SUBrr:
case ARM::t2SUBri:
+ case ARM::t2SUBrs:
case ARM::t2SBCrr:
case ARM::t2SBCri:
+ case ARM::t2SBCrs:
case ARM::ANDrr:
case ARM::ANDri:
case ARM::ANDrsr:
diff --git a/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir
index 41d7e81be9449..1dc7d676cafc3 100644
--- a/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir
+++ b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-adc-shifted.mir
@@ -23,8 +23,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK-NEXT: [[ADCrsi:%[0-9]+]]:gpr = ADCrsi [[COPY]], [[COPY1]], 234, 14 /* CC::al */, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
- ; CHECK-NEXT: CMPri [[ADCrsi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[ADCrsi:%[0-9]+]]:gpr = ADCrsi [[COPY]], [[COPY1]], 234, 14 /* CC::al */, $noreg, def $cpsr, implicit $cpsr, implicit-def $cpsr
; CHECK-NEXT: Bcc %bb.1, 0 /* CC::eq */, $cpsr
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
@@ -74,8 +73,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2
- ; CHECK-NEXT: [[ADCrsr:%[0-9]+]]:gprnopc = ADCrsr [[COPY]], [[COPY1]], [[COPY2]], 2, 14 /* CC::al */, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
- ; CHECK-NEXT: CMPri [[ADCrsr]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[ADCrsr:%[0-9]+]]:gprnopc = ADCrsr [[COPY]], [[COPY1]], [[COPY2]], 2, 14 /* CC::al */, $noreg, def $cpsr, implicit $cpsr, implicit-def $cpsr
; CHECK-NEXT: Bcc %bb.1, 0 /* CC::eq */, $cpsr
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir
index 844d53397e1c1..2968d268e8cdc 100644
--- a/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir
+++ b/llvm/test/CodeGen/ARM/peephole-opt-optimize-compare-t2adcrs.mir
@@ -23,8 +23,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
- ; CHECK-NEXT: [[t2ADCrs:%[0-9]+]]:rgpr = t2ADCrs [[COPY]], [[COPY1]], 19, 14 /* CC::al */, $noreg, $noreg, implicit $cpsr, implicit-def $cpsr
- ; CHECK-NEXT: t2CMPri [[t2ADCrs]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[t2ADCrs:%[0-9]+]]:rgpr = t2ADCrs [[COPY]], [[COPY1]], 19, 14 /* CC::al */, $noreg, def $cpsr, implicit $cpsr, implicit-def $cpsr
; CHECK-NEXT: t2Bcc %bb.1, 0 /* CC::eq */, $cpsr
; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
index 7e5ba56a2f7ca..91ba40e16761a 100644
--- a/llvm/test/CodeGen/ARM/peephole-rsb.ll
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -7,8 +7,7 @@ define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: lsl r1, r1, #24
; CHECK-NEXT: asr r0, r0, #24
-; CHECK-NEXT: sub r0, r0, r1, asr #24
-; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: subs r0, r0, r1, asr #24
; CHECK-NEXT: rsbmi r0, r0, #0
; CHECK-NEXT: bx lr
%aext = sext i8 %a to i64
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