[llvm] [AArch64] Define APAS, BRB and TRCIT as SYS aliases (PR #203563)
Jonathan Thackray via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 08:24:26 PDT 2026
https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/203563
`APAS`, `BRB IALL/INJ` and `TRCIT` use `SYS` encodings, so define them
as aliases of SYSxt instead of separate instructions.
Check that the preferred architectural aliases are printed when their
features are enabled and that disassembly falls back to the generic SYS
spelling when not enabled.
>From 802ac0b98763ae4753ebe9b900d593984ea53fdf Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Fri, 12 Jun 2026 15:29:37 +0100
Subject: [PATCH] [AArch64] Define APAS, BRB and TRCIT as SYS aliases
`APAS`, `BRB IALL/INJ` and `TRCIT` use `SYS` encodings, so define them
as aliases of SYSxt instead of separate instructions.
Check that the preferred architectural aliases are printed when their
features are enabled and that disassembly falls back to the generic SYS
spelling when not enabled.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 19 ---------------
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 21 +++++++---------
llvm/test/MC/AArch64/arm64-aliases.s | 24 +++++++++++++++++++
3 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index c252f4933dc18..787a11401cb6e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1848,12 +1848,6 @@ class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
let Inst{7-5} = Op2;
}
-class APASI : SimpleSystemI<0, (ins GPR64:$Xt), "apas", "\t$Xt">, Sched<[]> {
- bits<5> Xt;
- let Inst{20-5} = 0b0111001110000000;
- let Inst{4-0} = Xt;
-}
-
// Hint instructions that take both a CRm and a 3-bit immediate.
// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
// model patterns with sufficiently fine granularity
@@ -13097,19 +13091,6 @@ class LRCPC3NEONLdStSingle<bit L, dag oops, dag iops, string asm, string cst>
let hasSideEffects = 1;
}
-//---
-// Instrumentation Extension (FEAT_ITE)
-//---
-
-let Predicates = [HasITE] in
-def TRCIT : RtSystemI<0b0, (outs), (ins GPR64:$Rt), "trcit", "\t$Rt"> {
- let Inst{20-19} = 0b01;
- let Inst{18-16} = 0b011;
- let Inst{15-12} = 0b0111;
- let Inst{11-8} = 0b0010;
- let Inst{7-5} = 0b111;
-}
-
// * RCWCAS family
// * RCW<OP> family
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index d1fe1718dcc44..a8afffceaa961 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1614,16 +1614,6 @@ def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;
def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;
}
-// Branch Record Buffer two-word mnemonic instructions
-class BRBEI<bits<3> op2, string keyword>
- : SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> {
- let Inst{31-8} = 0b110101010000100101110010;
- let Inst{7-5} = op2;
- let Predicates = [HasBRBE];
-}
-def BRB_IALL: BRBEI<0b100, "\tiall">;
-def BRB_INJ: BRBEI<0b101, "\tinj">;
-
}
// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ
@@ -2552,6 +2542,14 @@ def SYSLxt : SystemLXtI<1, "sysl">;
def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
(SYSxt timm32_0_7:$op1, sys_cr_op:$Cn,
sys_cr_op:$Cm, timm32_0_7:$op2, XZR)>;
+def : InstAlias<"apas $Xt",
+ (SYSxt 6, 7, 0, 0, GPR64:$Xt), 2>;
+def : InstAlias<"brb\tiall",
+ (SYSxt 1, 7, 2, 4, XZR), 2>, Requires<[HasBRBE]>;
+def : InstAlias<"brb\tinj",
+ (SYSxt 1, 7, 2, 5, XZR), 2>, Requires<[HasBRBE]>;
+def : InstAlias<"trcit $Rt",
+ (SYSxt 3, 7, 2, 7, GPR64:$Rt), 2>, Requires<[HasITE]>;
//===----------------------------------------------------------------------===//
@@ -3081,9 +3079,6 @@ let Predicates = [HasLSUI] in {
defm : STOPregisterLSUI<"sttset","LDTSET">; // STTSETx
}
-// v9.6-a FEAT_RME_GPC3
-def APAS : APASI;
-
// v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
diff --git a/llvm/test/MC/AArch64/arm64-aliases.s b/llvm/test/MC/AArch64/arm64-aliases.s
index ae157c676c95f..fd529791eb679 100644
--- a/llvm/test/MC/AArch64/arm64-aliases.s
+++ b/llvm/test/MC/AArch64/arm64-aliases.s
@@ -1,4 +1,9 @@
; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding -print-imm-hex < %s | FileCheck %s
+; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,+ite -filetype=obj < %s | llvm-objdump -d --mattr=+ite --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-ITE
+; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,+ite -filetype=obj < %s | llvm-objdump -d --mattr=-ite --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-NO-ITE
+; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,+brbe -filetype=obj < %s | llvm-objdump -d --mattr=+brbe --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-BRBE
+; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,+brbe -filetype=obj < %s | llvm-objdump -d --mattr=-brbe --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-NO-BRBE
+; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -filetype=obj < %s | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-RME
foo:
;-----------------------------------------------------------------------------
@@ -526,6 +531,25 @@ foo:
sys #4, c8, c7, #6, x31
; CHECK: tlbi vmalls12e1
+ sys #3, c7, c2, #7, x2
+; CHECK-ITE: trcit x2
+; CHECK-NO-ITE: sys #3, c7, c2, #7, x2
+ sys #3, c7, c2, #7
+; CHECK-ITE: trcit xzr
+; CHECK-NO-ITE: sys #3, c7, c2, #7
+
+ sys #1, c7, c2, #4
+; CHECK-BRBE: brb iall
+; CHECK-NO-BRBE: sys #1, c7, c2, #4
+ sys #1, c7, c2, #5
+; CHECK-BRBE: brb inj
+; CHECK-NO-BRBE: sys #1, c7, c2, #5
+
+ sys #6, c7, c0, #0, x3
+; CHECK-RME: apas x3
+ sys #6, c7, c0, #0
+; CHECK-RME: apas xzr
+
ic ialluis
; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5]
ic iallu
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