[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for pk_f64 fadd, fmul and fma (PR #203559)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 08:12:42 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
---
Patch is 23.09 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203559.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+9-2)
- (modified) llvm/test/CodeGen/AMDGPU/packed-fp64.ll (+238-22)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 76a7ed6e54299..680edd0b1249c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -165,6 +165,9 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
case UniV32S32:
return MRI.getType(Reg) == LLT::fixed_vector(32, 32) &&
MUI.isUniformAtDef(Reg);
+ case UniV2S64:
+ return MRI.getType(Reg) == LLT::fixed_vector(2, 64) &&
+ MUI.isUniformAtDef(Reg);
case UniB32:
return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isUniformAtDef(Reg);
case UniB64:
@@ -1476,7 +1479,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
hasSALUFloat)
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
.Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32, VgprV2S32}}})
- .Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32, VgprV2S32}}});
+ .Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32, VgprV2S32}}})
+ .Any({{UniV2S64}, {{UniInVgprV2S64}, {VgprV2S64, VgprV2S64}}})
+ .Any({{DivV2S64}, {{VgprV2S64}, {VgprV2S64, VgprV2S64}}});
addRulesForGOpcs({G_FSUB, G_STRICT_FSUB}, Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
@@ -1516,7 +1521,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
{{SgprV2S16}, {SgprV2S16, SgprV2S16, SgprV2S16}, ScalarizeToS16},
hasSALUFloat)
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16, VgprV2S16}},
- !hasSALUFloat);
+ !hasSALUFloat)
+ .Any({{UniV2S64}, {{UniInVgprV2S64}, {VgprV2S64, VgprV2S64, VgprV2S64}}})
+ .Any({{DivV2S64}, {{VgprV2S64}, {VgprV2S64, VgprV2S64, VgprV2S64}}});
addRulesForGOpcs({G_AMDGPU_FMED3}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16, Vgpr16}})
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
index fecf30d8d8f63..86ae25aee5236 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-GISEL %s
define amdgpu_kernel void @fadd_v2_vv(ptr addrspace(1) %a) {
; GFX1251-LABEL: fadd_v2_vv:
@@ -70,16 +70,24 @@ define amdgpu_kernel void @fadd_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x
; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1251-GISEL-NEXT: s_clause 0x1
; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
-; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX1251-GISEL-NEXT: s_endpgm
%add = fadd <2 x double> %x, %y
store <2 x double> %add, ptr addrspace(1) %a, align 8
@@ -662,9 +670,14 @@ define amdgpu_kernel void @fadd_v2_v_fneg(ptr addrspace(1) %a, double %x) {
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1251-GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
; GFX1251-GISEL-NEXT: s_endpgm
@@ -703,10 +716,15 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, double %x) {
; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
+; GFX1251-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
; GFX1251-GISEL-NEXT: s_endpgm
@@ -745,10 +763,15 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, double %x) {
; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[6:7], -s[2:3], -s[2:3]
+; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
+; GFX1251-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
; GFX1251-GISEL-NEXT: s_endpgm
@@ -792,9 +815,13 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, double %x, do
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
; GFX1251-GISEL-NEXT: s_endpgm
@@ -833,14 +860,18 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, double %x, do
; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1251-GISEL-NEXT: s_clause 0x1
; GFX1251-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[8:9], s[4:5], 0x34 nv
; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
-; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[6:7], -s[2:3], -s[2:3]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[6:7]
+; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s11, v5
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
; GFX1251-GISEL-NEXT: s_endpgm
@@ -923,16 +954,24 @@ define amdgpu_kernel void @fmul_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x
; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1251-GISEL-NEXT: s_clause 0x1
; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
-; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX1251-GISEL-NEXT: s_endpgm
%mul = fmul <2 x double> %x, %y
store <2 x double> %mul, ptr addrspace(1) %a, align 8
@@ -1433,9 +1472,14 @@ define amdgpu_kernel void @fmul_v2_v_fneg(ptr addrspace(1) %a, double %x) {
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1251-GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
; GFX1251-GISEL-NEXT: s_endpgm
@@ -1530,9 +1574,17 @@ define amdgpu_kernel void @fma_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[0:3], v[0:3], v[4:7], v[8:11]
; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX1251-GISEL-NEXT: s_endpgm
%fma = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %x, <2 x double> %y, <2 x double> %z)
@@ -1867,3 +1919,167 @@ entry:
store <2 x double> %r, ptr addrspace(1) %out, align 16
ret void
}
+
+define void @strict_fadd_v2_ss(<2 x double> inreg %x, <2 x double> inreg %y, ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: strict_fadd_v2_ss:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v5, s19
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_pk_add_f64 v[2:5], v[6:9], v[2:5]
+; GFX1251-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1251-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1251-GISEL-LABEL: strict_fadd_v2_ss:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[18:19]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_pk_add_f64 v[2:5], v[2:5], v[6:9]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1251-GISEL-NEXT: s_set_pc_i64 s[30:31]
+ %add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ store <2 x double> %add, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define void @strict_fadd_v2_vv(<2 x double> %x, <2 x double> %y, ptr addrspace(1) %a) {
+; GFX1251-LABEL: strict_fadd_v2_vv:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-NEXT: global_store_b128 v[8:9], v[0:3], off
+; GFX1251-NEXT: s_set_pc_i64 s[30:31]
+ %add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ store <2 x double> %add, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define void @strict_fmul_v2_ss(<2 x double> inreg %x, <2 x double> inreg %y, ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: strict_fmul_v2_ss:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v5, s19
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[2:5], v[6:9], v[2:5]
+; GFX1251-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1251-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1251-GISEL-LABEL: strict_fmul_v2_ss:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[18:19]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[2:5], v[2:5], v[6:9]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1251-GISEL-NEXT: s_set_pc_i64 s[30:31]
+ %mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ store <2 x double> %mul, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define void @strict_fmul_v2_vv(<2 x double> %x, <2 x double> %y, ptr addrspace(1) %a) {
+; GFX1251-LABEL: strict_fmul_v2_vv:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-NEXT: global_store_b128 v[8:9], v[0:3], off
+; GFX1251-NEXT: s_set_pc_i64 s[30:31]
+ %mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ store <2 x double> %mul, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define void @strict_fma_v2_ss(<2 x double> inreg %x, <2 x double> inreg %y, <2 x double> ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203559
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