[llvm] AMDGPU/GlobalISel: Switch some tests to -new-reg-bank-select (PR #203557)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 08:09:57 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
---
Patch is 651.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203557.diff
13 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll (+9-17)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+805-682)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (+802-677)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll (+186-380)
- (modified) llvm/test/CodeGen/AMDGPU/gws_agpr.ll (+66-31)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll (+191-203)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll (+71-95)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.ll (+554-425)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp10.ll (+555-426)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.ll (+246-207)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+1125-735)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+1125-735)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+457-329)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
index 55b7c745b471c..7c478f93c6952 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=irtranslator -o - %s | FileCheck %s
define float @test_atomicrmw_fadd(ptr addrspace(3) %addr) {
; CHECK-LABEL: name: test_atomicrmw_fadd
@@ -40,10 +40,8 @@ define float @test_atomicrmw_fsub(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](s32)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fsub ptr addrspace(3) %addr, float 1.0 seq_cst
ret float %oldval
@@ -93,10 +91,8 @@ define <2 x half> @test_atomicrmw_fsub_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fsub ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
ret <2 x half> %oldval
@@ -131,10 +127,8 @@ define <2 x half> @test_atomicrmw_fmin_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fmin ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
ret <2 x half> %oldval
@@ -169,10 +163,8 @@ define <2 x half> @test_atomicrmw_fmax_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fmax ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
ret <2 x half> %oldval
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
index b0d486396bfb1..19bd666db37e5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,GISEL %s
-; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,CGP %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
@@ -194,144 +194,182 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[0:1], 0
-; CHECK-NEXT: s_mov_b32 s0, 1
-; CHECK-NEXT: s_cbranch_vccz .LBB1_2
+; CHECK-NEXT: v_cmp_ne_u64_e64 s[0:1], s[0:1], 0
+; CHECK-NEXT: s_mov_b32 s6, 1
+; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; CHECK-NEXT: s_cbranch_scc0 .LBB1_2
; CHECK-NEXT: ; %bb.1:
-; CHECK-NEXT: s_ashr_i32 s6, s3, 31
-; CHECK-NEXT: s_ashr_i32 s8, s5, 31
-; CHECK-NEXT: s_add_u32 s0, s2, s6
-; CHECK-NEXT: s_addc_u32 s1, s3, s6
-; CHECK-NEXT: s_add_u32 s10, s4, s8
-; CHECK-NEXT: s_mov_b32 s9, s8
-; CHECK-NEXT: s_addc_u32 s11, s5, s8
-; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s10
-; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s11
+; CHECK-NEXT: s_ashr_i32 s0, s3, 31
+; CHECK-NEXT: s_ashr_i32 s6, s5, 31
+; CHECK-NEXT: s_add_u32 s10, s2, s0
+; CHECK-NEXT: s_addc_u32 s11, s3, s0
+; CHECK-NEXT: s_add_u32 s8, s4, s6
; CHECK-NEXT: s_mov_b32 s7, s6
-; CHECK-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7]
-; CHECK-NEXT: s_sub_u32 s3, 0, s10
+; CHECK-NEXT: s_addc_u32 s9, s5, s6
+; CHECK-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s8
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s9
+; CHECK-NEXT: s_mov_b32 s1, s0
+; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1]
+; CHECK-NEXT: s_sub_u32 s3, 0, s8
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; CHECK-NEXT: s_subb_u32 s5, 0, s11
+; CHECK-NEXT: s_subb_u32 s5, 0, s9
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v0
-; CHECK-NEXT: v_cvt_u32_f32_e32 v7, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s3, v6, 0
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s3, v7, v[1:2]
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v6, v[2:3]
-; CHECK-NEXT: v_mul_lo_u32 v2, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v7, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v6, v4
-; CHECK-NEXT: v_mul_hi_u32 v5, v6, v4
-; CHECK-NEXT: v_mul_lo_u32 v8, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v0
-; CHECK-NEXT: v_addc_u32_e32 v7, vcc, v7, v1, vcc
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s3, v6, 0
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s3, v7, v[1:2]
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v6, v[2:3]
-; CHECK-NEXT: v_mul_lo_u32 v3, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v7, v0
-; CHECK-NEXT: v_mul_lo_u32 v2, v6, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v3, v6, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_mul_lo_u32 v2, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v6, v0
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v2, s12, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, s12, v1
-; CHECK-NEXT: v_mul_lo_u32 v4, s13, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, s13, v0
-; CHECK-NEXT: v_mov_b32_e32 v7, s13
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v4, s12, v1
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, s13, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v4, s13, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s10, v6, 0
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v2
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s10, v4, v[1:2]
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s12, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, s11
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s11, v6, v[2:3]
-; CHECK-NEXT: v_subb_u32_e64 v2, s[0:1], v7, v4, vcc
-; CHECK-NEXT: v_sub_i32_e64 v3, s[0:1], s13, v4
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v0
-; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s11, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v5, s[0:1]
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s10, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s11, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v3
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
-; CHECK-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9]
-; CHECK-NEXT: v_xor_b32_e32 v0, s0, v0
-; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
-; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
+; CHECK-NEXT: v_mul_hi_u32 v2, s3, v0
+; CHECK-NEXT: v_readfirstlane_b32 s13, v0
+; CHECK-NEXT: s_mul_i32 s15, s3, s13
+; CHECK-NEXT: v_readfirstlane_b32 s12, v1
+; CHECK-NEXT: v_readfirstlane_b32 s16, v2
+; CHECK-NEXT: v_mul_hi_u32 v2, v0, s15
+; CHECK-NEXT: s_mul_i32 s14, s3, s12
+; CHECK-NEXT: s_add_u32 s14, s14, s16
+; CHECK-NEXT: s_mul_i32 s16, s5, s13
+; CHECK-NEXT: s_add_u32 s14, s16, s14
+; CHECK-NEXT: v_readfirstlane_b32 s16, v2
+; CHECK-NEXT: s_mul_i32 s17, s13, s14
+; CHECK-NEXT: v_mul_hi_u32 v2, v1, s15
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s14
+; CHECK-NEXT: s_mul_i32 s18, s12, s15
+; CHECK-NEXT: s_add_u32 s16, s16, s17
+; CHECK-NEXT: s_cselect_b32 s17, 1, 0
+; CHECK-NEXT: s_add_u32 s16, s16, s18
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_i32 s17, s17, s15
+; CHECK-NEXT: v_readfirstlane_b32 s15, v2
+; CHECK-NEXT: v_readfirstlane_b32 s16, v0
+; CHECK-NEXT: s_mul_i32 s18, s12, s14
+; CHECK-NEXT: s_add_u32 s15, s15, s16
+; CHECK-NEXT: s_cselect_b32 s16, 1, 0
+; CHECK-NEXT: s_add_u32 s15, s15, s18
+; CHECK-NEXT: s_cselect_b32 s18, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, v1, s14
+; CHECK-NEXT: s_add_i32 s16, s16, s18
+; CHECK-NEXT: s_add_u32 s14, s15, s17
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_i32 s16, s16, s15
+; CHECK-NEXT: v_readfirstlane_b32 s15, v0
+; CHECK-NEXT: s_add_i32 s15, s15, s16
+; CHECK-NEXT: s_add_u32 s13, s13, s14
+; CHECK-NEXT: v_mov_b32_e32 v0, s13
+; CHECK-NEXT: v_mul_hi_u32 v0, s3, v0
+; CHECK-NEXT: s_mul_i32 s14, s3, s13
+; CHECK-NEXT: s_addc_u32 s12, s12, s15
+; CHECK-NEXT: s_mul_i32 s3, s3, s12
+; CHECK-NEXT: v_readfirstlane_b32 s15, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s14
+; CHECK-NEXT: v_mul_hi_u32 v1, s13, v0
+; CHECK-NEXT: s_add_u32 s3, s3, s15
+; CHECK-NEXT: s_mul_i32 s5, s5, s13
+; CHECK-NEXT: s_add_u32 s3, s5, s3
+; CHECK-NEXT: v_readfirstlane_b32 s5, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-NEXT: s_mul_i32 s15, s13, s3
+; CHECK-NEXT: v_mul_hi_u32 v0, s12, v0
+; CHECK-NEXT: v_mul_hi_u32 v2, s13, v1
+; CHECK-NEXT: s_mul_i32 s14, s12, s14
+; CHECK-NEXT: s_add_u32 s5, s5, s15
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_u32 s5, s5, s14
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s15, s15, s5
+; CHECK-NEXT: v_readfirstlane_b32 s5, v0
+; CHECK-NEXT: v_readfirstlane_b32 s14, v2
+; CHECK-NEXT: s_mul_i32 s3, s12, s3
+; CHECK-NEXT: s_add_u32 s5, s5, s14
+; CHECK-NEXT: s_cselect_b32 s14, 1, 0
+; CHECK-NEXT: s_add_u32 s3, s5, s3
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, s12, v1
+; CHECK-NEXT: s_add_i32 s5, s14, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s15
+; CHECK-NEXT: s_cselect_b32 s14, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s5, s14
+; CHECK-NEXT: v_readfirstlane_b32 s14, v0
+; CHECK-NEXT: s_add_i32 s14, s14, s5
+; CHECK-NEXT: s_add_u32 s3, s13, s3
+; CHECK-NEXT: v_mov_b32_e32 v0, s3
+; CHECK-NEXT: v_mul_hi_u32 v0, s10, v0
+; CHECK-NEXT: s_addc_u32 s5, s12, s14
+; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: s_mul_i32 s13, s10, s5
+; CHECK-NEXT: v_readfirstlane_b32 s12, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s11
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s3
+; CHECK-NEXT: v_mul_hi_u32 v2, s10, v1
+; CHECK-NEXT: s_mul_i32 s14, s11, s3
+; CHECK-NEXT: s_add_u32 s12, s12, s13
+; CHECK-NEXT: s_cselect_b32 s13, 1, 0
+; CHECK-NEXT: s_add_u32 s12, s12, s14
+; CHECK-NEXT: s_cselect_b32 s3, 1, 0
+; CHECK-NEXT: s_add_i32 s13, s13, s3
+; CHECK-NEXT: v_readfirstlane_b32 s3, v0
+; CHECK-NEXT: v_readfirstlane_b32 s12, v2
+; CHECK-NEXT: s_mul_i32 s5, s11, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s12
+; CHECK-NEXT: s_cselect_b32 s12, 1, 0
+; CHECK-NEXT: s_add_u32 s3, s3, s5
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s12, s5
+; CHECK-NEXT: s_add_u32 s12, s3, s13
+; CHECK-NEXT: v_mul_hi_u32 v0, s11, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s12
+; CHECK-NEXT: v_mul_hi_u32 v1, s8, v1
+; CHECK-NEXT: s_cselect_b32 s3, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s5, s3
+; CHECK-NEXT: v_readfirstlane_b32 s3, v0
+; CHECK-NEXT: s_add_i32 s13, s3, s5
+; CHECK-NEXT: v_readfirstlane_b32 s5, v1
+; CHECK-NEXT: s_mul_i32 s14, s8, s13
+; CHECK-NEXT: s_add_u32 s5, s14, s5
+; CHECK-NEXT: s_mul_i32 s14, s9, s12
+; CHECK-NEXT: s_mul_i32 s3, s8, s12
+; CHECK-NEXT: s_add_u32 s5, s14, s5
+; CHECK-NEXT: s_sub_u32 s3, s10, s3
+; CHECK-NEXT: s_cselect_b32 s10, 1, 0
+; CHECK-NEXT: s_subb_u32 s14, s11, s5
+; CHECK-NEXT: s_sub_i32 s5, s11, s5
+; CHECK-NEXT: s_cmp_ge_u32 s14, s9
+; CHECK-NEXT: s_cselect_b32 s11, -1, 0
+; CHECK-NEXT: s_cmp_ge_u32 s3, s8
+; CHECK-NEXT: s_cselect_b32 s15, -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s14, s9
+; CHECK-NEXT: s_cselect_b32 s14, s15, s11
+; CHECK-NEXT: s_sub_u32 s3, s3, s8
+; CHECK-NEXT: s_cselect_b32 s11, 1, 0
+; CHECK-NEXT: s_cmp_lg_u32 s10, 0
+; CHECK-NEXT: s_subb_u32 s5, s5, s9
+; CHECK-NEXT: s_cmp_lg_u32 s11, 0
+; CHECK-NEXT: s_subb_u32 s5, s5, 0
+; CHECK-NEXT: s_add_u32 s10, s12, 1
+; CHECK-NEXT: s_addc_u32 s11, s13, 0
+; CHECK-NEXT: s_cmp_ge_u32 s5, s9
+; CHECK-NEXT: s_cselect_b32 s15, -1, 0
+; CHECK-NEXT: s_cmp_ge_u32 s3, s8
+; CHECK-NEXT: s_cselect_b32 s3, -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s5, s9
+; CHECK-NEXT: s_cselect_b32 s3, s3, s15
+; CHECK-NEXT: s_add_u32 s8, s10, 1
+; CHECK-NEXT: s_addc_u32 s9, s11, 0
+; CHECK-NEXT: s_cmp_lg_u32 s3, 0
+; CHECK-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
+; CHECK-NEXT: s_cmp_lg_u32 s14, 0
+; CHECK-NEXT: s_cselect_b64 s[8:9], s[8:9], s[12:13]
+; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[6:7]
+; CHECK-NEXT: s_xor_b64 s[6:7], s[8:9], s[0:1]
+; CHECK-NEXT: s_sub_u32 s0, s6, s0
+; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
-; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
+; CHECK-NEXT: ; implicit-def: $sgpr0_sgpr1
; CHECK-NEXT: .LBB1_3: ; %Flow
-; CHECK-NEXT: s_xor_b32 s0, s0, 1
-; CHECK-NEXT: s_cmp_lg_u32 s0, 0
+; CHECK-NEXT: s_xor_b32 s1, s6, 1
+; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
@@ -339,22 +377,32 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0
-; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT: v_readfirstlane_b32 s1, v0
+; CHECK-NEXT: s_mul_i32 s0, s0, s1
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s0
+; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_add_i32 s0, s1, s0
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, v0, s4
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_subrev_i32_e64 v2, s[0:1], s4, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: .LBB1_5: ; %.split
+; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_mul_i32 s3, s0, s4
+; CHECK-NEXT: s_sub_i32 s3, s2, s3
+; CHECK-NEXT: s_cmp_ge_u32 s3, s4
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s2, s0, 1
+; CHECK-NEXT: s_cmp_lg_u32 s5, 0
+; CHECK-NEXT: s_cselect_b32 s2, s2, s0
+; CHECK-NEXT: s_su...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203557
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