[llvm] AMDGPU/GlobalISel: Switch some tests to -new-reg-bank-select (PR #203557)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 08:08:46 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/203557
None
>From 3f51f92b16b21e993a9cd12be09a04a9d4e720cd Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Fri, 12 Jun 2026 17:01:38 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Switch some tests to -new-reg-bank-select
---
.../GlobalISel/irtranslator-atomicrmw.ll | 26 +-
.../CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 1487 +++++++------
.../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 1479 +++++++------
.../test/CodeGen/AMDGPU/flat-saddr-atomics.ll | 566 ++---
llvm/test/CodeGen/AMDGPU/gws_agpr.ll | 97 +-
.../AMDGPU/llvm.amdgcn.av.load.b128.ll | 394 ++--
.../AMDGPU/llvm.amdgcn.av.store.b128.ll | 166 +-
llvm/test/CodeGen/AMDGPU/llvm.exp.ll | 979 +++++----
llvm/test/CodeGen/AMDGPU/llvm.exp10.ll | 981 +++++----
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll | 453 ++--
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 1860 ++++++++++-------
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 1860 ++++++++++-------
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 786 ++++---
13 files changed, 6192 insertions(+), 4942 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
index 55b7c745b471c..7c478f93c6952 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=irtranslator -o - %s | FileCheck %s
define float @test_atomicrmw_fadd(ptr addrspace(3) %addr) {
; CHECK-LABEL: name: test_atomicrmw_fadd
@@ -40,10 +40,8 @@ define float @test_atomicrmw_fsub(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](s32)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fsub ptr addrspace(3) %addr, float 1.0 seq_cst
ret float %oldval
@@ -93,10 +91,8 @@ define <2 x half> @test_atomicrmw_fsub_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fsub ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
ret <2 x half> %oldval
@@ -131,10 +127,8 @@ define <2 x half> @test_atomicrmw_fmin_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fmin ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
ret <2 x half> %oldval
@@ -169,10 +163,8 @@ define <2 x half> @test_atomicrmw_fmax_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.atomicrmw.end:
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
- ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
- ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%oldval = atomicrmw fmax ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
ret <2 x half> %oldval
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
index b0d486396bfb1..19bd666db37e5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,GISEL %s
-; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,CGP %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
@@ -194,144 +194,182 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[0:1], 0
-; CHECK-NEXT: s_mov_b32 s0, 1
-; CHECK-NEXT: s_cbranch_vccz .LBB1_2
+; CHECK-NEXT: v_cmp_ne_u64_e64 s[0:1], s[0:1], 0
+; CHECK-NEXT: s_mov_b32 s6, 1
+; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; CHECK-NEXT: s_cbranch_scc0 .LBB1_2
; CHECK-NEXT: ; %bb.1:
-; CHECK-NEXT: s_ashr_i32 s6, s3, 31
-; CHECK-NEXT: s_ashr_i32 s8, s5, 31
-; CHECK-NEXT: s_add_u32 s0, s2, s6
-; CHECK-NEXT: s_addc_u32 s1, s3, s6
-; CHECK-NEXT: s_add_u32 s10, s4, s8
-; CHECK-NEXT: s_mov_b32 s9, s8
-; CHECK-NEXT: s_addc_u32 s11, s5, s8
-; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s10
-; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s11
+; CHECK-NEXT: s_ashr_i32 s0, s3, 31
+; CHECK-NEXT: s_ashr_i32 s6, s5, 31
+; CHECK-NEXT: s_add_u32 s10, s2, s0
+; CHECK-NEXT: s_addc_u32 s11, s3, s0
+; CHECK-NEXT: s_add_u32 s8, s4, s6
; CHECK-NEXT: s_mov_b32 s7, s6
-; CHECK-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7]
-; CHECK-NEXT: s_sub_u32 s3, 0, s10
+; CHECK-NEXT: s_addc_u32 s9, s5, s6
+; CHECK-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s8
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s9
+; CHECK-NEXT: s_mov_b32 s1, s0
+; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1]
+; CHECK-NEXT: s_sub_u32 s3, 0, s8
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; CHECK-NEXT: s_subb_u32 s5, 0, s11
+; CHECK-NEXT: s_subb_u32 s5, 0, s9
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v0
-; CHECK-NEXT: v_cvt_u32_f32_e32 v7, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s3, v6, 0
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s3, v7, v[1:2]
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v6, v[2:3]
-; CHECK-NEXT: v_mul_lo_u32 v2, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v7, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v6, v4
-; CHECK-NEXT: v_mul_hi_u32 v5, v6, v4
-; CHECK-NEXT: v_mul_lo_u32 v8, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v0
-; CHECK-NEXT: v_addc_u32_e32 v7, vcc, v7, v1, vcc
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s3, v6, 0
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s3, v7, v[1:2]
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v6, v[2:3]
-; CHECK-NEXT: v_mul_lo_u32 v3, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v7, v0
-; CHECK-NEXT: v_mul_lo_u32 v2, v6, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v3, v6, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_mul_lo_u32 v2, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v6, v0
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v2, s12, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, s12, v1
-; CHECK-NEXT: v_mul_lo_u32 v4, s13, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, s13, v0
-; CHECK-NEXT: v_mov_b32_e32 v7, s13
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v4, s12, v1
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, s13, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v4, s13, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s10, v6, 0
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v2
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s10, v4, v[1:2]
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s12, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, s11
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s11, v6, v[2:3]
-; CHECK-NEXT: v_subb_u32_e64 v2, s[0:1], v7, v4, vcc
-; CHECK-NEXT: v_sub_i32_e64 v3, s[0:1], s13, v4
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v0
-; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s11, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v5, s[0:1]
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s10, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s11, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v3
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
-; CHECK-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9]
-; CHECK-NEXT: v_xor_b32_e32 v0, s0, v0
-; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
-; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
+; CHECK-NEXT: v_mul_hi_u32 v2, s3, v0
+; CHECK-NEXT: v_readfirstlane_b32 s13, v0
+; CHECK-NEXT: s_mul_i32 s15, s3, s13
+; CHECK-NEXT: v_readfirstlane_b32 s12, v1
+; CHECK-NEXT: v_readfirstlane_b32 s16, v2
+; CHECK-NEXT: v_mul_hi_u32 v2, v0, s15
+; CHECK-NEXT: s_mul_i32 s14, s3, s12
+; CHECK-NEXT: s_add_u32 s14, s14, s16
+; CHECK-NEXT: s_mul_i32 s16, s5, s13
+; CHECK-NEXT: s_add_u32 s14, s16, s14
+; CHECK-NEXT: v_readfirstlane_b32 s16, v2
+; CHECK-NEXT: s_mul_i32 s17, s13, s14
+; CHECK-NEXT: v_mul_hi_u32 v2, v1, s15
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s14
+; CHECK-NEXT: s_mul_i32 s18, s12, s15
+; CHECK-NEXT: s_add_u32 s16, s16, s17
+; CHECK-NEXT: s_cselect_b32 s17, 1, 0
+; CHECK-NEXT: s_add_u32 s16, s16, s18
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_i32 s17, s17, s15
+; CHECK-NEXT: v_readfirstlane_b32 s15, v2
+; CHECK-NEXT: v_readfirstlane_b32 s16, v0
+; CHECK-NEXT: s_mul_i32 s18, s12, s14
+; CHECK-NEXT: s_add_u32 s15, s15, s16
+; CHECK-NEXT: s_cselect_b32 s16, 1, 0
+; CHECK-NEXT: s_add_u32 s15, s15, s18
+; CHECK-NEXT: s_cselect_b32 s18, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, v1, s14
+; CHECK-NEXT: s_add_i32 s16, s16, s18
+; CHECK-NEXT: s_add_u32 s14, s15, s17
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_i32 s16, s16, s15
+; CHECK-NEXT: v_readfirstlane_b32 s15, v0
+; CHECK-NEXT: s_add_i32 s15, s15, s16
+; CHECK-NEXT: s_add_u32 s13, s13, s14
+; CHECK-NEXT: v_mov_b32_e32 v0, s13
+; CHECK-NEXT: v_mul_hi_u32 v0, s3, v0
+; CHECK-NEXT: s_mul_i32 s14, s3, s13
+; CHECK-NEXT: s_addc_u32 s12, s12, s15
+; CHECK-NEXT: s_mul_i32 s3, s3, s12
+; CHECK-NEXT: v_readfirstlane_b32 s15, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s14
+; CHECK-NEXT: v_mul_hi_u32 v1, s13, v0
+; CHECK-NEXT: s_add_u32 s3, s3, s15
+; CHECK-NEXT: s_mul_i32 s5, s5, s13
+; CHECK-NEXT: s_add_u32 s3, s5, s3
+; CHECK-NEXT: v_readfirstlane_b32 s5, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-NEXT: s_mul_i32 s15, s13, s3
+; CHECK-NEXT: v_mul_hi_u32 v0, s12, v0
+; CHECK-NEXT: v_mul_hi_u32 v2, s13, v1
+; CHECK-NEXT: s_mul_i32 s14, s12, s14
+; CHECK-NEXT: s_add_u32 s5, s5, s15
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_u32 s5, s5, s14
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s15, s15, s5
+; CHECK-NEXT: v_readfirstlane_b32 s5, v0
+; CHECK-NEXT: v_readfirstlane_b32 s14, v2
+; CHECK-NEXT: s_mul_i32 s3, s12, s3
+; CHECK-NEXT: s_add_u32 s5, s5, s14
+; CHECK-NEXT: s_cselect_b32 s14, 1, 0
+; CHECK-NEXT: s_add_u32 s3, s5, s3
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, s12, v1
+; CHECK-NEXT: s_add_i32 s5, s14, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s15
+; CHECK-NEXT: s_cselect_b32 s14, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s5, s14
+; CHECK-NEXT: v_readfirstlane_b32 s14, v0
+; CHECK-NEXT: s_add_i32 s14, s14, s5
+; CHECK-NEXT: s_add_u32 s3, s13, s3
+; CHECK-NEXT: v_mov_b32_e32 v0, s3
+; CHECK-NEXT: v_mul_hi_u32 v0, s10, v0
+; CHECK-NEXT: s_addc_u32 s5, s12, s14
+; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: s_mul_i32 s13, s10, s5
+; CHECK-NEXT: v_readfirstlane_b32 s12, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s11
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s3
+; CHECK-NEXT: v_mul_hi_u32 v2, s10, v1
+; CHECK-NEXT: s_mul_i32 s14, s11, s3
+; CHECK-NEXT: s_add_u32 s12, s12, s13
+; CHECK-NEXT: s_cselect_b32 s13, 1, 0
+; CHECK-NEXT: s_add_u32 s12, s12, s14
+; CHECK-NEXT: s_cselect_b32 s3, 1, 0
+; CHECK-NEXT: s_add_i32 s13, s13, s3
+; CHECK-NEXT: v_readfirstlane_b32 s3, v0
+; CHECK-NEXT: v_readfirstlane_b32 s12, v2
+; CHECK-NEXT: s_mul_i32 s5, s11, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s12
+; CHECK-NEXT: s_cselect_b32 s12, 1, 0
+; CHECK-NEXT: s_add_u32 s3, s3, s5
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s12, s5
+; CHECK-NEXT: s_add_u32 s12, s3, s13
+; CHECK-NEXT: v_mul_hi_u32 v0, s11, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s12
+; CHECK-NEXT: v_mul_hi_u32 v1, s8, v1
+; CHECK-NEXT: s_cselect_b32 s3, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s5, s3
+; CHECK-NEXT: v_readfirstlane_b32 s3, v0
+; CHECK-NEXT: s_add_i32 s13, s3, s5
+; CHECK-NEXT: v_readfirstlane_b32 s5, v1
+; CHECK-NEXT: s_mul_i32 s14, s8, s13
+; CHECK-NEXT: s_add_u32 s5, s14, s5
+; CHECK-NEXT: s_mul_i32 s14, s9, s12
+; CHECK-NEXT: s_mul_i32 s3, s8, s12
+; CHECK-NEXT: s_add_u32 s5, s14, s5
+; CHECK-NEXT: s_sub_u32 s3, s10, s3
+; CHECK-NEXT: s_cselect_b32 s10, 1, 0
+; CHECK-NEXT: s_subb_u32 s14, s11, s5
+; CHECK-NEXT: s_sub_i32 s5, s11, s5
+; CHECK-NEXT: s_cmp_ge_u32 s14, s9
+; CHECK-NEXT: s_cselect_b32 s11, -1, 0
+; CHECK-NEXT: s_cmp_ge_u32 s3, s8
+; CHECK-NEXT: s_cselect_b32 s15, -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s14, s9
+; CHECK-NEXT: s_cselect_b32 s14, s15, s11
+; CHECK-NEXT: s_sub_u32 s3, s3, s8
+; CHECK-NEXT: s_cselect_b32 s11, 1, 0
+; CHECK-NEXT: s_cmp_lg_u32 s10, 0
+; CHECK-NEXT: s_subb_u32 s5, s5, s9
+; CHECK-NEXT: s_cmp_lg_u32 s11, 0
+; CHECK-NEXT: s_subb_u32 s5, s5, 0
+; CHECK-NEXT: s_add_u32 s10, s12, 1
+; CHECK-NEXT: s_addc_u32 s11, s13, 0
+; CHECK-NEXT: s_cmp_ge_u32 s5, s9
+; CHECK-NEXT: s_cselect_b32 s15, -1, 0
+; CHECK-NEXT: s_cmp_ge_u32 s3, s8
+; CHECK-NEXT: s_cselect_b32 s3, -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s5, s9
+; CHECK-NEXT: s_cselect_b32 s3, s3, s15
+; CHECK-NEXT: s_add_u32 s8, s10, 1
+; CHECK-NEXT: s_addc_u32 s9, s11, 0
+; CHECK-NEXT: s_cmp_lg_u32 s3, 0
+; CHECK-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
+; CHECK-NEXT: s_cmp_lg_u32 s14, 0
+; CHECK-NEXT: s_cselect_b64 s[8:9], s[8:9], s[12:13]
+; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[6:7]
+; CHECK-NEXT: s_xor_b64 s[6:7], s[8:9], s[0:1]
+; CHECK-NEXT: s_sub_u32 s0, s6, s0
+; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
-; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
+; CHECK-NEXT: ; implicit-def: $sgpr0_sgpr1
; CHECK-NEXT: .LBB1_3: ; %Flow
-; CHECK-NEXT: s_xor_b32 s0, s0, 1
-; CHECK-NEXT: s_cmp_lg_u32 s0, 0
+; CHECK-NEXT: s_xor_b32 s1, s6, 1
+; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
@@ -339,22 +377,32 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0
-; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT: v_readfirstlane_b32 s1, v0
+; CHECK-NEXT: s_mul_i32 s0, s0, s1
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s0
+; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_add_i32 s0, s1, s0
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, v0, s4
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_subrev_i32_e64 v2, s[0:1], s4, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: .LBB1_5: ; %.split
+; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_mul_i32 s3, s0, s4
+; CHECK-NEXT: s_sub_i32 s3, s2, s3
+; CHECK-NEXT: s_cmp_ge_u32 s3, s4
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s2, s0, 1
+; CHECK-NEXT: s_cmp_lg_u32 s5, 0
+; CHECK-NEXT: s_cselect_b32 s2, s2, s0
+; CHECK-NEXT: s_sub_i32 s0, s3, s4
+; CHECK-NEXT: s_cmp_lg_u32 s5, 0
+; CHECK-NEXT: s_cselect_b32 s0, s0, s3
+; CHECK-NEXT: s_cmp_ge_u32 s0, s4
+; CHECK-NEXT: s_cselect_b32 s4, 1, 0
+; CHECK-NEXT: s_add_i32 s0, s2, 1
+; CHECK-NEXT: s_mov_b32 s3, s1
+; CHECK-NEXT: s_cmp_lg_u32 s4, 0
+; CHECK-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; CHECK-NEXT: .LBB1_5: ; %.split
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog
%result = sdiv i64 %num, %den
@@ -1039,126 +1087,146 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_sdiv_i64_oddk_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
-; CHECK-NEXT: v_mov_b32_e32 v9, 0xffed2705
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; CHECK-NEXT: v_trunc_f32_e32 v3, v3
-; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
-; CHECK-NEXT: v_cvt_u32_f32_e32 v8, v2
-; CHECK-NEXT: v_cvt_u32_f32_e32 v10, v3
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v8, 0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, v[3:4]
-; CHECK-NEXT: v_mul_hi_u32 v3, v8, v2
-; CHECK-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v8, v[4:5]
-; CHECK-NEXT: v_mul_lo_u32 v4, v10, v2
-; CHECK-NEXT: v_mul_hi_u32 v2, v10, v2
-; CHECK-NEXT: v_mul_lo_u32 v5, v8, v6
-; CHECK-NEXT: v_mul_hi_u32 v7, v8, v6
-; CHECK-NEXT: v_mul_lo_u32 v11, v10, v6
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v11
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; CHECK-NEXT: v_mul_hi_u32 v5, v10, v6
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v2
-; CHECK-NEXT: v_addc_u32_e32 v10, vcc, v10, v3, vcc
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v8, 0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, v[3:4]
-; CHECK-NEXT: v_ashrrev_i32_e32 v9, 31, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v8, v[4:5]
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v9, vcc
-; CHECK-NEXT: v_xor_b32_e32 v4, v0, v9
-; CHECK-NEXT: v_mul_hi_u32 v0, v8, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, v8, v6
-; CHECK-NEXT: v_xor_b32_e32 v5, v1, v9
-; CHECK-NEXT: v_mul_lo_u32 v1, v10, v2
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; CHECK-NEXT: v_xor_b32_e32 v5, v0, v2
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
+; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; CHECK-NEXT: v_trunc_f32_e32 v4, v4
+; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
+; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, 0xffed2705
+; CHECK-NEXT: v_mov_b32_e32 v7, 0x12d8fb
+; CHECK-NEXT: v_mul_hi_u32 v6, v4, v3
+; CHECK-NEXT: v_readfirstlane_b32 s4, v3
+; CHECK-NEXT: s_mul_i32 s6, s4, 0xffed2705
+; CHECK-NEXT: v_readfirstlane_b32 s5, v0
+; CHECK-NEXT: v_readfirstlane_b32 s7, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v3, s6
+; CHECK-NEXT: s_mul_i32 s8, s5, 0xffed2705
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: s_mul_i32 s8, s4, -1
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s8, v6
+; CHECK-NEXT: s_mul_i32 s9, s4, s7
+; CHECK-NEXT: v_mul_hi_u32 v6, v0, s6
+; CHECK-NEXT: v_mul_hi_u32 v3, v3, s7
+; CHECK-NEXT: s_mul_i32 s10, s5, s6
+; CHECK-NEXT: s_add_u32 s8, s8, s9
+; CHECK-NEXT: s_cselect_b32 s9, 1, 0
+; CHECK-NEXT: s_add_u32 s8, s8, s10
+; CHECK-NEXT: s_cselect_b32 s6, 1, 0
+; CHECK-NEXT: s_add_i32 s9, s9, s6
+; CHECK-NEXT: v_readfirstlane_b32 s6, v6
+; CHECK-NEXT: v_readfirstlane_b32 s8, v3
+; CHECK-NEXT: s_mul_i32 s10, s5, s7
+; CHECK-NEXT: s_add_u32 s6, s6, s8
+; CHECK-NEXT: s_cselect_b32 s8, 1, 0
+; CHECK-NEXT: s_add_u32 s6, s6, s10
+; CHECK-NEXT: s_cselect_b32 s10, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s7
+; CHECK-NEXT: s_add_i32 s8, s8, s10
+; CHECK-NEXT: s_add_u32 s6, s6, s9
+; CHECK-NEXT: s_cselect_b32 s7, 1, 0
+; CHECK-NEXT: s_add_i32 s8, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s7, v0
+; CHECK-NEXT: s_add_i32 s7, s7, s8
+; CHECK-NEXT: s_add_u32 s4, s4, s6
+; CHECK-NEXT: v_mul_hi_u32 v0, v4, s4
+; CHECK-NEXT: s_mul_i32 s6, s4, 0xffed2705
+; CHECK-NEXT: s_addc_u32 s5, s5, s7
+; CHECK-NEXT: v_xor_b32_e32 v6, v1, v2
+; CHECK-NEXT: v_readfirstlane_b32 s7, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s6
+; CHECK-NEXT: v_mul_hi_u32 v1, s4, v0
+; CHECK-NEXT: s_mul_i32 s8, s5, 0xffed2705
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: s_mul_i32 s8, s4, -1
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s8, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s7
+; CHECK-NEXT: s_mul_i32 s9, s4, s7
+; CHECK-NEXT: v_mul_hi_u32 v0, s5, v0
+; CHECK-NEXT: v_mul_hi_u32 v3, s4, v1
+; CHECK-NEXT: s_mul_i32 s6, s5, s6
+; CHECK-NEXT: s_add_u32 s8, s8, s9
+; CHECK-NEXT: s_cselect_b32 s9, 1, 0
+; CHECK-NEXT: s_add_u32 s6, s8, s6
+; CHECK-NEXT: s_cselect_b32 s6, 1, 0
+; CHECK-NEXT: s_add_i32 s9, s9, s6
+; CHECK-NEXT: v_readfirstlane_b32 s6, v0
+; CHECK-NEXT: v_readfirstlane_b32 s8, v3
+; CHECK-NEXT: s_mul_i32 s7, s5, s7
+; CHECK-NEXT: s_add_u32 s6, s6, s8
+; CHECK-NEXT: s_cselect_b32 s8, 1, 0
+; CHECK-NEXT: s_add_u32 s6, s6, s7
+; CHECK-NEXT: s_cselect_b32 s7, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, s5, v1
+; CHECK-NEXT: s_add_i32 s7, s8, s7
+; CHECK-NEXT: s_add_u32 s6, s6, s9
+; CHECK-NEXT: s_cselect_b32 s8, 1, 0
+; CHECK-NEXT: s_add_i32 s7, s7, s8
+; CHECK-NEXT: v_readfirstlane_b32 s8, v0
+; CHECK-NEXT: s_add_i32 s8, s8, s7
+; CHECK-NEXT: s_add_u32 s4, s4, s6
+; CHECK-NEXT: s_addc_u32 s5, s5, s8
+; CHECK-NEXT: v_mul_hi_u32 v0, v5, s4
+; CHECK-NEXT: v_mul_lo_u32 v1, v5, s5
+; CHECK-NEXT: v_mul_lo_u32 v3, v6, s4
+; CHECK-NEXT: v_mul_hi_u32 v4, v5, s5
+; CHECK-NEXT: v_mul_hi_u32 v9, v6, s5
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v1, v10, v2
-; CHECK-NEXT: v_mul_hi_u32 v2, v8, v6
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v3, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v10, v6
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_mul_hi_u32 v3, v10, v6
+; CHECK-NEXT: v_mul_hi_u32 v3, v6, s4
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; CHECK-NEXT: v_mul_lo_u32 v1, v6, s5
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v8, v0
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v10, v1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v2, v4, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v4, v1
-; CHECK-NEXT: v_mul_lo_u32 v7, v5, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0
-; CHECK-NEXT: v_mov_b32_e32 v6, 0x12d8fb
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v7, v4, v1
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, v5, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v7, v3
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v8, v5, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v7, 0
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v2
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v8, v[1:2]
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT: v_subb_u32_e64 v1, s[4:5], v5, v2, vcc
-; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v5, v2
-; CHECK-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v1, v0
+; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v8, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v3
+; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v7, v9, v[1:2]
+; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT: v_subb_u32_e64 v1, s[4:5], v6, v3, vcc
+; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v6, v3
+; CHECK-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v7
+; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
-; CHECK-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, v3, s[4:5]
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v7
-; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v6
+; CHECK-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, v4, s[4:5]
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v8
+; CHECK-NEXT: v_addc_u32_e32 v5, vcc, 0, v9, vcc
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v7
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v3
-; CHECK-NEXT: v_addc_u32_e32 v5, vcc, 0, v4, vcc
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v4
+; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v5, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc
-; CHECK-NEXT: v_xor_b32_e32 v0, v0, v9
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v9
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
+; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2
+; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %num, 1235195
ret i64 %result
@@ -1170,465 +1238,520 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; GISEL-NEXT: v_mov_b32_e32 v6, 0xffed2705
+; GISEL-NEXT: s_mov_b32 s8, 1
+; GISEL-NEXT: s_cmp_lg_u32 s8, 0
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
-; GISEL-NEXT: v_trunc_f32_e32 v5, v5
-; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
-; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v4
-; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v5
-; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v7, 0
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v8, v[5:6]
-; GISEL-NEXT: s_mov_b32 s4, 1
-; GISEL-NEXT: s_cmp_lg_u32 s4, 0
-; GISEL-NEXT: s_subb_u32 s6, 0, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], s6, v7, v[9:10]
-; GISEL-NEXT: v_mul_hi_u32 v10, v7, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, v8, v4
-; GISEL-NEXT: v_mul_hi_u32 v12, v8, v4
-; GISEL-NEXT: v_mul_lo_u32 v4, v7, v13
-; GISEL-NEXT: v_mul_hi_u32 v9, v7, v13
-; GISEL-NEXT: v_mul_lo_u32 v14, v8, v13
-; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v15, v4
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v12, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v14, v9
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v6, v4, 0
-; GISEL-NEXT: v_addc_u32_e32 v17, vcc, v8, v9, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v6, v17, v[14:15]
-; GISEL-NEXT: v_mul_hi_u32 v9, v4, v13
-; GISEL-NEXT: v_mul_lo_u32 v18, v17, v13
-; GISEL-NEXT: v_mul_hi_u32 v19, v17, v13
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], s6, v4, v[15:16]
-; GISEL-NEXT: v_mul_lo_u32 v14, v4, v13
-; GISEL-NEXT: v_mul_lo_u32 v15, v17, v13
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v18
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v9
-; GISEL-NEXT: v_mul_hi_u32 v9, v4, v13
-; GISEL-NEXT: v_mul_hi_u32 v13, v17, v13
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v19, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v9, v15
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
+; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
+; GISEL-NEXT: v_trunc_f32_e32 v6, v6
+; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
+; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v5
+; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v6
+; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v1, v4, vcc
+; GISEL-NEXT: v_xor_b32_e32 v1, v0, v4
+; GISEL-NEXT: v_mov_b32_e32 v0, 0xffed2705
+; GISEL-NEXT: v_mul_hi_u32 v8, v0, v7
+; GISEL-NEXT: v_readfirstlane_b32 s7, v7
+; GISEL-NEXT: s_mul_i32 s5, s7, 0xffed2705
+; GISEL-NEXT: v_readfirstlane_b32 s6, v5
+; GISEL-NEXT: v_readfirstlane_b32 s9, v8
+; GISEL-NEXT: v_mul_hi_u32 v8, v7, s5
+; GISEL-NEXT: s_subb_u32 s4, 0, 0
+; GISEL-NEXT: s_mul_i32 s10, s6, 0xffed2705
+; GISEL-NEXT: s_add_u32 s9, s10, s9
+; GISEL-NEXT: s_mul_i32 s10, s4, s7
+; GISEL-NEXT: s_add_u32 s10, s10, s9
+; GISEL-NEXT: v_readfirstlane_b32 s11, v8
+; GISEL-NEXT: s_mul_i32 s12, s7, s10
+; GISEL-NEXT: v_mul_hi_u32 v8, v5, s5
+; GISEL-NEXT: v_mul_hi_u32 v9, v7, s10
+; GISEL-NEXT: s_mul_i32 s13, s6, s5
+; GISEL-NEXT: s_add_u32 s12, s11, s12
+; GISEL-NEXT: s_cselect_b32 s14, 1, 0
+; GISEL-NEXT: s_add_u32 s12, s12, s13
+; GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GISEL-NEXT: s_add_i32 s14, s14, s5
+; GISEL-NEXT: v_readfirstlane_b32 s12, v8
+; GISEL-NEXT: v_readfirstlane_b32 s5, v9
+; GISEL-NEXT: s_mul_i32 s15, s6, s10
+; GISEL-NEXT: s_add_u32 s5, s12, s5
+; GISEL-NEXT: s_cselect_b32 s16, 1, 0
+; GISEL-NEXT: s_add_u32 s5, s5, s15
+; GISEL-NEXT: s_cselect_b32 s15, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v8, v5, s10
+; GISEL-NEXT: s_add_i32 s15, s16, s15
+; GISEL-NEXT: s_add_u32 s5, s5, s14
+; GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; GISEL-NEXT: s_add_i32 s15, s15, s10
+; GISEL-NEXT: v_readfirstlane_b32 s10, v8
+; GISEL-NEXT: s_add_i32 s10, s10, s15
+; GISEL-NEXT: s_add_u32 s5, s7, s5
+; GISEL-NEXT: v_mul_hi_u32 v8, v0, s5
+; GISEL-NEXT: s_mul_i32 s14, s5, 0xffed2705
+; GISEL-NEXT: v_xor_b32_e32 v14, v6, v4
+; GISEL-NEXT: v_mov_b32_e32 v6, s14
+; GISEL-NEXT: s_addc_u32 s10, s6, s10
+; GISEL-NEXT: v_readfirstlane_b32 s15, v8
+; GISEL-NEXT: v_mul_hi_u32 v8, s5, v6
+; GISEL-NEXT: s_mul_i32 s16, s10, 0xffed2705
+; GISEL-NEXT: s_add_u32 s15, s16, s15
+; GISEL-NEXT: s_mul_i32 s4, s4, s5
+; GISEL-NEXT: s_add_u32 s4, s4, s15
+; GISEL-NEXT: v_readfirstlane_b32 s15, v8
+; GISEL-NEXT: v_mov_b32_e32 v8, s4
+; GISEL-NEXT: s_mul_i32 s16, s5, s4
+; GISEL-NEXT: v_mul_hi_u32 v6, s10, v6
+; GISEL-NEXT: v_mul_hi_u32 v9, s5, v8
+; GISEL-NEXT: s_mul_i32 s14, s10, s14
+; GISEL-NEXT: s_add_u32 s15, s15, s16
+; GISEL-NEXT: s_cselect_b32 s16, 1, 0
+; GISEL-NEXT: s_add_u32 s14, s15, s14
+; GISEL-NEXT: s_cselect_b32 s14, 1, 0
+; GISEL-NEXT: s_add_i32 s16, s16, s14
+; GISEL-NEXT: v_readfirstlane_b32 s14, v6
+; GISEL-NEXT: v_readfirstlane_b32 s15, v9
+; GISEL-NEXT: s_mul_i32 s4, s10, s4
+; GISEL-NEXT: s_add_u32 s14, s14, s15
+; GISEL-NEXT: s_cselect_b32 s15, 1, 0
+; GISEL-NEXT: s_add_u32 s4, s14, s4
+; GISEL-NEXT: s_cselect_b32 s14, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v6, s10, v8
+; GISEL-NEXT: s_add_i32 s14, s15, s14
+; GISEL-NEXT: s_add_u32 s4, s4, s16
+; GISEL-NEXT: s_cselect_b32 s15, 1, 0
+; GISEL-NEXT: s_add_i32 s14, s14, s15
+; GISEL-NEXT: v_readfirstlane_b32 s15, v6
+; GISEL-NEXT: s_add_i32 s15, s15, s14
+; GISEL-NEXT: s_add_u32 s4, s5, s4
+; GISEL-NEXT: s_addc_u32 s5, s10, s15
+; GISEL-NEXT: v_mul_hi_u32 v8, v1, s4
+; GISEL-NEXT: v_mul_lo_u32 v9, v1, s5
+; GISEL-NEXT: v_mul_lo_u32 v10, v14, s4
+; GISEL-NEXT: v_mul_hi_u32 v11, v1, s5
+; GISEL-NEXT: v_mov_b32_e32 v6, 0x12d8fb
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v16, vcc, v16, v9
-; GISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v1
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT: v_xor_b32_e32 v18, v0, v9
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v14
-; GISEL-NEXT: v_xor_b32_e32 v19, v1, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v16, v1
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v17, v1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v13, v18, v0
-; GISEL-NEXT: v_mul_lo_u32 v14, v18, v1
-; GISEL-NEXT: v_mul_lo_u32 v15, v19, v0
-; GISEL-NEXT: v_mul_hi_u32 v0, v19, v0
-; GISEL-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v15, v18, v1
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT: v_mul_lo_u32 v14, v19, v1
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT: v_mul_hi_u32 v1, v19, v1
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v0, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v14, v0
-; GISEL-NEXT: v_add_i32_e32 v20, vcc, v1, v0
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v17, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v4, v20, v[1:2]
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v18, v0
-; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], 0, v17, v[13:14]
-; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v19, v15, vcc
-; GISEL-NEXT: v_sub_i32_e64 v13, s[4:5], v19, v15
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v13, vcc
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT: v_add_i32_e32 v16, vcc, 1, v17
-; GISEL-NEXT: v_addc_u32_e32 v18, vcc, 0, v20, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v15, -1, v14, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v19, -1, v0, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v8, v[5:6]
-; GISEL-NEXT: s_mov_b32 s4, 1
-; GISEL-NEXT: s_cmp_lg_u32 s4, 0
-; GISEL-NEXT: s_subb_u32 s6, 0, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], s6, v7, v[0:1]
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v16
-; GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v18, vcc
-; GISEL-NEXT: v_mul_lo_u32 v5, v7, v13
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GISEL-NEXT: v_cndmask_b32_e32 v14, v16, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v16, v18, v1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v5, v7, v13
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GISEL-NEXT: v_mul_lo_u32 v1, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v12, v5
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v10, v14, s4
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_mul_lo_u32 v9, v14, s5
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v5, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v10, v5
-; GISEL-NEXT: v_mul_hi_u32 v10, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v5, v1
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v10, v1
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v7, v0
-; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v8, v1, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v10, 0
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v17, v14, vcc
-; GISEL-NEXT: v_ashrrev_i32_e32 v13, 31, v3
-; GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v6, v11, v[1:2]
-; GISEL-NEXT: v_xor_b32_e32 v1, v5, v9
-; GISEL-NEXT: v_cndmask_b32_e32 v12, v20, v16, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v13
-; GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s6, v10, v[7:8]
-; GISEL-NEXT: v_mul_hi_u32 v6, v10, v0
-; GISEL-NEXT: v_xor_b32_e32 v14, v2, v13
-; GISEL-NEXT: v_mul_lo_u32 v2, v11, v0
-; GISEL-NEXT: v_mul_lo_u32 v7, v10, v5
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v13, vcc
-; GISEL-NEXT: v_mul_hi_u32 v0, v11, v0
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v6, v10, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GISEL-NEXT: v_mul_lo_u32 v7, v11, v5
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GISEL-NEXT: v_mul_hi_u32 v5, v11, v5
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT: v_add_i32_e32 v15, vcc, v9, v8
+; GISEL-NEXT: v_mul_hi_u32 v12, v14, s5
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v6, v15, 0
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT: v_add_i32_e32 v16, vcc, v12, v10
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v16, v[9:10]
+; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
+; GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], 0, v15, v[10:11]
+; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v14, v12, vcc
+; GISEL-NEXT: v_sub_i32_e64 v9, s[4:5], v14, v12
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, -1, v10, s[4:5]
+; GISEL-NEXT: s_subb_u32 s4, 0, 0
+; GISEL-NEXT: s_mul_i32 s5, s4, s7
+; GISEL-NEXT: s_add_u32 s5, s5, s9
+; GISEL-NEXT: s_mul_i32 s8, s7, s5
+; GISEL-NEXT: v_mul_hi_u32 v7, v7, s5
+; GISEL-NEXT: s_add_u32 s8, s11, s8
+; GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GISEL-NEXT: s_add_u32 s8, s8, s13
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: s_add_i32 s9, s9, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v7
+; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
+; GISEL-NEXT: s_mul_i32 s10, s6, s5
+; GISEL-NEXT: s_add_u32 s8, s12, s8
+; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
+; GISEL-NEXT: s_cselect_b32 s11, 1, 0
+; GISEL-NEXT: s_add_u32 s8, s8, s10
+; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
+; GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v5, v5, s5
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, 1, v15
+; GISEL-NEXT: s_add_i32 s10, s11, s10
+; GISEL-NEXT: v_addc_u32_e32 v11, vcc, 0, v16, vcc
+; GISEL-NEXT: s_add_u32 s5, s8, s9
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v6
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GISEL-NEXT: s_add_i32 s10, s10, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GISEL-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v10
+; GISEL-NEXT: s_add_i32 s8, s8, s10
+; GISEL-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc
+; GISEL-NEXT: s_add_u32 s5, s7, s5
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GISEL-NEXT: v_mul_hi_u32 v0, v0, s5
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cndmask_b32_e32 v8, v16, v9, vcc
+; GISEL-NEXT: v_xor_b32_e32 v11, v8, v4
+; GISEL-NEXT: v_ashrrev_i32_e32 v8, 31, v3
+; GISEL-NEXT: s_mul_i32 s7, s5, 0xffed2705
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v15, v1, vcc
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT: s_addc_u32 s6, s6, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GISEL-NEXT: v_xor_b32_e32 v5, v2, v8
+; GISEL-NEXT: v_mul_hi_u32 v2, s5, v0
+; GISEL-NEXT: s_mul_i32 s9, s6, 0xffed2705
+; GISEL-NEXT: s_add_u32 s8, s9, s8
+; GISEL-NEXT: s_mul_i32 s4, s4, s5
+; GISEL-NEXT: s_add_u32 s4, s4, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GISEL-NEXT: s_mul_i32 s9, s5, s4
+; GISEL-NEXT: v_mul_hi_u32 v0, s6, v0
+; GISEL-NEXT: v_mul_hi_u32 v7, s5, v2
+; GISEL-NEXT: s_mul_i32 s7, s6, s7
+; GISEL-NEXT: s_add_u32 s8, s8, s9
+; GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GISEL-NEXT: s_add_u32 s7, s8, s7
+; GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-NEXT: s_add_i32 s9, s9, s7
+; GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GISEL-NEXT: v_readfirstlane_b32 s8, v7
+; GISEL-NEXT: s_mul_i32 s4, s6, s4
+; GISEL-NEXT: s_add_u32 s7, s7, s8
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: s_add_u32 s4, s7, s4
+; GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v0, s6, v2
+; GISEL-NEXT: s_add_i32 s7, s8, s7
+; GISEL-NEXT: s_add_u32 s4, s4, s9
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: s_add_i32 s7, s7, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GISEL-NEXT: s_add_i32 s8, s8, s7
+; GISEL-NEXT: s_add_u32 s4, s5, s4
+; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT: s_addc_u32 s5, s6, s8
+; GISEL-NEXT: v_mul_hi_u32 v0, v5, s4
+; GISEL-NEXT: v_mul_lo_u32 v2, v5, s5
+; GISEL-NEXT: v_xor_b32_e32 v7, v3, v8
+; GISEL-NEXT: v_mul_lo_u32 v3, v7, s4
+; GISEL-NEXT: v_mul_hi_u32 v9, v5, s5
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0
-; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v11, v2, vcc
-; GISEL-NEXT: v_mul_hi_u32 v5, v14, v0
-; GISEL-NEXT: v_mul_lo_u32 v6, v14, v2
-; GISEL-NEXT: v_xor_b32_e32 v10, v3, v13
-; GISEL-NEXT: v_mul_lo_u32 v3, v10, v0
-; GISEL-NEXT: v_mul_hi_u32 v0, v10, v0
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v3, v7, s4
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GISEL-NEXT: v_mul_lo_u32 v2, v7, s5
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v9
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v5, v14, v2
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GISEL-NEXT: v_mul_lo_u32 v6, v10, v2
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v0, v3
-; GISEL-NEXT: v_mul_hi_u32 v6, v10, v2
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v11, 0
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v3
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v2, v0
+; GISEL-NEXT: v_mul_hi_u32 v10, v7, s5
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v12, 0
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v5, v0
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v6, v0
-; GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v15, v[3:4]
-; GISEL-NEXT: v_xor_b32_e32 v12, v12, v9
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v1, v9
-; GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], 0, v11, v[5:6]
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v12, v9, vcc
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v14, v2
-; GISEL-NEXT: v_sub_i32_e64 v5, s[4:5], v10, v7
-; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], v10, v7, vcc
-; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, -1, v6, s[4:5]
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v11
-; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v15, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v9, v0
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v10, v0
+; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v13, v[3:4]
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v11, v4, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v12, v[9:10]
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v5, v2
+; GISEL-NEXT: v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
+; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v7, v3
+; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v12
+; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v13, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v6
-; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v5
+; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v15, v4, vcc
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v13
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v13
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v13
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v13, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v8
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v8
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; CGP-NEXT: v_mov_b32_e32 v6, 0xffed2705
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; CGP-NEXT: v_xor_b32_e32 v9, v0, v5
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
-; CGP-NEXT: v_trunc_f32_e32 v5, v5
-; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
+; CGP-NEXT: v_trunc_f32_e32 v6, v6
+; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v8, v5
-; CGP-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v7, 0
-; CGP-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v8, v[5:6]
-; CGP-NEXT: v_mul_hi_u32 v11, v8, v4
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], -1, v7, v[9:10]
-; CGP-NEXT: v_mul_hi_u32 v9, v7, v4
-; CGP-NEXT: v_mul_lo_u32 v10, v8, v4
-; CGP-NEXT: v_mul_lo_u32 v4, v7, v12
-; CGP-NEXT: v_mul_hi_u32 v13, v7, v12
-; CGP-NEXT: v_mul_lo_u32 v14, v8, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v8, v12
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v11, v13
-; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
-; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v15, v4
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v13, v4
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; CGP-NEXT: v_addc_u32_e32 v16, vcc, v8, v12, vcc
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v6, v4, 0
-; CGP-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v6, v16, v[13:14]
-; CGP-NEXT: v_mul_hi_u32 v17, v4, v12
-; CGP-NEXT: v_mul_lo_u32 v18, v16, v12
-; CGP-NEXT: v_mul_hi_u32 v19, v16, v12
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], -1, v4, v[14:15]
-; CGP-NEXT: v_mul_lo_u32 v13, v4, v12
-; CGP-NEXT: v_mul_lo_u32 v15, v16, v12
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v17, v13
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v18
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_mul_hi_u32 v14, v4, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v16, v12
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v19, v14
-; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
-; CGP-NEXT: v_ashrrev_i32_e32 v17, 31, v1
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v17
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v17, vcc
-; CGP-NEXT: v_xor_b32_e32 v18, v0, v17
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v13
-; CGP-NEXT: v_xor_b32_e32 v19, v1, v17
+; CGP-NEXT: v_mov_b32_e32 v4, 0xffed2705
+; CGP-NEXT: v_cvt_u32_f32_e32 v0, v6
+; CGP-NEXT: v_xor_b32_e32 v10, v1, v5
+; CGP-NEXT: v_mul_hi_u32 v6, v4, v7
+; CGP-NEXT: v_readfirstlane_b32 s6, v7
+; CGP-NEXT: s_mul_i32 s4, s6, 0xffed2705
+; CGP-NEXT: v_readfirstlane_b32 s7, v0
+; CGP-NEXT: v_readfirstlane_b32 s5, v6
+; CGP-NEXT: v_mul_hi_u32 v6, v7, s4
+; CGP-NEXT: s_mul_i32 s8, s7, 0xffed2705
+; CGP-NEXT: s_add_u32 s5, s8, s5
+; CGP-NEXT: s_mul_i32 s8, s6, -1
+; CGP-NEXT: s_add_u32 s5, s8, s5
+; CGP-NEXT: v_readfirstlane_b32 s8, v6
+; CGP-NEXT: s_mul_i32 s9, s6, s5
+; CGP-NEXT: v_mul_hi_u32 v6, v0, s4
+; CGP-NEXT: v_mul_hi_u32 v7, v7, s5
+; CGP-NEXT: s_mul_i32 s10, s7, s4
+; CGP-NEXT: s_add_u32 s11, s8, s9
+; CGP-NEXT: s_cselect_b32 s12, 1, 0
+; CGP-NEXT: s_add_u32 s11, s11, s10
+; CGP-NEXT: s_cselect_b32 s4, 1, 0
+; CGP-NEXT: s_add_i32 s12, s12, s4
+; CGP-NEXT: v_readfirstlane_b32 s11, v6
+; CGP-NEXT: v_readfirstlane_b32 s13, v7
+; CGP-NEXT: s_mul_i32 s14, s7, s5
+; CGP-NEXT: s_add_u32 s4, s11, s13
+; CGP-NEXT: s_cselect_b32 s15, 1, 0
+; CGP-NEXT: s_add_u32 s4, s4, s14
+; CGP-NEXT: s_cselect_b32 s16, 1, 0
+; CGP-NEXT: v_mul_hi_u32 v0, v0, s5
+; CGP-NEXT: s_add_i32 s15, s15, s16
+; CGP-NEXT: s_add_u32 s4, s4, s12
+; CGP-NEXT: s_cselect_b32 s5, 1, 0
+; CGP-NEXT: s_add_i32 s15, s15, s5
+; CGP-NEXT: v_readfirstlane_b32 s12, v0
+; CGP-NEXT: s_add_i32 s5, s12, s15
+; CGP-NEXT: s_add_u32 s4, s6, s4
+; CGP-NEXT: v_mul_hi_u32 v0, v4, s4
+; CGP-NEXT: s_mul_i32 s15, s4, 0xffed2705
+; CGP-NEXT: s_addc_u32 s5, s7, s5
+; CGP-NEXT: s_mul_i32 s17, s5, 0xffed2705
+; CGP-NEXT: v_readfirstlane_b32 s16, v0
+; CGP-NEXT: v_mov_b32_e32 v0, s15
+; CGP-NEXT: v_mul_hi_u32 v1, s4, v0
+; CGP-NEXT: s_add_u32 s16, s17, s16
+; CGP-NEXT: s_mul_i32 s17, s4, -1
+; CGP-NEXT: s_add_u32 s16, s17, s16
+; CGP-NEXT: v_readfirstlane_b32 s17, v1
+; CGP-NEXT: v_mov_b32_e32 v1, s16
+; CGP-NEXT: s_mul_i32 s18, s4, s16
+; CGP-NEXT: v_mul_hi_u32 v0, s5, v0
+; CGP-NEXT: v_mul_hi_u32 v6, s4, v1
+; CGP-NEXT: s_mul_i32 s15, s5, s15
+; CGP-NEXT: s_add_u32 s17, s17, s18
+; CGP-NEXT: s_cselect_b32 s18, 1, 0
+; CGP-NEXT: s_add_u32 s15, s17, s15
+; CGP-NEXT: s_cselect_b32 s15, 1, 0
+; CGP-NEXT: s_add_i32 s18, s18, s15
+; CGP-NEXT: v_readfirstlane_b32 s15, v0
+; CGP-NEXT: v_readfirstlane_b32 s17, v6
+; CGP-NEXT: s_mul_i32 s16, s5, s16
+; CGP-NEXT: s_add_u32 s15, s15, s17
+; CGP-NEXT: s_cselect_b32 s17, 1, 0
+; CGP-NEXT: s_add_u32 s15, s15, s16
+; CGP-NEXT: s_cselect_b32 s16, 1, 0
+; CGP-NEXT: v_mul_hi_u32 v0, s5, v1
+; CGP-NEXT: s_add_i32 s16, s17, s16
+; CGP-NEXT: s_add_u32 s15, s15, s18
+; CGP-NEXT: s_cselect_b32 s17, 1, 0
+; CGP-NEXT: s_add_i32 s16, s16, s17
+; CGP-NEXT: v_readfirstlane_b32 s17, v0
+; CGP-NEXT: s_add_i32 s17, s17, s16
+; CGP-NEXT: s_add_u32 s4, s4, s15
+; CGP-NEXT: s_addc_u32 s5, s5, s17
+; CGP-NEXT: v_mul_hi_u32 v0, v9, s4
+; CGP-NEXT: v_mul_lo_u32 v1, v9, s5
+; CGP-NEXT: v_mul_lo_u32 v7, v10, s4
+; CGP-NEXT: v_mul_hi_u32 v8, v9, s5
+; CGP-NEXT: v_mov_b32_e32 v6, 0x12d8fb
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v15, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v16, v1, vcc
-; CGP-NEXT: v_mul_hi_u32 v12, v18, v0
-; CGP-NEXT: v_mul_lo_u32 v13, v18, v1
-; CGP-NEXT: v_mul_lo_u32 v14, v19, v0
-; CGP-NEXT: v_mul_hi_u32 v0, v19, v0
-; CGP-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
-; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v14, v18, v1
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT: v_mul_lo_u32 v13, v19, v1
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v14
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_mul_hi_u32 v1, v19, v1
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v0, v12
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v13, v0
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v1, v0
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v14, 0
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v4, v15, v[1:2]
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v18, v0
-; CGP-NEXT: v_subb_u32_e64 v1, s[4:5], v19, v12, vcc
-; CGP-NEXT: v_sub_i32_e64 v12, s[4:5], v19, v12
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT: v_mul_hi_u32 v7, v10, s4
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; CGP-NEXT: v_mul_lo_u32 v1, v10, s5
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v7, v1
+; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v1, v0
+; CGP-NEXT: v_mul_hi_u32 v12, v10, s5
+; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v11, 0
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v7
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v6, v12, v[1:2]
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v9, v0
+; CGP-NEXT: v_subb_u32_e64 v1, s[4:5], v10, v7, vcc
+; CGP-NEXT: v_sub_i32_e64 v7, s[4:5], v10, v7
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
-; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v12, vcc
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT: v_add_i32_e32 v18, vcc, 1, v14
-; CGP-NEXT: v_addc_u32_e32 v19, vcc, 0, v15, vcc
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
+; CGP-NEXT: v_cndmask_b32_e64 v1, -1, v8, s[4:5]
+; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT: s_add_u32 s4, s8, s9
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT: s_cselect_b32 s5, 1, 0
+; CGP-NEXT: s_add_u32 s4, s4, s10
+; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT: s_cselect_b32 s4, 1, 0
+; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v11
+; CGP-NEXT: s_add_i32 s5, s5, s4
+; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v12, vcc
+; CGP-NEXT: s_add_u32 s4, s11, s13
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v6
+; CGP-NEXT: s_cselect_b32 s8, 1, 0
+; CGP-NEXT: s_add_u32 s4, s4, s14
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT: v_cndmask_b32_e64 v16, -1, v13, s[4:5]
-; CGP-NEXT: v_cndmask_b32_e32 v20, -1, v0, vcc
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v8, v[5:6]
-; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v18
-; CGP-NEXT: v_addc_u32_e32 v21, vcc, 0, v19, vcc
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], -1, v7, v[0:1]
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; CGP-NEXT: v_cndmask_b32_e32 v0, v18, v5, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v1, v19, v21, vcc
-; CGP-NEXT: v_mul_lo_u32 v5, v7, v12
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; CGP-NEXT: v_cndmask_b32_e32 v0, v14, v0, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v1, v15, v1, vcc
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v10
-; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CGP-NEXT: v_mul_hi_u32 v10, v7, v12
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_mul_lo_u32 v9, v8, v12
-; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9
-; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10
-; CGP-NEXT: v_mul_hi_u32 v11, v8, v12
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9
-; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9
-; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v7, v5
-; CGP-NEXT: v_addc_u32_e64 v12, s[4:5], v8, v9, s[4:5]
-; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v6, v11, 0
-; CGP-NEXT: v_xor_b32_e32 v0, v0, v17
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v17
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v17
-; CGP-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v12, v[8:9]
-; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v17, vcc
-; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3
-; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], -1, v11, v[9:10]
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_mul_hi_u32 v6, v11, v7
-; CGP-NEXT: v_mul_lo_u32 v9, v11, v5
-; CGP-NEXT: v_xor_b32_e32 v10, v2, v8
-; CGP-NEXT: v_mul_lo_u32 v2, v12, v7
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v6, v12, v7
-; CGP-NEXT: v_mul_hi_u32 v7, v11, v5
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v9, v2
-; CGP-NEXT: v_mul_lo_u32 v9, v12, v5
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT: v_mul_hi_u32 v5, v12, v5
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v11, v2
-; CGP-NEXT: v_addc_u32_e32 v5, vcc, v12, v5, vcc
-; CGP-NEXT: v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT: v_mul_lo_u32 v7, v10, v5
-; CGP-NEXT: v_xor_b32_e32 v9, v3, v8
-; CGP-NEXT: v_mul_lo_u32 v3, v9, v2
-; CGP-NEXT: v_mul_hi_u32 v2, v9, v2
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v6, v10, v5
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v7, v3
-; CGP-NEXT: v_mul_lo_u32 v7, v9, v5
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; CGP-NEXT: s_cselect_b32 s9, 1, 0
+; CGP-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
+; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v8
+; CGP-NEXT: s_add_i32 s8, s8, s9
+; CGP-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; CGP-NEXT: s_add_u32 s4, s4, s5
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; CGP-NEXT: s_cselect_b32 s5, 1, 0
+; CGP-NEXT: v_cndmask_b32_e32 v0, v8, v7, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CGP-NEXT: s_add_i32 s8, s8, s5
+; CGP-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT: s_add_i32 s12, s12, s8
+; CGP-NEXT: v_cndmask_b32_e32 v1, v12, v7, vcc
+; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
+; CGP-NEXT: s_add_u32 s4, s6, s4
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
+; CGP-NEXT: v_mul_hi_u32 v4, v4, s4
+; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v2, v3
-; CGP-NEXT: v_mul_hi_u32 v5, v9, v5
-; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, 0
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v11
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v5, v6
-; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v11, v[3:4]
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v9, v5, vcc
-; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CGP-NEXT: s_mul_i32 s6, s4, 0xffed2705
+; CGP-NEXT: v_xor_b32_e32 v8, v2, v7
+; CGP-NEXT: v_mov_b32_e32 v2, s6
+; CGP-NEXT: s_addc_u32 s5, s7, s12
+; CGP-NEXT: v_readfirstlane_b32 s7, v4
+; CGP-NEXT: v_mul_hi_u32 v4, s4, v2
+; CGP-NEXT: s_mul_i32 s8, s5, 0xffed2705
+; CGP-NEXT: s_add_u32 s7, s8, s7
+; CGP-NEXT: s_mul_i32 s8, s4, -1
+; CGP-NEXT: s_add_u32 s7, s8, s7
+; CGP-NEXT: v_readfirstlane_b32 s8, v4
+; CGP-NEXT: v_mov_b32_e32 v4, s7
+; CGP-NEXT: s_mul_i32 s9, s4, s7
+; CGP-NEXT: v_mul_hi_u32 v2, s5, v2
+; CGP-NEXT: v_mul_hi_u32 v5, s4, v4
+; CGP-NEXT: s_mul_i32 s6, s5, s6
+; CGP-NEXT: s_add_u32 s8, s8, s9
+; CGP-NEXT: s_cselect_b32 s9, 1, 0
+; CGP-NEXT: s_add_u32 s6, s8, s6
+; CGP-NEXT: s_cselect_b32 s6, 1, 0
+; CGP-NEXT: s_add_i32 s9, s9, s6
+; CGP-NEXT: v_readfirstlane_b32 s6, v2
+; CGP-NEXT: v_readfirstlane_b32 s8, v5
+; CGP-NEXT: s_mul_i32 s7, s5, s7
+; CGP-NEXT: s_add_u32 s6, s6, s8
+; CGP-NEXT: s_cselect_b32 s8, 1, 0
+; CGP-NEXT: s_add_u32 s6, s6, s7
+; CGP-NEXT: s_cselect_b32 s7, 1, 0
+; CGP-NEXT: v_mul_hi_u32 v2, s5, v4
+; CGP-NEXT: s_add_i32 s7, s8, s7
+; CGP-NEXT: s_add_u32 s6, s6, s9
+; CGP-NEXT: s_cselect_b32 s8, 1, 0
+; CGP-NEXT: s_add_i32 s7, s7, s8
+; CGP-NEXT: v_readfirstlane_b32 s8, v2
+; CGP-NEXT: s_add_i32 s8, s8, s7
+; CGP-NEXT: s_add_u32 s4, s4, s6
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
+; CGP-NEXT: s_addc_u32 s5, s5, s8
+; CGP-NEXT: v_mul_hi_u32 v2, v8, s4
+; CGP-NEXT: v_mul_lo_u32 v4, v8, s5
+; CGP-NEXT: v_xor_b32_e32 v9, v3, v7
+; CGP-NEXT: v_mul_lo_u32 v3, v9, s4
+; CGP-NEXT: v_mul_hi_u32 v5, v8, s5
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; CGP-NEXT: v_mul_hi_u32 v3, v9, s4
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; CGP-NEXT: v_mul_lo_u32 v4, v9, s5
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v3, v2
+; CGP-NEXT: v_mul_hi_u32 v11, v9, s5
+; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v10, 0
+; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v4
+; CGP-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v11, v[3:4]
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v8, v2
+; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v9, v4, vcc
+; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v9, v4
+; CGP-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
-; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; CGP-NEXT: v_cndmask_b32_e64 v3, -1, v6, s[4:5]
-; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v7
-; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
+; CGP-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; CGP-NEXT: v_cndmask_b32_e64 v3, -1, v5, s[4:5]
+; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v10
+; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v11, vcc
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
-; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v6
-; CGP-NEXT: v_addc_u32_e32 v5, vcc, 0, v9, vcc
+; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v5
+; CGP-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT: v_cndmask_b32_e32 v2, v6, v4, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v4, v9, v5, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; CGP-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
-; CGP-NEXT: v_xor_b32_e32 v2, v2, v8
-; CGP-NEXT: v_xor_b32_e32 v3, v3, v8
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; CGP-NEXT: v_xor_b32_e32 v2, v2, v7
+; CGP-NEXT: v_xor_b32_e32 v3, v3, v7
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
+; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i64> %num, <i64 1235195, i64 1235195>
ret <2 x i64> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index 3cd02dd65fd95..8aee15cfc0add 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,GISEL %s
-; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,CGP %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
@@ -190,142 +190,183 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[0:1], 0
-; CHECK-NEXT: s_mov_b32 s0, 1
-; CHECK-NEXT: s_cbranch_vccz .LBB1_2
+; CHECK-NEXT: v_cmp_ne_u64_e64 s[0:1], s[0:1], 0
+; CHECK-NEXT: s_mov_b32 s6, 1
+; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; CHECK-NEXT: s_cbranch_scc0 .LBB1_2
; CHECK-NEXT: ; %bb.1:
-; CHECK-NEXT: s_ashr_i32 s6, s3, 31
-; CHECK-NEXT: s_ashr_i32 s0, s5, 31
-; CHECK-NEXT: s_add_u32 s10, s2, s6
-; CHECK-NEXT: s_addc_u32 s11, s3, s6
-; CHECK-NEXT: s_add_u32 s8, s4, s0
+; CHECK-NEXT: s_ashr_i32 s0, s3, 31
+; CHECK-NEXT: s_ashr_i32 s6, s5, 31
+; CHECK-NEXT: s_add_u32 s8, s2, s0
+; CHECK-NEXT: s_addc_u32 s9, s3, s0
+; CHECK-NEXT: s_add_u32 s10, s4, s6
+; CHECK-NEXT: s_mov_b32 s7, s6
+; CHECK-NEXT: s_addc_u32 s11, s5, s6
+; CHECK-NEXT: s_xor_b64 s[6:7], s[10:11], s[6:7]
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s6
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s7
; CHECK-NEXT: s_mov_b32 s1, s0
-; CHECK-NEXT: s_addc_u32 s9, s5, s0
; CHECK-NEXT: s_xor_b64 s[8:9], s[8:9], s[0:1]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s8
-; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s9
-; CHECK-NEXT: s_mov_b32 s7, s6
-; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[6:7]
-; CHECK-NEXT: s_sub_u32 s3, 0, s8
+; CHECK-NEXT: s_sub_u32 s3, 0, s6
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; CHECK-NEXT: s_subb_u32 s5, 0, s9
+; CHECK-NEXT: s_subb_u32 s5, 0, s7
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v0
-; CHECK-NEXT: v_cvt_u32_f32_e32 v7, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s3, v6, 0
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s3, v7, v[1:2]
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v6, v[2:3]
-; CHECK-NEXT: v_mul_lo_u32 v2, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v7, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v6, v4
-; CHECK-NEXT: v_mul_hi_u32 v5, v6, v4
-; CHECK-NEXT: v_mul_lo_u32 v8, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v0
-; CHECK-NEXT: v_addc_u32_e32 v7, vcc, v7, v1, vcc
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s3, v6, 0
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s3, v7, v[1:2]
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v6, v[2:3]
-; CHECK-NEXT: v_mul_lo_u32 v3, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v7, v0
-; CHECK-NEXT: v_mul_lo_u32 v2, v6, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v3, v6, v4
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_mul_lo_u32 v2, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v6, v0
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v2, s10, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, s10, v1
-; CHECK-NEXT: v_mul_lo_u32 v4, s11, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, s11, v0
-; CHECK-NEXT: v_mov_b32_e32 v7, s11
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v4, s10, v1
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, s11, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v4, s11, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s8, v6, 0
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v2
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s8, v4, v[1:2]
-; CHECK-NEXT: v_mov_b32_e32 v1, s9
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s9, v6, v[2:3]
-; CHECK-NEXT: v_sub_i32_e64 v3, s[0:1], s11, v4
-; CHECK-NEXT: v_subb_u32_e64 v2, s[0:1], v7, v4, vcc
-; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v0
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v2
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v5, s[0:1]
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CHECK-NEXT: v_xor_b32_e32 v0, s6, v0
-; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
-; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
+; CHECK-NEXT: v_mul_hi_u32 v2, s3, v0
+; CHECK-NEXT: v_readfirstlane_b32 s11, v0
+; CHECK-NEXT: s_mul_i32 s13, s3, s11
+; CHECK-NEXT: v_readfirstlane_b32 s10, v1
+; CHECK-NEXT: v_readfirstlane_b32 s14, v2
+; CHECK-NEXT: v_mul_hi_u32 v2, v0, s13
+; CHECK-NEXT: s_mul_i32 s12, s3, s10
+; CHECK-NEXT: s_add_u32 s12, s12, s14
+; CHECK-NEXT: s_mul_i32 s14, s5, s11
+; CHECK-NEXT: s_add_u32 s12, s14, s12
+; CHECK-NEXT: v_readfirstlane_b32 s14, v2
+; CHECK-NEXT: s_mul_i32 s15, s11, s12
+; CHECK-NEXT: v_mul_hi_u32 v2, v1, s13
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s12
+; CHECK-NEXT: s_mul_i32 s16, s10, s13
+; CHECK-NEXT: s_add_u32 s14, s14, s15
+; CHECK-NEXT: s_cselect_b32 s15, 1, 0
+; CHECK-NEXT: s_add_u32 s14, s14, s16
+; CHECK-NEXT: s_cselect_b32 s13, 1, 0
+; CHECK-NEXT: s_add_i32 s15, s15, s13
+; CHECK-NEXT: v_readfirstlane_b32 s13, v2
+; CHECK-NEXT: v_readfirstlane_b32 s14, v0
+; CHECK-NEXT: s_mul_i32 s16, s10, s12
+; CHECK-NEXT: s_add_u32 s13, s13, s14
+; CHECK-NEXT: s_cselect_b32 s14, 1, 0
+; CHECK-NEXT: s_add_u32 s13, s13, s16
+; CHECK-NEXT: s_cselect_b32 s16, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, v1, s12
+; CHECK-NEXT: s_add_i32 s14, s14, s16
+; CHECK-NEXT: s_add_u32 s12, s13, s15
+; CHECK-NEXT: s_cselect_b32 s13, 1, 0
+; CHECK-NEXT: s_add_i32 s14, s14, s13
+; CHECK-NEXT: v_readfirstlane_b32 s13, v0
+; CHECK-NEXT: s_add_i32 s13, s13, s14
+; CHECK-NEXT: s_add_u32 s11, s11, s12
+; CHECK-NEXT: v_mov_b32_e32 v0, s11
+; CHECK-NEXT: v_mul_hi_u32 v0, s3, v0
+; CHECK-NEXT: s_mul_i32 s12, s3, s11
+; CHECK-NEXT: s_addc_u32 s10, s10, s13
+; CHECK-NEXT: s_mul_i32 s3, s3, s10
+; CHECK-NEXT: v_readfirstlane_b32 s13, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s12
+; CHECK-NEXT: v_mul_hi_u32 v1, s11, v0
+; CHECK-NEXT: s_add_u32 s3, s3, s13
+; CHECK-NEXT: s_mul_i32 s5, s5, s11
+; CHECK-NEXT: s_add_u32 s3, s5, s3
+; CHECK-NEXT: v_readfirstlane_b32 s5, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-NEXT: s_mul_i32 s13, s11, s3
+; CHECK-NEXT: v_mul_hi_u32 v0, s10, v0
+; CHECK-NEXT: v_mul_hi_u32 v2, s11, v1
+; CHECK-NEXT: s_mul_i32 s12, s10, s12
+; CHECK-NEXT: s_add_u32 s5, s5, s13
+; CHECK-NEXT: s_cselect_b32 s13, 1, 0
+; CHECK-NEXT: s_add_u32 s5, s5, s12
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s13, s13, s5
+; CHECK-NEXT: v_readfirstlane_b32 s5, v0
+; CHECK-NEXT: v_readfirstlane_b32 s12, v2
+; CHECK-NEXT: s_mul_i32 s3, s10, s3
+; CHECK-NEXT: s_add_u32 s5, s5, s12
+; CHECK-NEXT: s_cselect_b32 s12, 1, 0
+; CHECK-NEXT: s_add_u32 s3, s5, s3
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, s10, v1
+; CHECK-NEXT: s_add_i32 s5, s12, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s13
+; CHECK-NEXT: s_cselect_b32 s12, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s5, s12
+; CHECK-NEXT: v_readfirstlane_b32 s12, v0
+; CHECK-NEXT: s_add_i32 s12, s12, s5
+; CHECK-NEXT: s_add_u32 s3, s11, s3
+; CHECK-NEXT: v_mov_b32_e32 v0, s3
+; CHECK-NEXT: v_mul_hi_u32 v0, s8, v0
+; CHECK-NEXT: s_addc_u32 s5, s10, s12
+; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: s_mul_i32 s11, s8, s5
+; CHECK-NEXT: v_readfirstlane_b32 s10, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s9
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s3
+; CHECK-NEXT: v_mul_hi_u32 v2, s8, v1
+; CHECK-NEXT: s_mul_i32 s12, s9, s3
+; CHECK-NEXT: s_add_u32 s10, s10, s11
+; CHECK-NEXT: s_cselect_b32 s11, 1, 0
+; CHECK-NEXT: s_add_u32 s10, s10, s12
+; CHECK-NEXT: s_cselect_b32 s3, 1, 0
+; CHECK-NEXT: s_add_i32 s11, s11, s3
+; CHECK-NEXT: v_readfirstlane_b32 s3, v0
+; CHECK-NEXT: v_readfirstlane_b32 s10, v2
+; CHECK-NEXT: s_mul_i32 s5, s9, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s10
+; CHECK-NEXT: s_cselect_b32 s10, 1, 0
+; CHECK-NEXT: s_add_u32 s3, s3, s5
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s10, s5
+; CHECK-NEXT: s_add_u32 s3, s3, s11
+; CHECK-NEXT: v_mul_hi_u32 v0, s9, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-NEXT: v_mul_hi_u32 v1, s6, v1
+; CHECK-NEXT: s_cselect_b32 s10, 1, 0
+; CHECK-NEXT: s_add_i32 s5, s5, s10
+; CHECK-NEXT: v_readfirstlane_b32 s10, v0
+; CHECK-NEXT: s_add_i32 s10, s10, s5
+; CHECK-NEXT: v_readfirstlane_b32 s11, v1
+; CHECK-NEXT: s_mul_i32 s10, s6, s10
+; CHECK-NEXT: s_mul_i32 s5, s6, s3
+; CHECK-NEXT: s_add_u32 s10, s10, s11
+; CHECK-NEXT: s_mul_i32 s3, s7, s3
+; CHECK-NEXT: s_add_u32 s3, s3, s10
+; CHECK-NEXT: s_sub_u32 s10, s8, s5
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_subb_u32 s11, s9, s3
+; CHECK-NEXT: s_sub_i32 s3, s9, s3
+; CHECK-NEXT: s_cmp_ge_u32 s11, s7
+; CHECK-NEXT: s_cselect_b32 s8, -1, 0
+; CHECK-NEXT: s_cmp_ge_u32 s10, s6
+; CHECK-NEXT: s_cselect_b32 s9, -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s11, s7
+; CHECK-NEXT: s_cselect_b32 s12, s9, s8
+; CHECK-NEXT: s_sub_u32 s8, s10, s6
+; CHECK-NEXT: s_cselect_b32 s13, 1, 0
+; CHECK-NEXT: s_cmp_lg_u32 s5, 0
+; CHECK-NEXT: s_subb_u32 s3, s3, s7
+; CHECK-NEXT: s_cmp_lg_u32 s13, 0
+; CHECK-NEXT: s_subb_u32 s9, s3, 0
+; CHECK-NEXT: s_cmp_ge_u32 s9, s7
+; CHECK-NEXT: s_cselect_b32 s5, -1, 0
+; CHECK-NEXT: s_cmp_ge_u32 s8, s6
+; CHECK-NEXT: s_cselect_b32 s14, -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s9, s7
+; CHECK-NEXT: s_cselect_b32 s5, s14, s5
+; CHECK-NEXT: s_sub_u32 s6, s8, s6
+; CHECK-NEXT: s_cselect_b32 s14, 1, 0
+; CHECK-NEXT: s_cmp_lg_u32 s13, 0
+; CHECK-NEXT: s_subb_u32 s3, s3, s7
+; CHECK-NEXT: s_cmp_lg_u32 s14, 0
+; CHECK-NEXT: s_subb_u32 s7, s3, 0
+; CHECK-NEXT: s_cmp_lg_u32 s5, 0
+; CHECK-NEXT: s_cselect_b64 s[6:7], s[6:7], s[8:9]
+; CHECK-NEXT: s_cmp_lg_u32 s12, 0
+; CHECK-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
+; CHECK-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]
+; CHECK-NEXT: s_sub_u32 s0, s6, s0
+; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
-; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
+; CHECK-NEXT: ; implicit-def: $sgpr0_sgpr1
; CHECK-NEXT: .LBB1_3: ; %Flow
-; CHECK-NEXT: s_xor_b32 s0, s0, 1
-; CHECK-NEXT: s_cmp_lg_u32 s0, 0
+; CHECK-NEXT: s_xor_b32 s1, s6, 1
+; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
@@ -333,20 +374,29 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0
-; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT: v_readfirstlane_b32 s1, v0
+; CHECK-NEXT: s_mul_i32 s0, s0, s1
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s0
+; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_add_i32 s0, s1, s0
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0
-; CHECK-NEXT: v_mul_lo_u32 v0, v0, s4
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
-; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CHECK-NEXT: .LBB1_5: ; %.split
+; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_mul_i32 s0, s0, s4
+; CHECK-NEXT: s_sub_i32 s0, s2, s0
+; CHECK-NEXT: s_cmp_ge_u32 s0, s4
+; CHECK-NEXT: s_cselect_b32 s2, 1, 0
+; CHECK-NEXT: s_sub_i32 s3, s0, s4
+; CHECK-NEXT: s_cmp_lg_u32 s2, 0
+; CHECK-NEXT: s_cselect_b32 s2, s3, s0
+; CHECK-NEXT: s_cmp_ge_u32 s2, s4
+; CHECK-NEXT: s_cselect_b32 s5, 1, 0
+; CHECK-NEXT: s_sub_i32 s0, s2, s4
+; CHECK-NEXT: s_mov_b32 s3, s1
+; CHECK-NEXT: s_cmp_lg_u32 s5, 0
+; CHECK-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; CHECK-NEXT: .LBB1_5: ; %.split
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog
%result = srem i64 %num, %den
@@ -1024,124 +1074,144 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_srem_i64_oddk_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
-; CHECK-NEXT: v_mov_b32_e32 v9, 0xffed2705
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; CHECK-NEXT: v_trunc_f32_e32 v3, v3
-; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
-; CHECK-NEXT: v_cvt_u32_f32_e32 v8, v2
-; CHECK-NEXT: v_cvt_u32_f32_e32 v10, v3
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v8, 0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, v[3:4]
-; CHECK-NEXT: v_mul_hi_u32 v3, v8, v2
-; CHECK-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v8, v[4:5]
-; CHECK-NEXT: v_mul_lo_u32 v4, v10, v2
-; CHECK-NEXT: v_mul_hi_u32 v2, v10, v2
-; CHECK-NEXT: v_mul_lo_u32 v5, v8, v6
-; CHECK-NEXT: v_mul_hi_u32 v7, v8, v6
-; CHECK-NEXT: v_mul_lo_u32 v11, v10, v6
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v11
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; CHECK-NEXT: v_mul_hi_u32 v5, v10, v6
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v2
-; CHECK-NEXT: v_addc_u32_e32 v10, vcc, v10, v3, vcc
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v8, 0
-; CHECK-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, v[3:4]
-; CHECK-NEXT: v_ashrrev_i32_e32 v9, 31, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v8, v[4:5]
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v9, vcc
-; CHECK-NEXT: v_xor_b32_e32 v4, v0, v9
-; CHECK-NEXT: v_mul_hi_u32 v0, v8, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, v8, v6
-; CHECK-NEXT: v_xor_b32_e32 v5, v1, v9
-; CHECK-NEXT: v_mul_lo_u32 v1, v10, v2
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; CHECK-NEXT: v_xor_b32_e32 v5, v0, v2
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
+; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; CHECK-NEXT: v_trunc_f32_e32 v4, v4
+; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
+; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, 0xffed2705
+; CHECK-NEXT: v_mov_b32_e32 v7, 0x12d8fb
+; CHECK-NEXT: v_mul_hi_u32 v6, v4, v3
+; CHECK-NEXT: v_readfirstlane_b32 s4, v3
+; CHECK-NEXT: s_mul_i32 s6, s4, 0xffed2705
+; CHECK-NEXT: v_readfirstlane_b32 s5, v0
+; CHECK-NEXT: v_readfirstlane_b32 s7, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v3, s6
+; CHECK-NEXT: s_mul_i32 s8, s5, 0xffed2705
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: s_mul_i32 s8, s4, -1
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s8, v6
+; CHECK-NEXT: s_mul_i32 s9, s4, s7
+; CHECK-NEXT: v_mul_hi_u32 v6, v0, s6
+; CHECK-NEXT: v_mul_hi_u32 v3, v3, s7
+; CHECK-NEXT: s_mul_i32 s10, s5, s6
+; CHECK-NEXT: s_add_u32 s8, s8, s9
+; CHECK-NEXT: s_cselect_b32 s9, 1, 0
+; CHECK-NEXT: s_add_u32 s8, s8, s10
+; CHECK-NEXT: s_cselect_b32 s6, 1, 0
+; CHECK-NEXT: s_add_i32 s9, s9, s6
+; CHECK-NEXT: v_readfirstlane_b32 s6, v6
+; CHECK-NEXT: v_readfirstlane_b32 s8, v3
+; CHECK-NEXT: s_mul_i32 s10, s5, s7
+; CHECK-NEXT: s_add_u32 s6, s6, s8
+; CHECK-NEXT: s_cselect_b32 s8, 1, 0
+; CHECK-NEXT: s_add_u32 s6, s6, s10
+; CHECK-NEXT: s_cselect_b32 s10, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, v0, s7
+; CHECK-NEXT: s_add_i32 s8, s8, s10
+; CHECK-NEXT: s_add_u32 s6, s6, s9
+; CHECK-NEXT: s_cselect_b32 s7, 1, 0
+; CHECK-NEXT: s_add_i32 s8, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s7, v0
+; CHECK-NEXT: s_add_i32 s7, s7, s8
+; CHECK-NEXT: s_add_u32 s4, s4, s6
+; CHECK-NEXT: v_mul_hi_u32 v0, v4, s4
+; CHECK-NEXT: s_mul_i32 s6, s4, 0xffed2705
+; CHECK-NEXT: s_addc_u32 s5, s5, s7
+; CHECK-NEXT: v_xor_b32_e32 v6, v1, v2
+; CHECK-NEXT: v_readfirstlane_b32 s7, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s6
+; CHECK-NEXT: v_mul_hi_u32 v1, s4, v0
+; CHECK-NEXT: s_mul_i32 s8, s5, 0xffed2705
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: s_mul_i32 s8, s4, -1
+; CHECK-NEXT: s_add_u32 s7, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s8, v1
+; CHECK-NEXT: v_mov_b32_e32 v1, s7
+; CHECK-NEXT: s_mul_i32 s9, s4, s7
+; CHECK-NEXT: v_mul_hi_u32 v0, s5, v0
+; CHECK-NEXT: v_mul_hi_u32 v3, s4, v1
+; CHECK-NEXT: s_mul_i32 s6, s5, s6
+; CHECK-NEXT: s_add_u32 s8, s8, s9
+; CHECK-NEXT: s_cselect_b32 s9, 1, 0
+; CHECK-NEXT: s_add_u32 s6, s8, s6
+; CHECK-NEXT: s_cselect_b32 s6, 1, 0
+; CHECK-NEXT: s_add_i32 s9, s9, s6
+; CHECK-NEXT: v_readfirstlane_b32 s6, v0
+; CHECK-NEXT: v_readfirstlane_b32 s8, v3
+; CHECK-NEXT: s_mul_i32 s7, s5, s7
+; CHECK-NEXT: s_add_u32 s6, s6, s8
+; CHECK-NEXT: s_cselect_b32 s8, 1, 0
+; CHECK-NEXT: s_add_u32 s6, s6, s7
+; CHECK-NEXT: s_cselect_b32 s7, 1, 0
+; CHECK-NEXT: v_mul_hi_u32 v0, s5, v1
+; CHECK-NEXT: s_add_i32 s7, s8, s7
+; CHECK-NEXT: s_add_u32 s6, s6, s9
+; CHECK-NEXT: s_cselect_b32 s8, 1, 0
+; CHECK-NEXT: s_add_i32 s7, s7, s8
+; CHECK-NEXT: v_readfirstlane_b32 s8, v0
+; CHECK-NEXT: s_add_i32 s8, s8, s7
+; CHECK-NEXT: s_add_u32 s4, s4, s6
+; CHECK-NEXT: s_addc_u32 s5, s5, s8
+; CHECK-NEXT: v_mul_hi_u32 v0, v5, s4
+; CHECK-NEXT: v_mul_lo_u32 v1, v5, s5
+; CHECK-NEXT: v_mul_lo_u32 v3, v6, s4
+; CHECK-NEXT: v_mul_hi_u32 v4, v5, s5
+; CHECK-NEXT: v_mul_hi_u32 v9, v6, s5
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v1, v10, v2
-; CHECK-NEXT: v_mul_hi_u32 v2, v8, v6
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v3, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v10, v6
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_mul_hi_u32 v3, v10, v6
+; CHECK-NEXT: v_mul_hi_u32 v3, v6, s4
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; CHECK-NEXT: v_mul_lo_u32 v1, v6, s5
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v8, v0
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v10, v1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v2, v4, v0
-; CHECK-NEXT: v_mul_lo_u32 v3, v4, v1
-; CHECK-NEXT: v_mul_lo_u32 v7, v5, v0
-; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0
-; CHECK-NEXT: v_mov_b32_e32 v6, 0x12d8fb
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_hi_u32 v7, v4, v1
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, v5, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v7, v3
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v8, v5, v1
-; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, 0
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v7
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v2
-; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v7, v[1:2]
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT: v_subb_u32_e64 v1, s[4:5], v5, v2, vcc
-; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v5, v2
-; CHECK-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6
-; CHECK-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6
-; CHECK-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
-; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v4, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, v1, v0
+; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v4, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v8
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v3
+; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v7, v8, v[1:2]
+; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT: v_subb_u32_e64 v1, s[4:5], v6, v3, vcc
+; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v6, v3
+; CHECK-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v7
+; CHECK-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v5, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v7
+; CHECK-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
+; CHECK-NEXT: v_sub_i32_e32 v7, vcc, v5, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
-; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v2, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[4:5]
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; CHECK-NEXT: v_xor_b32_e32 v0, v0, v9
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v9
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v3, vcc
+; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, v4, s[4:5]
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2
+; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %num, 1235195
ret i64 %result
@@ -1153,457 +1223,512 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; GISEL-NEXT: v_mov_b32_e32 v6, 0xffed2705
+; GISEL-NEXT: s_mov_b32 s8, 1
+; GISEL-NEXT: s_cmp_lg_u32 s8, 0
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
-; GISEL-NEXT: v_trunc_f32_e32 v5, v5
-; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
-; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v4
-; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v5
-; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v7, 0
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v8, v[5:6]
-; GISEL-NEXT: s_mov_b32 s4, 1
-; GISEL-NEXT: s_cmp_lg_u32 s4, 0
-; GISEL-NEXT: s_subb_u32 s6, 0, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], s6, v7, v[9:10]
-; GISEL-NEXT: v_mul_hi_u32 v10, v7, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, v8, v4
-; GISEL-NEXT: v_mul_hi_u32 v12, v8, v4
-; GISEL-NEXT: v_mul_lo_u32 v4, v7, v13
-; GISEL-NEXT: v_mul_hi_u32 v9, v7, v13
-; GISEL-NEXT: v_mul_lo_u32 v14, v8, v13
-; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v15, v4
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v12, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v14, v9
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v6, v4, 0
-; GISEL-NEXT: v_addc_u32_e32 v17, vcc, v8, v9, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v6, v17, v[14:15]
-; GISEL-NEXT: v_mul_hi_u32 v9, v4, v13
-; GISEL-NEXT: v_mul_lo_u32 v18, v17, v13
-; GISEL-NEXT: v_mul_hi_u32 v19, v17, v13
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], s6, v4, v[15:16]
-; GISEL-NEXT: v_mul_lo_u32 v14, v4, v13
-; GISEL-NEXT: v_mul_lo_u32 v15, v17, v13
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v18
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v9
-; GISEL-NEXT: v_mul_hi_u32 v9, v4, v13
-; GISEL-NEXT: v_mul_hi_u32 v13, v17, v13
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v19, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v9, v15
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
+; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
+; GISEL-NEXT: v_trunc_f32_e32 v6, v6
+; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
+; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v5
+; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v6
+; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v1, v4, vcc
+; GISEL-NEXT: v_xor_b32_e32 v1, v0, v4
+; GISEL-NEXT: v_mov_b32_e32 v0, 0xffed2705
+; GISEL-NEXT: v_mul_hi_u32 v8, v0, v7
+; GISEL-NEXT: v_readfirstlane_b32 s7, v7
+; GISEL-NEXT: s_mul_i32 s5, s7, 0xffed2705
+; GISEL-NEXT: v_readfirstlane_b32 s6, v5
+; GISEL-NEXT: v_readfirstlane_b32 s9, v8
+; GISEL-NEXT: v_mul_hi_u32 v8, v7, s5
+; GISEL-NEXT: s_subb_u32 s4, 0, 0
+; GISEL-NEXT: s_mul_i32 s10, s6, 0xffed2705
+; GISEL-NEXT: s_add_u32 s9, s10, s9
+; GISEL-NEXT: s_mul_i32 s10, s4, s7
+; GISEL-NEXT: s_add_u32 s10, s10, s9
+; GISEL-NEXT: v_readfirstlane_b32 s11, v8
+; GISEL-NEXT: s_mul_i32 s12, s7, s10
+; GISEL-NEXT: v_mul_hi_u32 v8, v5, s5
+; GISEL-NEXT: v_mul_hi_u32 v9, v7, s10
+; GISEL-NEXT: s_mul_i32 s13, s6, s5
+; GISEL-NEXT: s_add_u32 s12, s11, s12
+; GISEL-NEXT: s_cselect_b32 s14, 1, 0
+; GISEL-NEXT: s_add_u32 s12, s12, s13
+; GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GISEL-NEXT: s_add_i32 s14, s14, s5
+; GISEL-NEXT: v_readfirstlane_b32 s12, v8
+; GISEL-NEXT: v_readfirstlane_b32 s5, v9
+; GISEL-NEXT: s_mul_i32 s15, s6, s10
+; GISEL-NEXT: s_add_u32 s5, s12, s5
+; GISEL-NEXT: s_cselect_b32 s16, 1, 0
+; GISEL-NEXT: s_add_u32 s5, s5, s15
+; GISEL-NEXT: s_cselect_b32 s15, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v8, v5, s10
+; GISEL-NEXT: s_add_i32 s15, s16, s15
+; GISEL-NEXT: s_add_u32 s5, s5, s14
+; GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; GISEL-NEXT: s_add_i32 s15, s15, s10
+; GISEL-NEXT: v_readfirstlane_b32 s10, v8
+; GISEL-NEXT: s_add_i32 s10, s10, s15
+; GISEL-NEXT: s_add_u32 s5, s7, s5
+; GISEL-NEXT: v_mul_hi_u32 v8, v0, s5
+; GISEL-NEXT: s_mul_i32 s14, s5, 0xffed2705
+; GISEL-NEXT: v_xor_b32_e32 v14, v6, v4
+; GISEL-NEXT: v_mov_b32_e32 v6, s14
+; GISEL-NEXT: s_addc_u32 s10, s6, s10
+; GISEL-NEXT: v_readfirstlane_b32 s15, v8
+; GISEL-NEXT: v_mul_hi_u32 v8, s5, v6
+; GISEL-NEXT: s_mul_i32 s16, s10, 0xffed2705
+; GISEL-NEXT: s_add_u32 s15, s16, s15
+; GISEL-NEXT: s_mul_i32 s4, s4, s5
+; GISEL-NEXT: s_add_u32 s4, s4, s15
+; GISEL-NEXT: v_readfirstlane_b32 s15, v8
+; GISEL-NEXT: v_mov_b32_e32 v8, s4
+; GISEL-NEXT: s_mul_i32 s16, s5, s4
+; GISEL-NEXT: v_mul_hi_u32 v6, s10, v6
+; GISEL-NEXT: v_mul_hi_u32 v9, s5, v8
+; GISEL-NEXT: s_mul_i32 s14, s10, s14
+; GISEL-NEXT: s_add_u32 s15, s15, s16
+; GISEL-NEXT: s_cselect_b32 s16, 1, 0
+; GISEL-NEXT: s_add_u32 s14, s15, s14
+; GISEL-NEXT: s_cselect_b32 s14, 1, 0
+; GISEL-NEXT: s_add_i32 s16, s16, s14
+; GISEL-NEXT: v_readfirstlane_b32 s14, v6
+; GISEL-NEXT: v_readfirstlane_b32 s15, v9
+; GISEL-NEXT: s_mul_i32 s4, s10, s4
+; GISEL-NEXT: s_add_u32 s14, s14, s15
+; GISEL-NEXT: s_cselect_b32 s15, 1, 0
+; GISEL-NEXT: s_add_u32 s4, s14, s4
+; GISEL-NEXT: s_cselect_b32 s14, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v6, s10, v8
+; GISEL-NEXT: s_add_i32 s14, s15, s14
+; GISEL-NEXT: s_add_u32 s4, s4, s16
+; GISEL-NEXT: s_cselect_b32 s15, 1, 0
+; GISEL-NEXT: s_add_i32 s14, s14, s15
+; GISEL-NEXT: v_readfirstlane_b32 s15, v6
+; GISEL-NEXT: s_add_i32 s15, s15, s14
+; GISEL-NEXT: s_add_u32 s4, s5, s4
+; GISEL-NEXT: s_addc_u32 s5, s10, s15
+; GISEL-NEXT: v_mul_hi_u32 v8, v1, s4
+; GISEL-NEXT: v_mul_lo_u32 v9, v1, s5
+; GISEL-NEXT: v_mul_lo_u32 v10, v14, s4
+; GISEL-NEXT: v_mul_hi_u32 v11, v1, s5
+; GISEL-NEXT: v_mov_b32_e32 v6, 0x12d8fb
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v16, vcc, v16, v9
-; GISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v1
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT: v_xor_b32_e32 v18, v0, v9
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v14
-; GISEL-NEXT: v_xor_b32_e32 v19, v1, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v16, v1
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v17, v1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v13, v18, v0
-; GISEL-NEXT: v_mul_lo_u32 v14, v18, v1
-; GISEL-NEXT: v_mul_lo_u32 v15, v19, v0
-; GISEL-NEXT: v_mul_hi_u32 v0, v19, v0
-; GISEL-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v15, v18, v1
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT: v_mul_lo_u32 v14, v19, v1
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT: v_mul_hi_u32 v1, v19, v1
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v0, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v14, v0
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v1, v0
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v17, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v4, v15, v[1:2]
-; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], 0, v17, v[13:14]
-; GISEL-NEXT: v_sub_i32_e32 v16, vcc, v18, v0
-; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v19, v15
-; GISEL-NEXT: v_subb_u32_e64 v17, s[4:5], v19, v15, vcc
-; GISEL-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; GISEL-NEXT: v_sub_i32_e32 v18, vcc, v16, v4
-; GISEL-NEXT: v_subbrev_u32_e32 v19, vcc, 0, v0, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v16, v4
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v18, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v19
-; GISEL-NEXT: v_cndmask_b32_e64 v15, -1, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v20, -1, v0, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v8, v[5:6]
-; GISEL-NEXT: s_mov_b32 s4, 1
-; GISEL-NEXT: s_cmp_lg_u32 s4, 0
-; GISEL-NEXT: s_subb_u32 s6, 0, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], s6, v7, v[0:1]
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v18, v4
-; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v19, vcc
-; GISEL-NEXT: v_mul_lo_u32 v5, v7, v13
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; GISEL-NEXT: v_cndmask_b32_e32 v14, v18, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v18, v19, v1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v5, v7, v13
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GISEL-NEXT: v_mul_lo_u32 v1, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v12, v5
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v10, v14, s4
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_mul_lo_u32 v9, v14, s5
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v5, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v10, v5
-; GISEL-NEXT: v_mul_hi_u32 v10, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v5, v1
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v10, v1
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v7, v0
-; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v8, v1, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v10, 0
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v14, vcc
-; GISEL-NEXT: v_ashrrev_i32_e32 v13, 31, v3
-; GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v6, v11, v[1:2]
-; GISEL-NEXT: v_xor_b32_e32 v1, v5, v9
-; GISEL-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v13
-; GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], s6, v10, v[7:8]
-; GISEL-NEXT: v_mul_hi_u32 v6, v10, v0
-; GISEL-NEXT: v_xor_b32_e32 v14, v2, v13
-; GISEL-NEXT: v_mul_lo_u32 v2, v11, v0
-; GISEL-NEXT: v_mul_lo_u32 v7, v10, v5
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v13, vcc
-; GISEL-NEXT: v_mul_hi_u32 v0, v11, v0
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v6, v10, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GISEL-NEXT: v_mul_lo_u32 v7, v11, v5
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GISEL-NEXT: v_mul_hi_u32 v5, v11, v5
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT: v_add_i32_e32 v15, vcc, v9, v8
+; GISEL-NEXT: v_mul_hi_u32 v12, v14, s5
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v6, v15, 0
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v10
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v12, v[9:10]
+; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
+; GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], 0, v15, v[10:11]
+; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v14, v12, vcc
+; GISEL-NEXT: v_sub_i32_e64 v9, s[4:5], v14, v12
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v10, -1, v10, s[4:5]
+; GISEL-NEXT: s_subb_u32 s4, 0, 0
+; GISEL-NEXT: s_mul_i32 s5, s4, s7
+; GISEL-NEXT: s_add_u32 s5, s5, s9
+; GISEL-NEXT: s_mul_i32 s8, s7, s5
+; GISEL-NEXT: v_mul_hi_u32 v7, v7, s5
+; GISEL-NEXT: s_add_u32 s8, s11, s8
+; GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GISEL-NEXT: s_add_u32 s8, s8, s13
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: s_add_i32 s9, s9, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v7
+; GISEL-NEXT: s_mul_i32 s10, s6, s5
+; GISEL-NEXT: s_add_u32 s8, s12, s8
+; GISEL-NEXT: s_cselect_b32 s11, 1, 0
+; GISEL-NEXT: s_add_u32 s8, s8, s10
+; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
+; GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v5, v5, s5
+; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v1, v6
+; GISEL-NEXT: s_add_i32 s10, s11, s10
+; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
+; GISEL-NEXT: s_add_u32 s5, s8, s9
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v6
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GISEL-NEXT: s_add_i32 s10, s10, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v5
+; GISEL-NEXT: v_cndmask_b32_e32 v12, -1, v12, vcc
+; GISEL-NEXT: v_sub_i32_e32 v13, vcc, v11, v6
+; GISEL-NEXT: s_add_i32 s8, s8, s10
+; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v9, vcc
+; GISEL-NEXT: s_add_u32 s5, s7, s5
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT: v_mul_hi_u32 v0, v0, s5
+; GISEL-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v14, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
+; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
+; GISEL-NEXT: v_xor_b32_e32 v11, v8, v4
+; GISEL-NEXT: v_ashrrev_i32_e32 v8, 31, v3
+; GISEL-NEXT: s_mul_i32 s7, s5, 0xffed2705
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT: s_addc_u32 s6, s6, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GISEL-NEXT: v_xor_b32_e32 v5, v2, v8
+; GISEL-NEXT: v_mul_hi_u32 v2, s5, v0
+; GISEL-NEXT: s_mul_i32 s9, s6, 0xffed2705
+; GISEL-NEXT: s_add_u32 s8, s9, s8
+; GISEL-NEXT: s_mul_i32 s4, s4, s5
+; GISEL-NEXT: s_add_u32 s4, s4, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GISEL-NEXT: s_mul_i32 s9, s5, s4
+; GISEL-NEXT: v_mul_hi_u32 v0, s6, v0
+; GISEL-NEXT: v_mul_hi_u32 v7, s5, v2
+; GISEL-NEXT: s_mul_i32 s7, s6, s7
+; GISEL-NEXT: s_add_u32 s8, s8, s9
+; GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GISEL-NEXT: s_add_u32 s7, s8, s7
+; GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-NEXT: s_add_i32 s9, s9, s7
+; GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GISEL-NEXT: v_readfirstlane_b32 s8, v7
+; GISEL-NEXT: s_mul_i32 s4, s6, s4
+; GISEL-NEXT: s_add_u32 s7, s7, s8
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: s_add_u32 s4, s7, s4
+; GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-NEXT: v_mul_hi_u32 v0, s6, v2
+; GISEL-NEXT: s_add_i32 s7, s8, s7
+; GISEL-NEXT: s_add_u32 s4, s4, s9
+; GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GISEL-NEXT: s_add_i32 s7, s7, s8
+; GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GISEL-NEXT: s_add_i32 s8, s8, s7
+; GISEL-NEXT: s_add_u32 s4, s5, s4
+; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT: s_addc_u32 s5, s6, s8
+; GISEL-NEXT: v_mul_hi_u32 v0, v5, s4
+; GISEL-NEXT: v_mul_lo_u32 v2, v5, s5
+; GISEL-NEXT: v_xor_b32_e32 v7, v3, v8
+; GISEL-NEXT: v_mul_lo_u32 v3, v7, s4
+; GISEL-NEXT: v_mul_hi_u32 v9, v5, s5
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0
-; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v11, v2, vcc
-; GISEL-NEXT: v_mul_hi_u32 v5, v14, v0
-; GISEL-NEXT: v_mul_lo_u32 v6, v14, v2
-; GISEL-NEXT: v_xor_b32_e32 v10, v3, v13
-; GISEL-NEXT: v_mul_lo_u32 v3, v10, v0
-; GISEL-NEXT: v_mul_hi_u32 v0, v10, v0
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v3, v7, s4
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GISEL-NEXT: v_mul_lo_u32 v2, v7, s5
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v9
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v5, v14, v2
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GISEL-NEXT: v_mul_lo_u32 v6, v10, v2
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v0, v3
-; GISEL-NEXT: v_mul_hi_u32 v6, v10, v2
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v11, 0
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v3
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v2, v0
+; GISEL-NEXT: v_mul_hi_u32 v10, v7, s5
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v12, 0
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v5, v0
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v6, v0
-; GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v0, v[3:4]
-; GISEL-NEXT: v_xor_b32_e32 v12, v12, v9
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v1, v9
-; GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], 0, v11, v[5:6]
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v12, v9, vcc
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v14, v2
-; GISEL-NEXT: v_sub_i32_e64 v5, s[4:5], v10, v7
-; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], v10, v7, vcc
-; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v2, v4
-; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v7, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4
-; GISEL-NEXT: v_cndmask_b32_e32 v8, -1, v8, vcc
-; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v7, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v5, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[4:5]
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v13
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v13
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v13
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v13, vcc
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v9, v0
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0
+; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v0, v[3:4]
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v11, v4, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v12, v[9:10]
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v5, v2
+; GISEL-NEXT: v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
+; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v7, v3
+; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v2, v6
+; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v7, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
+; GISEL-NEXT: v_cndmask_b32_e32 v9, -1, v9, vcc
+; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; GISEL-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[4:5]
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v8
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v8
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_srem_v2i64_oddk_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; CGP-NEXT: v_mov_b32_e32 v6, 0xffed2705
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; CGP-NEXT: v_xor_b32_e32 v9, v0, v5
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
-; CGP-NEXT: v_trunc_f32_e32 v5, v5
-; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
+; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
+; CGP-NEXT: v_trunc_f32_e32 v6, v6
+; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v8, v5
-; CGP-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v7, 0
-; CGP-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v8, v[5:6]
-; CGP-NEXT: v_mul_hi_u32 v11, v8, v4
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], -1, v7, v[9:10]
-; CGP-NEXT: v_mul_hi_u32 v9, v7, v4
-; CGP-NEXT: v_mul_lo_u32 v10, v8, v4
-; CGP-NEXT: v_mul_lo_u32 v4, v7, v12
-; CGP-NEXT: v_mul_hi_u32 v13, v7, v12
-; CGP-NEXT: v_mul_lo_u32 v14, v8, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v8, v12
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v11, v13
-; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
-; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v15, v4
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v13, v4
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; CGP-NEXT: v_addc_u32_e32 v16, vcc, v8, v12, vcc
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v6, v4, 0
-; CGP-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v6, v16, v[13:14]
-; CGP-NEXT: v_mul_hi_u32 v17, v4, v12
-; CGP-NEXT: v_mul_lo_u32 v18, v16, v12
-; CGP-NEXT: v_mul_hi_u32 v19, v16, v12
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], -1, v4, v[14:15]
-; CGP-NEXT: v_mul_lo_u32 v13, v4, v12
-; CGP-NEXT: v_mul_lo_u32 v15, v16, v12
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v17, v13
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v18
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_mul_hi_u32 v14, v4, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v16, v12
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v19, v14
-; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
-; CGP-NEXT: v_ashrrev_i32_e32 v17, 31, v1
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v17
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v17, vcc
-; CGP-NEXT: v_xor_b32_e32 v18, v0, v17
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v13
-; CGP-NEXT: v_xor_b32_e32 v19, v1, v17
+; CGP-NEXT: v_mov_b32_e32 v4, 0xffed2705
+; CGP-NEXT: v_cvt_u32_f32_e32 v0, v6
+; CGP-NEXT: v_xor_b32_e32 v10, v1, v5
+; CGP-NEXT: v_mul_hi_u32 v6, v4, v7
+; CGP-NEXT: v_readfirstlane_b32 s6, v7
+; CGP-NEXT: s_mul_i32 s4, s6, 0xffed2705
+; CGP-NEXT: v_readfirstlane_b32 s7, v0
+; CGP-NEXT: v_readfirstlane_b32 s5, v6
+; CGP-NEXT: v_mul_hi_u32 v6, v7, s4
+; CGP-NEXT: s_mul_i32 s8, s7, 0xffed2705
+; CGP-NEXT: s_add_u32 s5, s8, s5
+; CGP-NEXT: s_mul_i32 s8, s6, -1
+; CGP-NEXT: s_add_u32 s5, s8, s5
+; CGP-NEXT: v_readfirstlane_b32 s8, v6
+; CGP-NEXT: s_mul_i32 s9, s6, s5
+; CGP-NEXT: v_mul_hi_u32 v6, v0, s4
+; CGP-NEXT: v_mul_hi_u32 v7, v7, s5
+; CGP-NEXT: s_mul_i32 s10, s7, s4
+; CGP-NEXT: s_add_u32 s11, s8, s9
+; CGP-NEXT: s_cselect_b32 s12, 1, 0
+; CGP-NEXT: s_add_u32 s11, s11, s10
+; CGP-NEXT: s_cselect_b32 s4, 1, 0
+; CGP-NEXT: s_add_i32 s12, s12, s4
+; CGP-NEXT: v_readfirstlane_b32 s11, v6
+; CGP-NEXT: v_readfirstlane_b32 s13, v7
+; CGP-NEXT: s_mul_i32 s14, s7, s5
+; CGP-NEXT: s_add_u32 s4, s11, s13
+; CGP-NEXT: s_cselect_b32 s15, 1, 0
+; CGP-NEXT: s_add_u32 s4, s4, s14
+; CGP-NEXT: s_cselect_b32 s16, 1, 0
+; CGP-NEXT: v_mul_hi_u32 v0, v0, s5
+; CGP-NEXT: s_add_i32 s15, s15, s16
+; CGP-NEXT: s_add_u32 s4, s4, s12
+; CGP-NEXT: s_cselect_b32 s5, 1, 0
+; CGP-NEXT: s_add_i32 s15, s15, s5
+; CGP-NEXT: v_readfirstlane_b32 s12, v0
+; CGP-NEXT: s_add_i32 s5, s12, s15
+; CGP-NEXT: s_add_u32 s4, s6, s4
+; CGP-NEXT: v_mul_hi_u32 v0, v4, s4
+; CGP-NEXT: s_mul_i32 s15, s4, 0xffed2705
+; CGP-NEXT: s_addc_u32 s5, s7, s5
+; CGP-NEXT: s_mul_i32 s17, s5, 0xffed2705
+; CGP-NEXT: v_readfirstlane_b32 s16, v0
+; CGP-NEXT: v_mov_b32_e32 v0, s15
+; CGP-NEXT: v_mul_hi_u32 v1, s4, v0
+; CGP-NEXT: s_add_u32 s16, s17, s16
+; CGP-NEXT: s_mul_i32 s17, s4, -1
+; CGP-NEXT: s_add_u32 s16, s17, s16
+; CGP-NEXT: v_readfirstlane_b32 s17, v1
+; CGP-NEXT: v_mov_b32_e32 v1, s16
+; CGP-NEXT: s_mul_i32 s18, s4, s16
+; CGP-NEXT: v_mul_hi_u32 v0, s5, v0
+; CGP-NEXT: v_mul_hi_u32 v6, s4, v1
+; CGP-NEXT: s_mul_i32 s15, s5, s15
+; CGP-NEXT: s_add_u32 s17, s17, s18
+; CGP-NEXT: s_cselect_b32 s18, 1, 0
+; CGP-NEXT: s_add_u32 s15, s17, s15
+; CGP-NEXT: s_cselect_b32 s15, 1, 0
+; CGP-NEXT: s_add_i32 s18, s18, s15
+; CGP-NEXT: v_readfirstlane_b32 s15, v0
+; CGP-NEXT: v_readfirstlane_b32 s17, v6
+; CGP-NEXT: s_mul_i32 s16, s5, s16
+; CGP-NEXT: s_add_u32 s15, s15, s17
+; CGP-NEXT: s_cselect_b32 s17, 1, 0
+; CGP-NEXT: s_add_u32 s15, s15, s16
+; CGP-NEXT: s_cselect_b32 s16, 1, 0
+; CGP-NEXT: v_mul_hi_u32 v0, s5, v1
+; CGP-NEXT: s_add_i32 s16, s17, s16
+; CGP-NEXT: s_add_u32 s15, s15, s18
+; CGP-NEXT: s_cselect_b32 s17, 1, 0
+; CGP-NEXT: s_add_i32 s16, s16, s17
+; CGP-NEXT: v_readfirstlane_b32 s17, v0
+; CGP-NEXT: s_add_i32 s17, s17, s16
+; CGP-NEXT: s_add_u32 s4, s4, s15
+; CGP-NEXT: s_addc_u32 s5, s5, s17
+; CGP-NEXT: v_mul_hi_u32 v0, v9, s4
+; CGP-NEXT: v_mul_lo_u32 v1, v9, s5
+; CGP-NEXT: v_mul_lo_u32 v7, v10, s4
+; CGP-NEXT: v_mul_hi_u32 v8, v9, s5
+; CGP-NEXT: v_mov_b32_e32 v6, 0x12d8fb
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v15, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v16, v1, vcc
-; CGP-NEXT: v_mul_hi_u32 v12, v18, v0
-; CGP-NEXT: v_mul_lo_u32 v13, v18, v1
-; CGP-NEXT: v_mul_lo_u32 v14, v19, v0
-; CGP-NEXT: v_mul_hi_u32 v0, v19, v0
-; CGP-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
-; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v14, v18, v1
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT: v_mul_lo_u32 v13, v19, v1
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v14
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v0, v12
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v14, v19, v1
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v0
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v12, 0
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v13
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v4, v14, v[1:2]
-; CGP-NEXT: v_sub_i32_e32 v14, vcc, v18, v0
-; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v19, v12
-; CGP-NEXT: v_subb_u32_e64 v15, s[4:5], v19, v12, vcc
-; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT: v_sub_i32_e32 v18, vcc, v14, v4
-; CGP-NEXT: v_subbrev_u32_e32 v19, vcc, 0, v0, vcc
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v14, v4
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v18, v4
-; CGP-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
-; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v19
-; CGP-NEXT: v_cndmask_b32_e64 v16, -1, v1, s[4:5]
-; CGP-NEXT: v_cndmask_b32_e32 v20, -1, v0, vcc
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v8, v[5:6]
-; CGP-NEXT: v_sub_i32_e32 v5, vcc, v18, v4
-; CGP-NEXT: v_subbrev_u32_e32 v21, vcc, 0, v19, vcc
-; CGP-NEXT: v_mad_u64_u32 v[12:13], s[4:5], -1, v7, v[0:1]
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; CGP-NEXT: v_cndmask_b32_e32 v0, v18, v5, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v1, v19, v21, vcc
-; CGP-NEXT: v_mul_lo_u32 v5, v7, v12
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; CGP-NEXT: v_cndmask_b32_e32 v0, v14, v0, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v1, v15, v1, vcc
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v10
-; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CGP-NEXT: v_mul_hi_u32 v10, v7, v12
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_mul_lo_u32 v9, v8, v12
-; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9
-; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10
-; CGP-NEXT: v_mul_hi_u32 v11, v8, v12
-; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9
-; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9
-; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v7, v5
-; CGP-NEXT: v_addc_u32_e64 v12, s[4:5], v8, v9, s[4:5]
-; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v6, v11, 0
-; CGP-NEXT: v_xor_b32_e32 v0, v0, v17
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v17
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v17
-; CGP-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v12, v[8:9]
-; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v17, vcc
-; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3
-; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], -1, v11, v[9:10]
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_mul_hi_u32 v6, v11, v7
-; CGP-NEXT: v_mul_lo_u32 v9, v11, v5
-; CGP-NEXT: v_xor_b32_e32 v10, v2, v8
-; CGP-NEXT: v_mul_lo_u32 v2, v12, v7
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v6, v12, v7
-; CGP-NEXT: v_mul_hi_u32 v7, v11, v5
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v9, v2
-; CGP-NEXT: v_mul_lo_u32 v9, v12, v5
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT: v_mul_hi_u32 v5, v12, v5
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v11, v2
-; CGP-NEXT: v_addc_u32_e32 v5, vcc, v12, v5, vcc
-; CGP-NEXT: v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT: v_mul_lo_u32 v7, v10, v5
-; CGP-NEXT: v_xor_b32_e32 v9, v3, v8
-; CGP-NEXT: v_mul_lo_u32 v3, v9, v2
-; CGP-NEXT: v_mul_hi_u32 v2, v9, v2
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT: v_mul_hi_u32 v6, v10, v5
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v7, v3
-; CGP-NEXT: v_mul_lo_u32 v7, v9, v5
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; CGP-NEXT: v_mul_hi_u32 v7, v10, s4
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; CGP-NEXT: v_mul_lo_u32 v1, v10, s5
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v7, v1
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v2, v3
-; CGP-NEXT: v_mul_hi_u32 v5, v9, v5
-; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, 0
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT: v_add_i32_e32 v8, vcc, v1, v0
+; CGP-NEXT: v_mul_hi_u32 v12, v10, s5
+; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v8, 0
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v11
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v5, v6
-; CGP-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v7, v[3:4]
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v9, v5, vcc
-; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v4
-; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v4
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v7
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v6, v11, v[1:2]
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v9, v0
+; CGP-NEXT: v_subb_u32_e64 v1, s[4:5], v10, v7, vcc
+; CGP-NEXT: v_sub_i32_e64 v7, s[4:5], v10, v7
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
+; CGP-NEXT: v_cndmask_b32_e64 v8, -1, v8, s[4:5]
+; CGP-NEXT: s_add_u32 s4, s8, s9
+; CGP-NEXT: s_cselect_b32 s5, 1, 0
+; CGP-NEXT: s_add_u32 s4, s4, s10
+; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT: s_cselect_b32 s4, 1, 0
+; CGP-NEXT: v_sub_i32_e32 v9, vcc, v0, v6
+; CGP-NEXT: s_add_i32 s5, s5, s4
+; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT: s_add_u32 s4, s11, s13
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v9, v6
+; CGP-NEXT: s_cselect_b32 s8, 1, 0
+; CGP-NEXT: s_add_u32 s4, s4, s14
+; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; CGP-NEXT: s_cselect_b32 s9, 1, 0
+; CGP-NEXT: v_cndmask_b32_e32 v10, -1, v10, vcc
+; CGP-NEXT: v_sub_i32_e32 v11, vcc, v9, v6
+; CGP-NEXT: s_add_i32 s8, s8, s9
+; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v7, vcc
+; CGP-NEXT: s_add_u32 s4, s4, s5
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
+; CGP-NEXT: s_cselect_b32 s5, 1, 0
+; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT: s_add_i32 s8, s8, s5
+; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
+; CGP-NEXT: s_add_i32 s12, s12, s8
+; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
+; CGP-NEXT: s_add_u32 s4, s6, s4
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
+; CGP-NEXT: v_mul_hi_u32 v4, v4, s4
+; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
+; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; CGP-NEXT: s_mul_i32 s6, s4, 0xffed2705
+; CGP-NEXT: v_xor_b32_e32 v8, v2, v7
+; CGP-NEXT: v_mov_b32_e32 v2, s6
+; CGP-NEXT: s_addc_u32 s5, s7, s12
+; CGP-NEXT: v_readfirstlane_b32 s7, v4
+; CGP-NEXT: v_mul_hi_u32 v4, s4, v2
+; CGP-NEXT: s_mul_i32 s8, s5, 0xffed2705
+; CGP-NEXT: s_add_u32 s7, s8, s7
+; CGP-NEXT: s_mul_i32 s8, s4, -1
+; CGP-NEXT: s_add_u32 s7, s8, s7
+; CGP-NEXT: v_readfirstlane_b32 s8, v4
+; CGP-NEXT: v_mov_b32_e32 v4, s7
+; CGP-NEXT: s_mul_i32 s9, s4, s7
+; CGP-NEXT: v_mul_hi_u32 v2, s5, v2
+; CGP-NEXT: v_mul_hi_u32 v5, s4, v4
+; CGP-NEXT: s_mul_i32 s6, s5, s6
+; CGP-NEXT: s_add_u32 s8, s8, s9
+; CGP-NEXT: s_cselect_b32 s9, 1, 0
+; CGP-NEXT: s_add_u32 s6, s8, s6
+; CGP-NEXT: s_cselect_b32 s6, 1, 0
+; CGP-NEXT: s_add_i32 s9, s9, s6
+; CGP-NEXT: v_readfirstlane_b32 s6, v2
+; CGP-NEXT: v_readfirstlane_b32 s8, v5
+; CGP-NEXT: s_mul_i32 s7, s5, s7
+; CGP-NEXT: s_add_u32 s6, s6, s8
+; CGP-NEXT: s_cselect_b32 s8, 1, 0
+; CGP-NEXT: s_add_u32 s6, s6, s7
+; CGP-NEXT: s_cselect_b32 s7, 1, 0
+; CGP-NEXT: v_mul_hi_u32 v2, s5, v4
+; CGP-NEXT: s_add_i32 s7, s8, s7
+; CGP-NEXT: s_add_u32 s6, s6, s9
+; CGP-NEXT: s_cselect_b32 s8, 1, 0
+; CGP-NEXT: s_add_i32 s7, s7, s8
+; CGP-NEXT: v_readfirstlane_b32 s8, v2
+; CGP-NEXT: s_add_i32 s8, s8, s7
+; CGP-NEXT: s_add_u32 s4, s4, s6
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
+; CGP-NEXT: s_addc_u32 s5, s5, s8
+; CGP-NEXT: v_mul_hi_u32 v2, v8, s4
+; CGP-NEXT: v_mul_lo_u32 v4, v8, s5
+; CGP-NEXT: v_xor_b32_e32 v9, v3, v7
+; CGP-NEXT: v_mul_lo_u32 v3, v9, s4
+; CGP-NEXT: v_mul_hi_u32 v5, v8, s5
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; CGP-NEXT: v_mul_hi_u32 v3, v9, s4
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; CGP-NEXT: v_mul_lo_u32 v4, v9, s5
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; CGP-NEXT: v_add_i32_e32 v5, vcc, v3, v2
+; CGP-NEXT: v_mul_hi_u32 v11, v9, s5
+; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v5, 0
+; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v4
+; CGP-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v10, v[3:4]
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v8, v2
+; CGP-NEXT: v_subb_u32_e64 v3, s[4:5], v9, v4, vcc
+; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v9, v4
+; CGP-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; CGP-NEXT: v_sub_i32_e32 v8, vcc, v2, v6
+; CGP-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v8, v6
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
; CGP-NEXT: v_cndmask_b32_e32 v9, -1, v9, vcc
-; CGP-NEXT: v_sub_i32_e32 v4, vcc, v7, v4
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CGP-NEXT: v_sub_i32_e32 v6, vcc, v8, v6
+; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
-; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v5, vcc
-; CGP-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[4:5]
+; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v4, vcc
+; CGP-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[4:5]
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; CGP-NEXT: v_xor_b32_e32 v2, v2, v8
-; CGP-NEXT: v_xor_b32_e32 v3, v3, v8
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; CGP-NEXT: v_xor_b32_e32 v2, v2, v7
+; CGP-NEXT: v_xor_b32_e32 v3, v3, v7
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
+; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, <i64 1235195, i64 1235195>
ret <2 x i64> %result
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index 199a65b52a858..1e85db6bec284 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
; Test using saddr addressing mode of flat_* atomic instructions. Make
; sure these are not incorrectly selected before gfx1250.
@@ -12970,52 +12970,28 @@ define float @flat_atomic_fmax_f32_saddr_rtn(ptr inreg %ptr, float %data) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmax_f32_saddr_rtn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_max_f32_e32 v4, v0, v0
-; GFX950-SDAG-NEXT: .LBB118_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_max_f32_e32 v0, v1, v1
-; GFX950-SDAG-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB118_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmax_f32_saddr_rtn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: flat_load_dword v0, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX950-GISEL-NEXT: .LBB118_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v0
-; GFX950-GISEL-NEXT: v_max_f32_e32 v0, v5, v5
-; GFX950-GISEL-NEXT: v_max_f32_e32 v4, v0, v1
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[4:5] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB118_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmax_f32_saddr_rtn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_max_f32_e32 v4, v0, v0
+; GFX950-NEXT: .LBB118_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_max_f32_e32 v0, v1, v1
+; GFX950-NEXT: v_max_f32_e32 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB118_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x float], ptr %ptr, i64 0, i64 10
%result = atomicrmw fmax ptr %gep.0, float %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret float %result
@@ -13032,51 +13008,28 @@ define void @flat_atomic_fmax_f32_saddr_nortn(ptr inreg %ptr, float %data) {
; GFX1250-NEXT: s_wait_storecnt_dscnt 0x0
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmax_f32_saddr_nortn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_max_f32_e32 v4, v0, v0
-; GFX950-SDAG-NEXT: .LBB119_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_max_f32_e32 v0, v1, v1
-; GFX950-SDAG-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB119_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmax_f32_saddr_nortn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_max_f32_e32 v4, v0, v0
-; GFX950-GISEL-NEXT: .LBB119_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_max_f32_e32 v0, v1, v1
-; GFX950-GISEL-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB119_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmax_f32_saddr_nortn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_max_f32_e32 v4, v0, v0
+; GFX950-NEXT: .LBB119_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_max_f32_e32 v0, v1, v1
+; GFX950-NEXT: v_max_f32_e32 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB119_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x float], ptr %ptr, i64 0, i64 10
%unused = atomicrmw fmax ptr %gep.0, float %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret void
@@ -13093,52 +13046,28 @@ define float @flat_atomic_fmin_f32_saddr_rtn(ptr inreg %ptr, float %data) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmin_f32_saddr_rtn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_max_f32_e32 v4, v0, v0
-; GFX950-SDAG-NEXT: .LBB120_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_max_f32_e32 v0, v1, v1
-; GFX950-SDAG-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB120_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmin_f32_saddr_rtn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: flat_load_dword v0, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX950-GISEL-NEXT: .LBB120_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v0
-; GFX950-GISEL-NEXT: v_max_f32_e32 v0, v5, v5
-; GFX950-GISEL-NEXT: v_min_f32_e32 v4, v0, v1
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[4:5] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB120_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmin_f32_saddr_rtn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_max_f32_e32 v4, v0, v0
+; GFX950-NEXT: .LBB120_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_max_f32_e32 v0, v1, v1
+; GFX950-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB120_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x float], ptr %ptr, i64 0, i64 10
%result = atomicrmw fmin ptr %gep.0, float %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret float %result
@@ -13155,51 +13084,28 @@ define void @flat_atomic_fmin_f32_saddr_nortn(ptr inreg %ptr, float %data) {
; GFX1250-NEXT: s_wait_storecnt_dscnt 0x0
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmin_f32_saddr_nortn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_max_f32_e32 v4, v0, v0
-; GFX950-SDAG-NEXT: .LBB121_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_max_f32_e32 v0, v1, v1
-; GFX950-SDAG-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB121_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmin_f32_saddr_nortn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_max_f32_e32 v4, v0, v0
-; GFX950-GISEL-NEXT: .LBB121_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_max_f32_e32 v0, v1, v1
-; GFX950-GISEL-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB121_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmin_f32_saddr_nortn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_max_f32_e32 v4, v0, v0
+; GFX950-NEXT: .LBB121_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_max_f32_e32 v0, v1, v1
+; GFX950-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB121_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x float], ptr %ptr, i64 0, i64 10
%unused = atomicrmw fmin ptr %gep.0, float %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret void
@@ -13299,55 +13205,30 @@ define <2 x half> @flat_atomic_fmax_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmax_v2f16_saddr_rtn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_pk_max_f16 v4, v0, v0
-; GFX950-SDAG-NEXT: .p2align 5, , 4
-; GFX950-SDAG-NEXT: .LBB124_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_pk_max_f16 v0, v1, v1
-; GFX950-SDAG-NEXT: s_nop 0
-; GFX950-SDAG-NEXT: v_pk_max_f16 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB124_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmax_v2f16_saddr_rtn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: flat_load_dword v0, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX950-GISEL-NEXT: .LBB124_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v0, v5, v5
-; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v4, v0, v1
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[4:5] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB124_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmax_v2f16_saddr_rtn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_pk_max_f16 v4, v0, v0
+; GFX950-NEXT: .p2align 5, , 4
+; GFX950-NEXT: .LBB124_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_pk_max_f16 v0, v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_pk_max_f16 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB124_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x <2 x half>], ptr %ptr, i64 0, i64 10
%result = atomicrmw fmax ptr %gep.0, <2 x half> %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret <2 x half> %result
@@ -13382,55 +13263,30 @@ define void @flat_atomic_fmax_v2f16_saddr_nortn(ptr inreg %ptr, <2 x half> %data
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmax_v2f16_saddr_nortn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_pk_max_f16 v4, v0, v0
-; GFX950-SDAG-NEXT: .p2align 5, , 4
-; GFX950-SDAG-NEXT: .LBB125_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_pk_max_f16 v0, v1, v1
-; GFX950-SDAG-NEXT: s_nop 0
-; GFX950-SDAG-NEXT: v_pk_max_f16 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB125_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmax_v2f16_saddr_nortn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v4, v0, v0
-; GFX950-GISEL-NEXT: .p2align 5, , 4
-; GFX950-GISEL-NEXT: .LBB125_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_pk_max_f16 v0, v1, v1
-; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v0, v0, v4
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB125_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmax_v2f16_saddr_nortn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_pk_max_f16 v4, v0, v0
+; GFX950-NEXT: .p2align 5, , 4
+; GFX950-NEXT: .LBB125_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_pk_max_f16 v0, v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_pk_max_f16 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB125_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x <2 x half>], ptr %ptr, i64 0, i64 10
%unused = atomicrmw fmax ptr %gep.0, <2 x half> %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret void
@@ -13466,55 +13322,30 @@ define <2 x half> @flat_atomic_fmin_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmin_v2f16_saddr_rtn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_pk_max_f16 v4, v0, v0
-; GFX950-SDAG-NEXT: .p2align 5, , 4
-; GFX950-SDAG-NEXT: .LBB126_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_pk_max_f16 v0, v1, v1
-; GFX950-SDAG-NEXT: s_nop 0
-; GFX950-SDAG-NEXT: v_pk_min_f16 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB126_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmin_v2f16_saddr_rtn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: flat_load_dword v0, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX950-GISEL-NEXT: .LBB126_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v0, v5, v5
-; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_pk_min_f16 v4, v0, v1
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[4:5] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB126_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmin_v2f16_saddr_rtn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_pk_max_f16 v4, v0, v0
+; GFX950-NEXT: .p2align 5, , 4
+; GFX950-NEXT: .LBB126_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_pk_max_f16 v0, v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_pk_min_f16 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB126_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x <2 x half>], ptr %ptr, i64 0, i64 10
%result = atomicrmw fmin ptr %gep.0, <2 x half> %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret <2 x half> %result
@@ -13549,55 +13380,30 @@ define void @flat_atomic_fmin_v2f16_saddr_nortn(ptr inreg %ptr, <2 x half> %data
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX950-SDAG-LABEL: flat_atomic_fmin_v2f16_saddr_nortn:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-SDAG-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], 0
-; GFX950-SDAG-NEXT: v_pk_max_f16 v4, v0, v0
-; GFX950-SDAG-NEXT: .p2align 5, , 4
-; GFX950-SDAG-NEXT: .LBB127_1: ; %atomicrmw.start
-; GFX950-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_pk_max_f16 v0, v1, v1
-; GFX950-SDAG-NEXT: s_nop 0
-; GFX950-SDAG-NEXT: v_pk_min_f16 v0, v0, v4
-; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-SDAG-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-SDAG-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB127_1
-; GFX950-SDAG-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: flat_atomic_fmin_v2f16_saddr_nortn:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: flat_load_dword v1, v[2:3] offset:40
-; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], 0
-; GFX950-GISEL-NEXT: v_pk_max_f16 v4, v0, v0
-; GFX950-GISEL-NEXT: .p2align 5, , 4
-; GFX950-GISEL-NEXT: .LBB127_1: ; %atomicrmw.start
-; GFX950-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_pk_max_f16 v0, v1, v1
-; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_pk_min_f16 v0, v0, v4
-; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, v0
-; GFX950-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB127_1
-; GFX950-GISEL-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX950-GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX950-LABEL: flat_atomic_fmin_v2f16_saddr_nortn:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: flat_load_dword v1, v[2:3] offset:40
+; GFX950-NEXT: s_mov_b64 s[2:3], 0
+; GFX950-NEXT: v_pk_max_f16 v4, v0, v0
+; GFX950-NEXT: .p2align 5, , 4
+; GFX950-NEXT: .LBB127_1: ; %atomicrmw.start
+; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_pk_max_f16 v0, v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_pk_min_f16 v0, v0, v4
+; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] offset:40 sc0
+; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX950-NEXT: v_mov_b32_e32 v1, v0
+; GFX950-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_cbranch_execnz .LBB127_1
+; GFX950-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX950-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
%gep.0 = getelementptr inbounds [512 x <2 x half>], ptr %ptr, i64 0, i64 10
%unused = atomicrmw fmin ptr %gep.0, <2 x half> %data syncscope("workgroup") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/gws_agpr.ll b/llvm/test/CodeGen/AMDGPU/gws_agpr.ll
index d87dac1d69047..99a76c402e059 100644
--- a/llvm/test/CodeGen/AMDGPU/gws_agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/gws_agpr.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,GISEL %s
define void @gws_init_offset0() #0 {
; CHECK-LABEL: gws_init_offset0:
@@ -76,22 +76,40 @@ define amdgpu_kernel void @gws_init_agpr_offset() #0 {
}
define void @gws_init_agpr_offset_add1() #0 {
-; CHECK-LABEL: gws_init_agpr_offset_add1:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: ;;#ASMSTART
-; CHECK-NEXT: ; def a1
-; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a1
-; CHECK-NEXT: v_readfirstlane_b32 s4, v0
-; CHECK-NEXT: ;;#ASMSTART
-; CHECK-NEXT: ; def a0
-; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: s_lshl_b32 m0, s4, 16
-; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: ds_gws_init a0 offset:1 gds
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_setpc_b64 s[30:31]
+; SDAG-LABEL: gws_init_agpr_offset_add1:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-NEXT: ;;#ASMSTART
+; SDAG-NEXT: ; def a1
+; SDAG-NEXT: ;;#ASMEND
+; SDAG-NEXT: v_accvgpr_read_b32 v0, a1
+; SDAG-NEXT: v_readfirstlane_b32 s4, v0
+; SDAG-NEXT: ;;#ASMSTART
+; SDAG-NEXT: ; def a0
+; SDAG-NEXT: ;;#ASMEND
+; SDAG-NEXT: s_lshl_b32 m0, s4, 16
+; SDAG-NEXT: s_nop 0
+; SDAG-NEXT: ds_gws_init a0 offset:1 gds
+; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-LABEL: gws_init_agpr_offset_add1:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-NEXT: ;;#ASMSTART
+; GISEL-NEXT: ; def a1
+; GISEL-NEXT: ;;#ASMEND
+; GISEL-NEXT: v_accvgpr_read_b32 v0, a1
+; GISEL-NEXT: v_add_u32_e32 v0, 1, v0
+; GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-NEXT: ;;#ASMSTART
+; GISEL-NEXT: ; def a0
+; GISEL-NEXT: ;;#ASMEND
+; GISEL-NEXT: s_lshl_b32 m0, s4, 16
+; GISEL-NEXT: s_nop 0
+; GISEL-NEXT: ds_gws_init a0 gds
+; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call i32 asm "; def $0", "=a"()
%offset.base = call i32 asm "; def $0", "=a"()
%offset = add i32 %offset.base, 1
@@ -100,20 +118,37 @@ define void @gws_init_agpr_offset_add1() #0 {
}
define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
-; CHECK-LABEL: gws_init_vgpr_offset_add:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_load_dword s0, s[8:9], 0x0
-; CHECK-NEXT: ;;#ASMSTART
-; CHECK-NEXT: ; def a0
-; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
-; CHECK-NEXT: v_readfirstlane_b32 s1, v0
-; CHECK-NEXT: s_lshl_b32 m0, s1, 16
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-NEXT: ds_gws_init v0 offset:3 gds
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_endpgm
+; SDAG-LABEL: gws_init_vgpr_offset_add:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_load_dword s0, s[8:9], 0x0
+; SDAG-NEXT: ;;#ASMSTART
+; SDAG-NEXT: ; def a0
+; SDAG-NEXT: ;;#ASMEND
+; SDAG-NEXT: v_accvgpr_read_b32 v0, a0
+; SDAG-NEXT: v_readfirstlane_b32 s1, v0
+; SDAG-NEXT: s_lshl_b32 m0, s1, 16
+; SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-NEXT: v_mov_b32_e32 v0, s0
+; SDAG-NEXT: ds_gws_init v0 offset:3 gds
+; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: gws_init_vgpr_offset_add:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_load_dword s0, s[8:9], 0x0
+; GISEL-NEXT: ;;#ASMSTART
+; GISEL-NEXT: ; def a0
+; GISEL-NEXT: ;;#ASMEND
+; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
+; GISEL-NEXT: v_add_u32_e32 v0, 3, v0
+; GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-NEXT: s_lshl_b32 m0, s1, 16
+; GISEL-NEXT: s_nop 0
+; GISEL-NEXT: ds_gws_init v0 gds
+; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-NEXT: s_endpgm
%agpr.offset.base = call i32 asm "; def $0", "=a"()
%agpr.offset = add i32 %agpr.offset.base, 3
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %agpr.offset)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
index 36fd9b2d6e0c4..288de47ddbe9a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
@@ -6,11 +6,11 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefix=GFX1012-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefix=GFX1012-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-ISEL %s
;;==============================================================================
;; A few basic test cases
@@ -6286,16 +6286,16 @@ define <4 x float> @global_addr_64bit_lsr_iv(ptr addrspace(1) %arg) {
; GFX906-ISEL: ; %bb.0: ; %bb
; GFX906-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX906-ISEL-NEXT: .LBB60_1: ; %bb3
; GFX906-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX906-ISEL-NEXT: v_add_u32_e32 v2, 1, v2
-; GFX906-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
-; GFX906-ISEL-NEXT: s_cbranch_vccz .LBB60_1
+; GFX906-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX906-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX906-ISEL-NEXT: s_cbranch_scc0 .LBB60_1
; GFX906-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX906-ISEL-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
+; GFX906-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX906-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s5
; GFX906-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX906-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX906-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
@@ -6306,16 +6306,18 @@ define <4 x float> @global_addr_64bit_lsr_iv(ptr addrspace(1) %arg) {
; GFX942-ISEL: ; %bb.0: ; %bb
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-ISEL-NEXT: s_mov_b32 s0, -1
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX942-ISEL-NEXT: .LBB60_1: ; %bb3
; GFX942-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX942-ISEL-NEXT: v_add_u32_e32 v2, 1, v2
-; GFX942-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
-; GFX942-ISEL-NEXT: s_cbranch_vccz .LBB60_1
+; GFX942-ISEL-NEXT: s_add_i32 s0, s0, 1
+; GFX942-ISEL-NEXT: s_cmpk_eq_i32 s0, 0xff
+; GFX942-ISEL-NEXT: s_cbranch_scc0 .LBB60_1
; GFX942-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]
+; GFX942-ISEL-NEXT: s_mov_b32 s1, 0
+; GFX942-ISEL-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX942-ISEL-NEXT: s_nop 1
+; GFX942-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX942-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX942-ISEL-NEXT: s_setpc_b64 s[30:31]
@@ -6324,15 +6326,16 @@ define <4 x float> @global_addr_64bit_lsr_iv(ptr addrspace(1) %arg) {
; GFX1012-ISEL: ; %bb.0: ; %bb
; GFX1012-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1012-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX1012-ISEL-NEXT: .LBB60_1: ; %bb3
; GFX1012-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1012-ISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
-; GFX1012-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v2
-; GFX1012-ISEL-NEXT: s_cbranch_vccz .LBB60_1
+; GFX1012-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX1012-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX1012-ISEL-NEXT: s_cbranch_scc0 .LBB60_1
; GFX1012-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX1012-ISEL-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
+; GFX1012-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX1012-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s5
; GFX1012-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX1012-ISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX1012-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
@@ -6343,20 +6346,19 @@ define <4 x float> @global_addr_64bit_lsr_iv(ptr addrspace(1) %arg) {
; GFX1100-ISEL: ; %bb.0: ; %bb
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: s_mov_b32 s0, -1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1100-ISEL-NEXT: .LBB60_1: ; %bb3
; GFX1100-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
-; GFX1100-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v2
-; GFX1100-ISEL-NEXT: s_cbranch_vccz .LBB60_1
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_add_i32 s0, s0, 1
+; GFX1100-ISEL-NEXT: s_cmpk_eq_i32 s0, 0xff
+; GFX1100-ISEL-NEXT: s_cbranch_scc0 .LBB60_1
; GFX1100-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX1100-ISEL-NEXT: s_mov_b32 s1, 0
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
; GFX1100-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX1100-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0)
@@ -6367,18 +6369,20 @@ define <4 x float> @global_addr_64bit_lsr_iv(ptr addrspace(1) %arg) {
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-ISEL-NEXT: s_mov_b32 s0, -1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-ISEL-NEXT: .LBB60_1: ; %bb3
; GFX1250-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
-; GFX1250-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v2
-; GFX1250-ISEL-NEXT: s_cbranch_vccz .LBB60_1
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_add_co_i32 s0, s0, 1
+; GFX1250-ISEL-NEXT: s_cmp_eq_u32 s0, 0xff
+; GFX1250-ISEL-NEXT: s_cbranch_scc0 .LBB60_1
; GFX1250-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]
+; GFX1250-ISEL-NEXT: s_mov_b32 s1, 0
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1250-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
@@ -6500,16 +6504,16 @@ define <4 x float> @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) %arg, pt
; GFX906-ISEL: ; %bb.0: ; %bb
; GFX906-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX906-ISEL-NEXT: .LBB61_1: ; %bb5
; GFX906-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX906-ISEL-NEXT: v_add_u32_e32 v2, 1, v2
-; GFX906-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
-; GFX906-ISEL-NEXT: s_cbranch_vccz .LBB61_1
+; GFX906-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX906-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX906-ISEL-NEXT: s_cbranch_scc0 .LBB61_1
; GFX906-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX906-ISEL-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
+; GFX906-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX906-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s5
; GFX906-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX906-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX906-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
@@ -6520,16 +6524,18 @@ define <4 x float> @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) %arg, pt
; GFX942-ISEL: ; %bb.0: ; %bb
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-ISEL-NEXT: s_mov_b32 s0, -1
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX942-ISEL-NEXT: .LBB61_1: ; %bb5
; GFX942-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX942-ISEL-NEXT: v_add_u32_e32 v2, 1, v2
-; GFX942-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
-; GFX942-ISEL-NEXT: s_cbranch_vccz .LBB61_1
+; GFX942-ISEL-NEXT: s_add_i32 s0, s0, 1
+; GFX942-ISEL-NEXT: s_cmpk_eq_i32 s0, 0xff
+; GFX942-ISEL-NEXT: s_cbranch_scc0 .LBB61_1
; GFX942-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]
+; GFX942-ISEL-NEXT: s_mov_b32 s1, 0
+; GFX942-ISEL-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX942-ISEL-NEXT: s_nop 1
+; GFX942-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX942-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX942-ISEL-NEXT: s_setpc_b64 s[30:31]
@@ -6538,15 +6544,16 @@ define <4 x float> @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) %arg, pt
; GFX1012-ISEL: ; %bb.0: ; %bb
; GFX1012-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1012-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX1012-ISEL-NEXT: .LBB61_1: ; %bb5
; GFX1012-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1012-ISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
-; GFX1012-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v2
-; GFX1012-ISEL-NEXT: s_cbranch_vccz .LBB61_1
+; GFX1012-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX1012-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX1012-ISEL-NEXT: s_cbranch_scc0 .LBB61_1
; GFX1012-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX1012-ISEL-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
+; GFX1012-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX1012-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s5
; GFX1012-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX1012-ISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX1012-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off glc
@@ -6557,20 +6564,19 @@ define <4 x float> @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) %arg, pt
; GFX1100-ISEL: ; %bb.0: ; %bb
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: s_mov_b32 s0, -1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1100-ISEL-NEXT: .LBB61_1: ; %bb5
; GFX1100-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
-; GFX1100-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v2
-; GFX1100-ISEL-NEXT: s_cbranch_vccz .LBB61_1
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_add_i32 s0, s0, 1
+; GFX1100-ISEL-NEXT: s_cmpk_eq_i32 s0, 0xff
+; GFX1100-ISEL-NEXT: s_cbranch_scc0 .LBB61_1
; GFX1100-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX1100-ISEL-NEXT: s_mov_b32 s1, 0
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
; GFX1100-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX1100-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off glc
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0)
@@ -6581,18 +6587,20 @@ define <4 x float> @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) %arg, pt
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-ISEL-NEXT: s_mov_b32 s0, -1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-ISEL-NEXT: .LBB61_1: ; %bb5
; GFX1250-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
-; GFX1250-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v2
-; GFX1250-ISEL-NEXT: s_cbranch_vccz .LBB61_1
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_add_co_i32 s0, s0, 1
+; GFX1250-ISEL-NEXT: s_cmp_eq_u32 s0, 0xff
+; GFX1250-ISEL-NEXT: s_cbranch_scc0 .LBB61_1
; GFX1250-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]
+; GFX1250-ISEL-NEXT: s_mov_b32 s1, 0
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1250-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
@@ -10522,9 +10530,7 @@ define <4 x float> @global_load_saddr_i8_zext_uniform_offset(ptr addrspace(1) in
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-ISEL-NEXT: s_add_co_u32 s0, s0, s2
-; GFX1250-ISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1] scope:SCOPE_DEV
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
@@ -10614,9 +10620,7 @@ define <4 x float> @global_load_saddr_i8_zext_uniform_offset_immoffset(ptr addrs
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-ISEL-NEXT: s_add_co_u32 s0, s0, s2
-; GFX1250-ISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-24 scope:SCOPE_SYS
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
@@ -10707,9 +10711,7 @@ define <4 x float> @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr addr
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-ISEL-NEXT: s_add_co_u32 s0, s0, s2
-; GFX1250-ISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1]
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
@@ -10801,9 +10803,7 @@ define <4 x float> @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offs
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-ISEL-NEXT: s_add_co_u32 s0, s0, s2
-; GFX1250-ISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:128
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
@@ -12002,21 +12002,18 @@ define <4 x float> @global_saddr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX906-ISEL: ; %bb.0: ; %bb
; GFX906-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, 0xff
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX906-ISEL-NEXT: .LBB114_1: ; %bb3
; GFX906-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX906-ISEL-NEXT: v_add_u32_e32 v0, 1, v0
-; GFX906-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX906-ISEL-NEXT: s_cbranch_vccz .LBB114_1
+; GFX906-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX906-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX906-ISEL-NEXT: s_cbranch_scc0 .LBB114_1
; GFX906-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX906-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s16
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s17
-; GFX906-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0
-; GFX906-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
-; GFX906-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off glc
+; GFX906-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX906-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX906-ISEL-NEXT: s_add_u32 s4, s16, s4
+; GFX906-ISEL-NEXT: s_addc_u32 s5, s17, s5
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX906-ISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[4:5] glc
; GFX906-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX906-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12024,17 +12021,18 @@ define <4 x float> @global_saddr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX942-ISEL: ; %bb.0: ; %bb
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-ISEL-NEXT: s_mov_b32 s2, -1
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v1, 0xff
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX942-ISEL-NEXT: .LBB114_1: ; %bb3
; GFX942-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX942-ISEL-NEXT: v_add_u32_e32 v0, 1, v0
-; GFX942-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX942-ISEL-NEXT: s_cbranch_vccz .LBB114_1
+; GFX942-ISEL-NEXT: s_add_i32 s2, s2, 1
+; GFX942-ISEL-NEXT: s_cmpk_eq_i32 s2, 0xff
+; GFX942-ISEL-NEXT: s_cbranch_scc0 .LBB114_1
; GFX942-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1]
-; GFX942-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1
+; GFX942-ISEL-NEXT: s_mov_b32 s3, 0
+; GFX942-ISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 2
+; GFX942-ISEL-NEXT: s_add_u32 s0, s0, s2
+; GFX942-ISEL-NEXT: s_addc_u32 s1, s1, s3
+; GFX942-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-ISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 sc1
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX942-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12042,20 +12040,18 @@ define <4 x float> @global_saddr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX1012-ISEL: ; %bb.0: ; %bb
; GFX1012-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1012-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX1012-ISEL-NEXT: .LBB114_1: ; %bb3
; GFX1012-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1012-ISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; GFX1012-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v0
-; GFX1012-ISEL-NEXT: s_cbranch_vccz .LBB114_1
+; GFX1012-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX1012-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX1012-ISEL-NEXT: s_cbranch_scc0 .LBB114_1
; GFX1012-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s16
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s17
-; GFX1012-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX1012-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
-; GFX1012-ISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
-; GFX1012-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off glc dlc
+; GFX1012-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1012-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX1012-ISEL-NEXT: s_add_u32 s4, s16, s4
+; GFX1012-ISEL-NEXT: s_addc_u32 s5, s17, s5
+; GFX1012-ISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[4:5] glc dlc
; GFX1012-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX1012-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12063,23 +12059,20 @@ define <4 x float> @global_saddr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX1100-ISEL: ; %bb.0: ; %bb
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: s_mov_b32 s2, -1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1100-ISEL-NEXT: .LBB114_1: ; %bb3
; GFX1100-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; GFX1100-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v0
-; GFX1100-ISEL-NEXT: s_cbranch_vccz .LBB114_1
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_add_i32 s2, s2, 1
+; GFX1100-ISEL-NEXT: s_cmpk_eq_i32 s2, 0xff
+; GFX1100-ISEL-NEXT: s_cbranch_scc0 .LBB114_1
; GFX1100-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX1100-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v3, v1, vcc_lo
-; GFX1100-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off glc
+; GFX1100-ISEL-NEXT: s_mov_b32 s3, 0
+; GFX1100-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1100-ISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 2
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_add_u32 s0, s0, s2
+; GFX1100-ISEL-NEXT: s_addc_u32 s1, s1, s3
+; GFX1100-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1] glc
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX1100-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12088,19 +12081,20 @@ define <4 x float> @global_saddr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-ISEL-NEXT: s_mov_b32 s2, -1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-ISEL-NEXT: .LBB114_1: ; %bb3
; GFX1250-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; GFX1250-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v0
-; GFX1250-ISEL-NEXT: s_cbranch_vccz .LBB114_1
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_add_co_i32 s2, s2, 1
+; GFX1250-ISEL-NEXT: s_cmp_eq_u32 s2, 0xff
+; GFX1250-ISEL-NEXT: s_cbranch_scc0 .LBB114_1
; GFX1250-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1]
-; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off scope:SCOPE_SYS
+; GFX1250-ISEL-NEXT: s_mov_b32 s3, 0
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-ISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 2
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_add_co_u32 s0, s0, s2
+; GFX1250-ISEL-NEXT: s_add_co_ci_u32 s1, s1, s3
+; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1] scope:SCOPE_SYS
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
bb:
@@ -12227,21 +12221,18 @@ define <4 x float> @global_saddr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg %
; GFX906-ISEL: ; %bb.0: ; %bb
; GFX906-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, 0xff
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX906-ISEL-NEXT: .LBB115_1: ; %bb5
; GFX906-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX906-ISEL-NEXT: v_add_u32_e32 v0, 1, v0
-; GFX906-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX906-ISEL-NEXT: s_cbranch_vccz .LBB115_1
+; GFX906-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX906-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX906-ISEL-NEXT: s_cbranch_scc0 .LBB115_1
; GFX906-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX906-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s16
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s17
-; GFX906-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0
-; GFX906-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
-; GFX906-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX906-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX906-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX906-ISEL-NEXT: s_add_u32 s4, s16, s4
+; GFX906-ISEL-NEXT: s_addc_u32 s5, s17, s5
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX906-ISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[4:5]
; GFX906-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX906-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12249,17 +12240,18 @@ define <4 x float> @global_saddr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg %
; GFX942-ISEL: ; %bb.0: ; %bb
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-ISEL-NEXT: s_mov_b32 s2, -1
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v1, 0xff
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX942-ISEL-NEXT: .LBB115_1: ; %bb5
; GFX942-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX942-ISEL-NEXT: v_add_u32_e32 v0, 1, v0
-; GFX942-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX942-ISEL-NEXT: s_cbranch_vccz .LBB115_1
+; GFX942-ISEL-NEXT: s_add_i32 s2, s2, 1
+; GFX942-ISEL-NEXT: s_cmpk_eq_i32 s2, 0xff
+; GFX942-ISEL-NEXT: s_cbranch_scc0 .LBB115_1
; GFX942-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX942-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1]
-; GFX942-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX942-ISEL-NEXT: s_mov_b32 s3, 0
+; GFX942-ISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 2
+; GFX942-ISEL-NEXT: s_add_u32 s0, s0, s2
+; GFX942-ISEL-NEXT: s_addc_u32 s1, s1, s3
+; GFX942-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-ISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX942-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX942-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12267,20 +12259,18 @@ define <4 x float> @global_saddr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg %
; GFX1012-ISEL: ; %bb.0: ; %bb
; GFX1012-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1012-ISEL-NEXT: s_mov_b32 s4, -1
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX1012-ISEL-NEXT: .LBB115_1: ; %bb5
; GFX1012-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1012-ISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; GFX1012-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v0
-; GFX1012-ISEL-NEXT: s_cbranch_vccz .LBB115_1
+; GFX1012-ISEL-NEXT: s_add_i32 s4, s4, 1
+; GFX1012-ISEL-NEXT: s_cmpk_eq_i32 s4, 0xff
+; GFX1012-ISEL-NEXT: s_cbranch_scc0 .LBB115_1
; GFX1012-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s16
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s17
-; GFX1012-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX1012-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
-; GFX1012-ISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
-; GFX1012-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX1012-ISEL-NEXT: s_mov_b32 s5, 0
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1012-ISEL-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
+; GFX1012-ISEL-NEXT: s_add_u32 s4, s16, s4
+; GFX1012-ISEL-NEXT: s_addc_u32 s5, s17, s5
+; GFX1012-ISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[4:5]
; GFX1012-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX1012-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12288,23 +12278,20 @@ define <4 x float> @global_saddr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg %
; GFX1100-ISEL: ; %bb.0: ; %bb
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: s_mov_b32 s2, -1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1100-ISEL-NEXT: .LBB115_1: ; %bb5
; GFX1100-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; GFX1100-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v0
-; GFX1100-ISEL-NEXT: s_cbranch_vccz .LBB115_1
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_add_i32 s2, s2, 1
+; GFX1100-ISEL-NEXT: s_cmpk_eq_i32 s2, 0xff
+; GFX1100-ISEL-NEXT: s_cbranch_scc0 .LBB115_1
; GFX1100-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX1100-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v3, v1, vcc_lo
-; GFX1100-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off
+; GFX1100-ISEL-NEXT: s_mov_b32 s3, 0
+; GFX1100-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1100-ISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 2
+; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-ISEL-NEXT: s_add_u32 s0, s0, s2
+; GFX1100-ISEL-NEXT: s_addc_u32 s1, s1, s3
+; GFX1100-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1]
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX1100-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12313,19 +12300,20 @@ define <4 x float> @global_saddr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg %
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-ISEL-NEXT: s_mov_b32 s2, -1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-ISEL-NEXT: .LBB115_1: ; %bb5
; GFX1250-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; GFX1250-ISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0xff, v0
-; GFX1250-ISEL-NEXT: s_cbranch_vccz .LBB115_1
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_add_co_i32 s2, s2, 1
+; GFX1250-ISEL-NEXT: s_cmp_eq_u32 s2, 0xff
+; GFX1250-ISEL-NEXT: s_cbranch_scc0 .LBB115_1
; GFX1250-ISEL-NEXT: ; %bb.2: ; %bb2
-; GFX1250-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1]
-; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v[0:1], off
+; GFX1250-ISEL-NEXT: s_mov_b32 s3, 0
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-ISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 2
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-ISEL-NEXT: s_add_co_u32 s0, s0, s2
+; GFX1250-ISEL-NEXT: s_add_co_ci_u32 s1, s1, s3
+; GFX1250-ISEL-NEXT: global_load_b128 v[0:3], v0, s[0:1]
; GFX1250-ISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
index a1de9877cf51a..79251044b8033 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
@@ -6,11 +6,11 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefix=GFX1012-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100-ISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefix=GFX1012-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100-ISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-ISEL %s
;;==============================================================================
;; A few basic test cases
@@ -1257,97 +1257,85 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset,
;
; GFX906-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX906-ISEL: ; %bb.0:
-; GFX906-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
-; GFX906-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX906-ISEL-NEXT: ds_read_b64 v[0:1], v0
-; GFX906-ISEL-NEXT: s_mov_b32 s7, 0
+; GFX906-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX906-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX906-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s6
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s7
-; GFX906-ISEL-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2
-; GFX906-ISEL-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc
+; GFX906-ISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX906-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s3
-; GFX906-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX906-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
; GFX906-ISEL-NEXT: s_endpgm
;
; GFX942-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX942-ISEL: ; %bb.0:
-; GFX942-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
-; GFX942-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX942-ISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX942-ISEL-NEXT: ds_read_b64 v[0:1], v0
-; GFX942-ISEL-NEXT: s_mov_b32 s7, 0
+; GFX942-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX942-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX942-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
-; GFX942-ISEL-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2
-; GFX942-ISEL-NEXT: s_nop 1
-; GFX942-ISEL-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc
+; GFX942-ISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX942-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX942-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
-; GFX942-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX942-ISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX942-ISEL-NEXT: s_nop 1
+; GFX942-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
; GFX942-ISEL-NEXT: s_endpgm
;
; GFX1012-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX1012-ISEL: ; %bb.0:
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1012-ISEL-NEXT: s_clause 0x1
-; GFX1012-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX1012-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX1012-ISEL-NEXT: s_mov_b32 s7, 0
-; GFX1012-ISEL-NEXT: ds_read_b64 v[0:1], v0
+; GFX1012-ISEL-NEXT: ds_read_b64 v[4:5], v0
+; GFX1012-ISEL-NEXT: s_load_dword s4, s[4:5], 0x24
; GFX1012-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s6
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s7
-; GFX1012-ISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
-; GFX1012-ISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s3
-; GFX1012-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX1012-ISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1012-ISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1012-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX1012-ISEL-NEXT: s_endpgm
;
; GFX1100-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX1100-ISEL: ; %bb.0:
-; GFX1100-ISEL-NEXT: s_clause 0x1
-; GFX1100-ISEL-NEXT: s_load_b32 s6, s[4:5], 0x24
; GFX1100-ISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-ISEL-NEXT: s_mov_b32 s7, 0
; GFX1100-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1100-ISEL-NEXT: s_load_b32 s4, s[4:5], 0x24
+; GFX1100-ISEL-NEXT: ds_load_b64 v[4:5], v0
; GFX1100-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX1100-ISEL-NEXT: ds_load_b64 v[0:1], v0
-; GFX1100-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-ISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo
; GFX1100-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX1100-ISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX1100-ISEL-NEXT: global_store_b128 v[4:5], v[0:3], off
+; GFX1100-ISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1100-ISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1100-ISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1100-ISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-ISEL-NEXT: s_endpgm
;
; GFX1250-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-ISEL-NEXT: s_clause 0x1
-; GFX1250-ISEL-NEXT: s_load_b32 s6, s[4:5], 0x24 nv
; GFX1250-ISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX1250-ISEL-NEXT: s_wait_xcnt 0x0
+; GFX1250-ISEL-NEXT: s_load_b32 s4, s[4:5], 0x24 nv
; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-ISEL-NEXT: s_mov_b32 s7, 0
-; GFX1250-ISEL-NEXT: ds_load_b64 v[0:1], v0
+; GFX1250-ISEL-NEXT: ds_load_b64 v[4:5], v0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
-; GFX1250-ISEL-NEXT: s_wait_dscnt 0x0
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
-; GFX1250-ISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo
; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
-; GFX1250-ISEL-NEXT: global_store_b128 v[4:5], v[0:3], off
+; GFX1250-ISEL-NEXT: s_wait_dscnt 0x0
+; GFX1250-ISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-ISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1250-ISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1250-ISEL-NEXT: s_endpgm
%sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
@@ -1445,97 +1433,85 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32
;
; GFX906-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX906-ISEL: ; %bb.0:
-; GFX906-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
-; GFX906-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX906-ISEL-NEXT: ds_read_b64 v[0:1], v0
-; GFX906-ISEL-NEXT: s_mov_b32 s7, 0
+; GFX906-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX906-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX906-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s6
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s7
-; GFX906-ISEL-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2
-; GFX906-ISEL-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc
+; GFX906-ISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX906-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s3
-; GFX906-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off offset:-120
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX906-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5] offset:-120
; GFX906-ISEL-NEXT: s_endpgm
;
; GFX942-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX942-ISEL: ; %bb.0:
-; GFX942-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
-; GFX942-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX942-ISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX942-ISEL-NEXT: ds_read_b64 v[0:1], v0
-; GFX942-ISEL-NEXT: s_mov_b32 s7, 0
+; GFX942-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX942-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX942-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
-; GFX942-ISEL-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2
-; GFX942-ISEL-NEXT: s_nop 1
-; GFX942-ISEL-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc
+; GFX942-ISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX942-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX942-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
-; GFX942-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off offset:-120 sc0
+; GFX942-ISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX942-ISEL-NEXT: s_nop 1
+; GFX942-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5] offset:-120 sc0
; GFX942-ISEL-NEXT: s_endpgm
;
; GFX1012-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX1012-ISEL: ; %bb.0:
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1012-ISEL-NEXT: s_clause 0x1
-; GFX1012-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX1012-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX1012-ISEL-NEXT: s_mov_b32 s7, 0
-; GFX1012-ISEL-NEXT: ds_read_b64 v[0:1], v0
+; GFX1012-ISEL-NEXT: ds_read_b64 v[4:5], v0
+; GFX1012-ISEL-NEXT: s_load_dword s4, s[4:5], 0x24
; GFX1012-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s6
-; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s7
-; GFX1012-ISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
-; GFX1012-ISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX1012-ISEL-NEXT: v_mov_b32_e32 v3, s3
-; GFX1012-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off offset:-120
+; GFX1012-ISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1012-ISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1012-ISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1012-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:-120
; GFX1012-ISEL-NEXT: s_endpgm
;
; GFX1100-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX1100-ISEL: ; %bb.0:
-; GFX1100-ISEL-NEXT: s_clause 0x1
-; GFX1100-ISEL-NEXT: s_load_b32 s6, s[4:5], 0x24
; GFX1100-ISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-ISEL-NEXT: s_mov_b32 s7, 0
; GFX1100-ISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1100-ISEL-NEXT: s_load_b32 s4, s[4:5], 0x24
+; GFX1100-ISEL-NEXT: ds_load_b64 v[4:5], v0
; GFX1100-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX1100-ISEL-NEXT: ds_load_b64 v[0:1], v0
-; GFX1100-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-ISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
-; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo
; GFX1100-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX1100-ISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX1100-ISEL-NEXT: global_store_b128 v[4:5], v[0:3], off offset:-120
+; GFX1100-ISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1100-ISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1100-ISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1100-ISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1] offset:-120
; GFX1100-ISEL-NEXT: s_endpgm
;
; GFX1250-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-ISEL-NEXT: s_clause 0x1
-; GFX1250-ISEL-NEXT: s_load_b32 s6, s[4:5], 0x24 nv
; GFX1250-ISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX1250-ISEL-NEXT: s_wait_xcnt 0x0
+; GFX1250-ISEL-NEXT: s_load_b32 s4, s[4:5], 0x24 nv
; GFX1250-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-ISEL-NEXT: s_mov_b32 s7, 0
-; GFX1250-ISEL-NEXT: ds_load_b64 v[0:1], v0
+; GFX1250-ISEL-NEXT: ds_load_b64 v[4:5], v0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
-; GFX1250-ISEL-NEXT: s_wait_dscnt 0x0
-; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-ISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
-; GFX1250-ISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo
; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
-; GFX1250-ISEL-NEXT: global_store_b128 v[4:5], v[0:3], off offset:-120
+; GFX1250-ISEL-NEXT: s_wait_dscnt 0x0
+; GFX1250-ISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-ISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1250-ISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1250-ISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1] offset:-120
; GFX1250-ISEL-NEXT: s_endpgm
%sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
index 91e4c0f1d7f7a..329fd5a4df87b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -66,16 +66,19 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42b17218
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
@@ -124,12 +127,15 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x42b17218
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
@@ -164,29 +170,32 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
;
; SI-GISEL-LABEL: s_exp_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
-; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s6, v0, -v2
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
-; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s6, v1, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3
; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42b17218
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -402,40 +411,47 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v4, s4, v1
-; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s4
; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, s3, v5
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x39a3b295, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3fb8a000, v5
; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v5
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v0
; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v5, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -484,36 +500,43 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0
; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3
; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v5
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v5, v0
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v5, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
@@ -564,36 +587,43 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
; SI-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2
; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0
; SI-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3
; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
-; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5
; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
-; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v5
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v5, v0
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s6
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -925,71 +955,82 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-LABEL: s_exp_v3f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x39a3b295
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x39a3b295
; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s3, s0, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v2
-; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, s1, v5
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3fb8a000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, s3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s3
+; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s1, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x39a3b295, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v5, v4
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v4
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s3
+; VI-GISEL-NEXT: s_and_b32 s3, s2, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4
-; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000
-; VI-GISEL-NEXT: v_ldexp_f32 v5, v5, v6
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x39a3b295, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
-; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v6
-; VI-GISEL-NEXT: v_exp_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v2, v6, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
@@ -1051,51 +1092,62 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s1, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v5
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v5
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v0
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v2, v3
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v5, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v2, v1
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v3
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v3
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
; GFX900-GISEL-NEXT: s_endpgm
@@ -1158,56 +1210,68 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-LABEL: s_exp_v3f32:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, s1, v1
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v5
-; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v5
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v1
-; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v0
-; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; SI-GISEL-NEXT: v_fma_f32 v3, s0, v2, v3
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v6
-; SI-GISEL-NEXT: v_fma_f32 v1, s2, v2, v1
-; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v3
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
-; SI-GISEL-NEXT: v_exp_f32_e32 v6, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; SI-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v3
+; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
+; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v6, v2
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; SI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s3
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; SI-GISEL-NEXT: s_waitcnt expcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8
; SI-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_exp_v3f32:
@@ -1679,90 +1743,105 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-LABEL: s_exp_v4f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8a000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x39a3b295
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b17218
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x39a3b295
; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0
-; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s6
+; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s1, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x39a3b295, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v5, v4
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s6
+; VI-GISEL-NEXT: s_and_b32 s6, s2, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x39a3b295, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v5, v4
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; VI-GISEL-NEXT: s_and_b32 s6, s3, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff000
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, s1, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v7, v1
-; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5
-; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v6
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, s0, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v9
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, s0, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v9, v6
-; VI-GISEL-NEXT: v_rndne_f32_e32 v9, v8
-; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v9
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v8, v6
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; VI-GISEL-NEXT: v_exp_f32_e32 v6, v6
-; VI-GISEL-NEXT: s_and_b32 s0, s3, 0xfffff000
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s0, v3
-; VI-GISEL-NEXT: v_ldexp_f32 v6, v6, v8
-; VI-GISEL-NEXT: v_mov_b32_e32 v8, s0
-; VI-GISEL-NEXT: v_sub_f32_e32 v8, s3, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3fb8a000, v8
-; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
-; VI-GISEL-NEXT: v_rndne_f32_e32 v8, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v8
-; VI-GISEL-NEXT: v_exp_f32_e32 v8, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v3, v8, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s6
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
@@ -1837,64 +1916,79 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8aa3b
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b17218
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v0
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v3, v1
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s1, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v1
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v3, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v6
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v9, v6
-; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v3, v8
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9
-; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s2, v0, -v3
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s2, v1, v5
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v6, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, s3, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v8
-; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v3, v2
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v8
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v8, v2
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, v2
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v8, v3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX900-GISEL-NEXT: s_endpgm
@@ -1970,66 +2064,81 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-LABEL: s_exp_v4f32:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8aa3b
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b17218
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v2
-; SI-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v0
-; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; SI-GISEL-NEXT: v_fma_f32 v1, s0, v3, v1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, s1, v2
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v1
-; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v1
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v3, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2
-; SI-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v6
-; SI-GISEL-NEXT: v_rndne_f32_e32 v9, v6
-; SI-GISEL-NEXT: v_fma_f32 v8, s2, v3, v8
-; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9
-; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; SI-GISEL-NEXT: v_exp_f32_e32 v6, v6
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; SI-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s8
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; SI-GISEL-NEXT: v_fma_f32 v5, s2, v0, -v3
+; SI-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; SI-GISEL-NEXT: v_fma_f32 v5, s2, v1, v5
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v6, v8
-; SI-GISEL-NEXT: v_mul_f32_e32 v8, s3, v2
-; SI-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v8
-; SI-GISEL-NEXT: v_fma_f32 v2, s3, v3, v2
-; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v8
-; SI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3
-; SI-GISEL-NEXT: v_add_f32_e32 v2, v8, v2
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
-; SI-GISEL-NEXT: v_exp_f32_e32 v8, v2
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s8
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v8, v3
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s8
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s8
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-GISEL-NEXT: s_endpgm
@@ -6504,23 +6613,42 @@ define <3 x half> @v_exp_v3f16(<3 x half> %in) {
; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp_v3f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX900-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2
-; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
-; GFX900-NEXT: v_exp_f32_e32 v2, v2
-; GFX900-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
-; GFX900-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_exp_v3f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp_v3f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp_v3f16:
; SI-SDAG: ; %bb.0:
@@ -6621,11 +6749,12 @@ define <3 x half> @v_exp_v3f16_afn(<3 x half> %in) {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc5
; GFX900-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v0
; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v1
; GFX900-GISEL-NEXT: v_exp_f16_e32 v3, v3
; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v1
; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v3
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp_v3f16_afn:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
index 34799aed60793..476d8d17a096c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -68,16 +68,19 @@ define amdgpu_kernel void @s_exp10_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x421a209b
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
@@ -126,12 +129,15 @@ define amdgpu_kernel void @s_exp10_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x421a209b
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
@@ -166,29 +172,32 @@ define amdgpu_kernel void @s_exp10_f32(ptr addrspace(1) %out, float %in) {
;
; SI-GISEL-LABEL: s_exp10_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
-; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s6, v0, -v2
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
-; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s6, v1, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3
; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x421a209b
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -404,40 +413,47 @@ define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v4, s4, v1
-; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s4
; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, s3, v5
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3a2784bc, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x40549000, v5
; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v5
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v0
; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v5, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -486,36 +502,43 @@ define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0
; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3
; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v5
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v5, v0
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v5, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
@@ -566,36 +589,43 @@ define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
; SI-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2
; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0
; SI-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3
; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
-; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5
; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
-; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v5
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v5, v0
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s6
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -927,71 +957,82 @@ define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-LABEL: s_exp10_v3f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3a2784bc
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3a2784bc
; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s3, s0, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v2
-; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, s1, v5
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x40549000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, s3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s3
+; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s1, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3a2784bc, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v5, v4
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v4
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s3
+; VI-GISEL-NEXT: s_and_b32 s3, s2, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4
-; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000
-; VI-GISEL-NEXT: v_ldexp_f32 v5, v5, v6
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x40549000, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
-; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v6
-; VI-GISEL-NEXT: v_exp_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v2, v6, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
@@ -1053,51 +1094,62 @@ define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s1, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v5
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v5
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v0
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v2, v3
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v5, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v2, v1
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v3
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v3
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
; GFX900-GISEL-NEXT: s_endpgm
@@ -1160,56 +1212,68 @@ define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-LABEL: s_exp10_v3f32:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, s1, v1
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v5
-; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v5
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v1
-; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v0
-; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; SI-GISEL-NEXT: v_fma_f32 v3, s0, v2, v3
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v6
-; SI-GISEL-NEXT: v_fma_f32 v1, s2, v2, v1
-; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v3
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
-; SI-GISEL-NEXT: v_exp_f32_e32 v6, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; SI-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v3
+; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
+; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v6, v2
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; SI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s3
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; SI-GISEL-NEXT: s_waitcnt expcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8
; SI-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_exp10_v3f32:
@@ -1681,90 +1745,105 @@ define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-LABEL: s_exp10_v4f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3a2784bc
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3a2784bc
; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0
-; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s6
+; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s1, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3a2784bc, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v5, v4
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s6
+; VI-GISEL-NEXT: s_and_b32 s6, s2, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3a2784bc, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v5, v4
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; VI-GISEL-NEXT: s_and_b32 s6, s3, 0xfffff000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: v_sub_f32_e32 v4, s3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff000
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, s1, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x40549000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v7, v1
-; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5
-; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v6
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x40549000, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, s0, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v9
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, s0, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v9, v6
-; VI-GISEL-NEXT: v_rndne_f32_e32 v9, v8
-; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v9
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v8, v6
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; VI-GISEL-NEXT: v_exp_f32_e32 v6, v6
-; VI-GISEL-NEXT: s_and_b32 s0, s3, 0xfffff000
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s0, v3
-; VI-GISEL-NEXT: v_ldexp_f32 v6, v6, v8
-; VI-GISEL-NEXT: v_mov_b32_e32 v8, s0
-; VI-GISEL-NEXT: v_sub_f32_e32 v8, s3, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x40549000, v8
-; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
-; VI-GISEL-NEXT: v_rndne_f32_e32 v8, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v8
-; VI-GISEL-NEXT: v_exp_f32_e32 v8, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v3, v8, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 0, s6
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s6
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
@@ -1839,64 +1918,79 @@ define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549a78
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v0
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v3, v1
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s1, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v1
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v3, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v6
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v9, v6
-; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v3, v8
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9
-; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s2, v0, -v3
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; GFX900-GISEL-NEXT: v_fma_f32 v5, s2, v1, v5
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v6, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, s3, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v8
-; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v3, v2
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v8
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v8, v2
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, v2
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v3
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v8, v3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX900-GISEL-NEXT: s_endpgm
@@ -1972,66 +2066,81 @@ define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-LABEL: s_exp10_v4f32:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549a78
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v2
-; SI-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v0
-; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
-; SI-GISEL-NEXT: v_fma_f32 v1, s0, v3, v1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v0
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v0, -v2
+; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
+; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, s1, v2
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v1
-; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v1
-; SI-GISEL-NEXT: v_fma_f32 v6, s1, v3, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2
-; SI-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v6
-; SI-GISEL-NEXT: v_rndne_f32_e32 v9, v6
-; SI-GISEL-NEXT: v_fma_f32 v8, s2, v3, v8
-; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9
-; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; SI-GISEL-NEXT: v_exp_f32_e32 v6, v6
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s1, v0
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v0, -v3
+; SI-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; SI-GISEL-NEXT: v_fma_f32 v5, s1, v1, v5
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x7f800000, s8
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v0
+; SI-GISEL-NEXT: v_fma_f32 v5, s2, v0, -v3
+; SI-GISEL-NEXT: v_rndne_f32_e32 v6, v3
+; SI-GISEL-NEXT: v_fma_f32 v5, s2, v1, v5
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v6, v8
-; SI-GISEL-NEXT: v_mul_f32_e32 v8, s3, v2
-; SI-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v8
-; SI-GISEL-NEXT: v_fma_f32 v2, s3, v3, v2
-; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v8
-; SI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3
-; SI-GISEL-NEXT: v_add_f32_e32 v2, v8, v2
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
-; SI-GISEL-NEXT: v_exp_f32_e32 v8, v2
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v5
+; SI-GISEL-NEXT: s_cselect_b32 s1, 0x7f800000, s8
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v3
+; SI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v0
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v3
+; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
+; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v3
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v8, v3
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s8
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v2
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0, s8
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s8
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-GISEL-NEXT: s_endpgm
@@ -6643,23 +6752,42 @@ define <3 x half> @v_exp10_v3f16(<3 x half> %in) {
; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp10_v3f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX900-NEXT: v_mul_f32_e32 v2, 0x40549a78, v2
-; GFX900-NEXT: v_mul_f32_e32 v0, 0x40549a78, v0
-; GFX900-NEXT: v_exp_f32_e32 v2, v2
-; GFX900-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x40549a78, v1
-; GFX900-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_exp10_v3f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549a78, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549a78, v0
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v1
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp10_v3f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549a78, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x40549a78, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp10_v3f16:
; SI-SDAG: ; %bb.0:
@@ -6793,18 +6921,19 @@ define <3 x half> @v_exp10_v3f16_afn(<3 x half> %in) {
; GFX900-GISEL-NEXT: v_mul_f16_e32 v5, 0x42a4, v0
; GFX900-GISEL-NEXT: v_mul_f16_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v4, 0x113c, v1
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x42a4, v1
; GFX900-GISEL-NEXT: v_exp_f16_e32 v3, v3
; GFX900-GISEL-NEXT: v_exp_f16_e32 v5, v5
; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v2
; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mul_f16_e32 v4, 0x113c, v1
-; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x42a4, v1
; GFX900-GISEL-NEXT: v_exp_f16_e32 v4, v4
; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v3, v5, v3
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v3, v0
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, v1, v4
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp10_v3f16_afn:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index 53b862e8bab2f..6ff5626854bc3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -32,19 +32,20 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; SI-GISEL-LABEL: s_exp2_f32:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
-; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-GISEL-NEXT: s_or_b64 s[0:1], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; SI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_not_b32_e32 v1, 63
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
; SI-GISEL-NEXT: s_mov_b32 s2, -1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, v0, s3
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -72,15 +73,15 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x42800000, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_not_b32_e32 v1, 63
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v2, v0, v1
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v0, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
@@ -108,17 +109,17 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, s2
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
@@ -201,22 +202,24 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
-; SI-GISEL-NEXT: v_not_b32_e32 v2, 63
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
-; SI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
-; SI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
-; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v3, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; SI-GISEL-NEXT: v_add_f32_e32 v0, s6, v0
+; SI-GISEL-NEXT: v_add_f32_e32 v1, s7, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, v0, s3
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v1, v1, s0
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-GISEL-NEXT: s_endpgm
@@ -250,22 +253,24 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
-; VI-GISEL-NEXT: v_not_b32_e32 v2, 63
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
-; VI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
-; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v3, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s7, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, s3
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -298,22 +303,24 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
-; GFX900-GISEL-NEXT: v_not_b32_e32 v2, 63
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
-; GFX900-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s11, v0
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v3, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s11, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, s0
; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX900-GISEL-NEXT: s_endpgm
;
@@ -417,32 +424,36 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; SI-GISEL-LABEL: s_exp2_v3f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
-; SI-GISEL-NEXT: v_not_b32_e32 v3, 63
+; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; SI-GISEL-NEXT: v_add_f32_e32 v4, s1, v4
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; SI-GISEL-NEXT: v_exp_f32_e32 v4, v4
-; SI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v2, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v4, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1]
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_add_f32_e32 v1, s8, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v0, s10, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v0
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, v1, s3
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v1, v2, s2
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v2, v3, s0
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
; SI-GISEL-NEXT: s_endpgm
@@ -483,32 +494,36 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; VI-GISEL-LABEL: s_exp2_v3f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
-; VI-GISEL-NEXT: v_not_b32_e32 v3, 63
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; VI-GISEL-NEXT: v_add_f32_e32 v4, s1, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; VI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
-; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
-; VI-GISEL-NEXT: v_exp_f32_e32 v2, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1]
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v4, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 0xffffffc0, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0x42800000, 0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s8, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s10, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v3, v0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v1, s5
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v2, s0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v3, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
;
@@ -546,32 +561,36 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; GFX900-GISEL-LABEL: s_exp2_v3f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX900-GISEL-NEXT: v_not_b32_e32 v3, 63
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_add_f32_e32 v4, s1, v4
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v4, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s8, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v1, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, s0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v3, s0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_exp2_v3f32:
@@ -705,36 +724,42 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
-; SI-GISEL-NEXT: v_not_b32_e32 v4, 63
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42800000, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
; SI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
-; SI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
-; SI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; SI-GISEL-NEXT: v_exp_f32_e32 v3, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1]
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v4
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; SI-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s11, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, v0, s3
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; SI-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v1, s11, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_exp_f32_e32 v4, v1
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v1, v2, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v2, v3, s3
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v3, v4, s0
; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -782,35 +807,41 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
-; VI-GISEL-NEXT: v_not_b32_e32 v4, 63
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 0xffffffc0, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0x42800000, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s11, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: s_cselect_b32 s1, 0xffffffc0, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s11, v1
; VI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
+; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, v1
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
-; VI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; VI-GISEL-NEXT: v_exp_f32_e32 v3, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-GISEL-NEXT: v_ldexp_f32 v3, v3, v4
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v2, s0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v3, s1
+; VI-GISEL-NEXT: v_ldexp_f32 v3, v4, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, s5
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
@@ -858,34 +889,40 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
-; GFX900-GISEL-NEXT: v_not_b32_e32 v4, 63
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s11, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s11, v1
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
-; GFX900-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v5, v2
-; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, s0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v3, s1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v4, s0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm
@@ -3413,6 +3450,7 @@ define <3 x half> @v_exp_v3f16(<3 x half> %in) {
; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp_v3f16:
@@ -3480,6 +3518,7 @@ define <3 x half> @v_exp2_v3f16_afn(<3 x half> %in) {
; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp2_v3f16_afn:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index cef8aa0c8dd38..867eee708a5e5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -45,30 +45,37 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
;
; SI-GISEL-LABEL: s_log_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s0, s[4:5], 0xb
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log_f32:
@@ -107,31 +114,41 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-LABEL: s_log_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -165,29 +182,36 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
;
; GFX900-GISEL-LABEL: s_log_f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v5
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x41b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log_f32:
@@ -221,28 +245,34 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_f32:
@@ -348,30 +378,37 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
;
; SI-GISEL-LABEL: s_log_contract_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s0, s[4:5], 0xb
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log_contract_f32:
@@ -410,31 +447,41 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
; VI-GISEL-LABEL: s_log_contract_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -468,29 +515,36 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
;
; GFX900-GISEL-LABEL: s_log_contract_f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v5
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x41b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log_contract_f32:
@@ -524,28 +578,34 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_contract_f32:
@@ -667,42 +727,57 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
;
; SI-GISEL-LABEL: s_log_v2f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
-; SI-GISEL-NEXT: v_fma_f32 v6, v1, v3, v6
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s7, v0
-; SI-GISEL-NEXT: v_log_f32_e32 v5, v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v5
-; SI-GISEL-NEXT: v_fma_f32 v2, v5, v2, -v1
-; SI-GISEL-NEXT: v_fma_f32 v2, v5, v3, v2
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log_v2f32:
@@ -757,49 +832,66 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
;
; VI-GISEL-LABEL: s_log_v2f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s6, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v4, v1, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v3
; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s7, v0
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x41b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, v3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
;
@@ -846,41 +938,56 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
;
; GFX900-GISEL-LABEL: s_log_v2f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v4, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s11, v0
-; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v6
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v3, -v1
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v4, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log_v2f32:
@@ -924,38 +1031,53 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v3, 0x3f317217, v1 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3f317217, v1, -v3
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v5, 0x3377d1cf, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v2, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s5
-; GFX1100-GISEL-NEXT: v_fma_f32 v4, 0x3f317217, v0, -v2
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v4, 0x3377d1cf, v0
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_mov_b32 v2, 0
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, s6, s5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s6
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s5, s4
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s3, s2
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
@@ -1130,57 +1252,81 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
;
; SI-GISEL-LABEL: s_log_v3f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
-; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
-; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0
-; SI-GISEL-NEXT: v_fma_f32 v6, v0, v2, -v5
-; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, v6
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, s9, v5
-; SI-GISEL-NEXT: v_log_f32_e32 v5, v5
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_fma_f32 v8, v5, v2, -v7
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_fma_f32 v8, v5, v3, v8
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1
-; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; SI-GISEL-NEXT: v_log_f32_e32 v8, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v5|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v7, s[2:3]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v8
-; SI-GISEL-NEXT: v_fma_f32 v2, v8, v2, -v5
-; SI-GISEL-NEXT: v_fma_f32 v2, v8, v3, v2
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s8, s8, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s1, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
+; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s3, s7, s3
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s8, v5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v6
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v8|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
-; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log_v3f32:
@@ -1256,68 +1402,94 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
;
; VI-GISEL-LABEL: s_log_v3f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
-; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s6, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v3
; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x41b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v3, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s4, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v2
; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_log_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v5, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, v6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; VI-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v6|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
;
@@ -1379,55 +1551,79 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
;
; GFX900-GISEL-LABEL: s_log_v3f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
-; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v2, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6
-; GFX900-GISEL-NEXT: v_ldexp_f32 v6, s9, v6
-; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v2, -v8
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v1
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v9
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v2, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v4, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v9|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v6
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log_v3f32:
@@ -1485,59 +1681,79 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-LABEL: s_log_v3f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x41b17218, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3f317217, v2 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_fma_f32 v8, 0x3f317217, v2, -v5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s6
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3377d1cf, v2
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fma_f32 v6, 0x3f317217, v0, -v3
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v6, 0x3377d1cf, v0 :: v_dual_lshlrev_b32 v1, 5, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s0
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x41b17218, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
-; GFX1100-GISEL-NEXT: v_fma_f32 v7, 0x3f317217, v1, -v4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v7, 0x3377d1cf, v1
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v4, v4, v7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v9 :: v_dual_sub_f32 v1, v1, v10
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s6, s3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s7, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s9, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s3
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
@@ -1767,69 +1983,101 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
;
; SI-GISEL-LABEL: s_log_v4f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s9, s9, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s1, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
; SI-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1
-; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v1
-; SI-GISEL-NEXT: v_fma_f32 v8, v1, v3, -v7
-; SI-GISEL-NEXT: v_fma_f32 v8, v1, v4, v8
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s7, s10, s7
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 5, v8
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v8, s10, v8
-; SI-GISEL-NEXT: v_log_f32_e32 v8, v8
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v8
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_fma_f32 v9, v8, v3, -v7
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; SI-GISEL-NEXT: v_fma_f32 v9, v8, v4, v9
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2
-; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v9
-; SI-GISEL-NEXT: v_log_f32_e32 v9, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v8|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v7, s[2:3]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v9
-; SI-GISEL-NEXT: v_fma_f32 v3, v9, v3, -v7
-; SI-GISEL-NEXT: v_fma_f32 v3, v9, v4, v3
-; SI-GISEL-NEXT: v_add_f32_e32 v3, v7, v3
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v9|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s10, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s7, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v7
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s9, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log_v4f32:
@@ -1923,86 +2171,120 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
;
; VI-GISEL-LABEL: s_log_v4f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3f317000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s9, v1
-; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x41b17218
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v1, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6
-; VI-GISEL-NEXT: v_ldexp_f32 v6, s10, v6
-; VI-GISEL-NEXT: v_log_f32_e32 v6, v6
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v7, v6, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s6, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; VI-GISEL-NEXT: s_and_b32 s4, s9, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s4, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v7, s4, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
+; VI-GISEL-NEXT: v_mul_f32_e32 v9, s4, v3
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_ldexp_f32 v2, s11, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_log_f32_e32 v7, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v7, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
;
@@ -2078,68 +2360,100 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
;
; GFX900-GISEL-LABEL: s_log_v4f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
+; GFX900-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v7, v1
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v7
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v1
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s9, v1
-; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v3, -v8
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v9, 5, v9
-; GFX900-GISEL-NEXT: v_ldexp_f32 v9, s10, v9
-; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v9
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v9
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v3, -v8
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s11, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v10
-; GFX900-GISEL-NEXT: v_log_f32_e32 v10, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v10
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v3, -v8
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v5, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v8, v3
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v10|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log_v4f32:
@@ -2206,69 +2520,104 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-GISEL-LABEL: s_log_v4f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x41b17218, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x41b17218, s9
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v3
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
-; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v7
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s8
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v8
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v7, v7, v12
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, s9, s8
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v8, v8, v13
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3f317217, v0, -v5
-; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3f317217, v1, -v6
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v10, 0x3377d1cf, v0 :: v_dual_fmac_f32 v11, 0x3377d1cf, v1
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_sub_f32 v0, v0, v4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v9 :: v_dual_sub_f32 v2, v2, v14
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v3, v3, v15
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s10, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s10, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s10, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s7, s6
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s10
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s8, s9
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s11, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v3, s3, s4
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: global_store_b128 v5, v[0:3], s[0:1]
+; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_v4f32:
@@ -7446,23 +7795,42 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_v3f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX900-NEXT: v_log_f32_e32 v2, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2
-; GFX900-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
-; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1
-; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_v3f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log_v3f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
@@ -7524,21 +7892,24 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3f317218
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v3, 0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, 0
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v3, 0
; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v2, v2, v3, 0
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_v3f16:
@@ -7588,17 +7959,30 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_v3f16_fast:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_log_f16_e32 v2, v0
-; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX900-NEXT: v_log_f16_e32 v1, v1
-; GFX900-NEXT: v_mul_f16_e32 v2, 0x398c, v2
-; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX900-NEXT: v_mul_f16_e32 v1, 0x398c, v1
-; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_v3f16_fast:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_log_f16_e32 v2, v0
+; GFX900-SDAG-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-SDAG-NEXT: v_log_f16_e32 v1, v1
+; GFX900-SDAG-NEXT: v_mul_f16_e32 v2, 0x398c, v2
+; GFX900-SDAG-NEXT: v_mul_f16_e32 v0, 0x398c, v0
+; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x398c, v1
+; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log_v3f16_fast:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_log_f16_e32 v2, v0
+; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v2, 0x398c, v2
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
+; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
@@ -7646,16 +8030,18 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_v3f16_fast:
@@ -8377,6 +8763,7 @@ define <3 x half> @v_log_v3f16_fpmath(<3 x half> %x) {
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x398c398c
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x398c
; GFX900-GISEL-NEXT: v_pk_mul_f16 v1, v1, v2
@@ -8427,14 +8814,17 @@ define <3 x half> @v_log_v3f16_fpmath(<3 x half> %x) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-FAKE16-NEXT: v_pk_mul_f16 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_pk_mul_f16 v0, 0x398c398c, v0
+; GFX1100-GISEL-FAKE16-NEXT: v_pk_mul_f16 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_v3f16_fpmath:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 7da9a6a9e4eea..0e0454041d90b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -45,30 +45,37 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
;
; SI-GISEL-LABEL: s_log10_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s0, s[4:5], 0xb
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log10_f32:
@@ -107,31 +114,41 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-LABEL: s_log10_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a2000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -165,29 +182,36 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
;
; GFX900-GISEL-LABEL: s_log10_f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v5
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x411a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log10_f32:
@@ -221,28 +245,34 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_f32:
@@ -348,30 +378,37 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
;
; SI-GISEL-LABEL: s_log10_contract_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s0, s[4:5], 0xb
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log10_contract_f32:
@@ -410,31 +447,41 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
; VI-GISEL-LABEL: s_log10_contract_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a2000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -468,29 +515,36 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
;
; GFX900-GISEL-LABEL: s_log10_contract_f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v5
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x411a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log10_contract_f32:
@@ -524,28 +578,34 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_contract_f32:
@@ -667,42 +727,57 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
;
; SI-GISEL-LABEL: s_log10_v2f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
-; SI-GISEL-NEXT: v_fma_f32 v6, v1, v3, v6
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s7, v0
-; SI-GISEL-NEXT: v_log_f32_e32 v5, v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v5
-; SI-GISEL-NEXT: v_fma_f32 v2, v5, v2, -v1
-; SI-GISEL-NEXT: v_fma_f32 v2, v5, v3, v2
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log10_v2f32:
@@ -757,49 +832,66 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
;
; VI-GISEL-LABEL: s_log10_v2f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a2000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s6, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v4, v1, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v3
; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s7, v0
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x411a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, v3, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
;
@@ -846,41 +938,56 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
;
; GFX900-GISEL-LABEL: s_log10_v2f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v4, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s11, v0
-; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v6
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v3, -v1
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v4, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log10_v2f32:
@@ -924,38 +1031,53 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v3, 0x3e9a209a, v1 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3e9a209a, v1, -v3
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v5, 0x3284fbcf, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v2, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s5
-; GFX1100-GISEL-NEXT: v_fma_f32 v4, 0x3e9a209a, v0, -v2
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v4, 0x3284fbcf, v0
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_mov_b32 v2, 0
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, s6, s5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s6
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s5, s4
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s3, s2
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
@@ -1130,57 +1252,81 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; SI-GISEL-LABEL: s_log10_v3f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
-; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
-; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0
-; SI-GISEL-NEXT: v_fma_f32 v6, v0, v2, -v5
-; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, v6
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, s9, v5
-; SI-GISEL-NEXT: v_log_f32_e32 v5, v5
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_fma_f32 v8, v5, v2, -v7
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_fma_f32 v8, v5, v3, v8
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1
-; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; SI-GISEL-NEXT: v_log_f32_e32 v8, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v5|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v7, s[2:3]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v8
-; SI-GISEL-NEXT: v_fma_f32 v2, v8, v2, -v5
-; SI-GISEL-NEXT: v_fma_f32 v2, v8, v3, v2
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s8, s8, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s1, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
+; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s3, s7, s3
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s8, v5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v6
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v8|, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
-; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log10_v3f32:
@@ -1256,68 +1402,94 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; VI-GISEL-LABEL: s_log10_v3f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a2000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
-; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s6, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v3
; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x411a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v3
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v3, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s4, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v2
; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_log_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v5, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v5, v6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; VI-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v6|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
;
@@ -1379,55 +1551,79 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; GFX900-GISEL-LABEL: s_log10_v3f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
-; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v2, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6
-; GFX900-GISEL-NEXT: v_ldexp_f32 v6, s9, v6
-; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v2, -v8
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v1
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v9
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v2, -v6
-; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v4, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v9|, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v6
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log10_v3f32:
@@ -1485,59 +1681,79 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-LABEL: s_log10_v3f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x411a209b, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v2 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_fma_f32 v8, 0x3e9a209a, v2, -v5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s6
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3284fbcf, v2
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fma_f32 v6, 0x3e9a209a, v0, -v3
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v6, 0x3284fbcf, v0 :: v_dual_lshlrev_b32 v1, 5, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s0
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x411a209b, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
-; GFX1100-GISEL-NEXT: v_fma_f32 v7, 0x3e9a209a, v1, -v4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v7, 0x3284fbcf, v1
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v4, v4, v7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v9 :: v_dual_sub_f32 v1, v1, v10
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s6, s3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s7, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s9, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s3
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
@@ -1767,69 +1983,101 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; SI-GISEL-LABEL: s_log10_v4f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s9, s9, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s1, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
; SI-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
-; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1
-; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v1
-; SI-GISEL-NEXT: v_fma_f32 v8, v1, v3, -v7
-; SI-GISEL-NEXT: v_fma_f32 v8, v1, v4, v8
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s7, s10, s7
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 5, v8
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v8, s10, v8
-; SI-GISEL-NEXT: v_log_f32_e32 v8, v8
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v8
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_fma_f32 v9, v8, v3, -v7
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; SI-GISEL-NEXT: v_fma_f32 v9, v8, v4, v9
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2
-; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v9
-; SI-GISEL-NEXT: v_log_f32_e32 v9, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v8|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v7, s[2:3]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v7
-; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v9
-; SI-GISEL-NEXT: v_fma_f32 v3, v9, v3, -v7
-; SI-GISEL-NEXT: v_fma_f32 v3, v9, v4, v3
-; SI-GISEL-NEXT: v_add_f32_e32 v3, v7, v3
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v9|, v5
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s10, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s7, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v7
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s9, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log10_v4f32:
@@ -1923,86 +2171,120 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; VI-GISEL-LABEL: s_log10_v4f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3e9a2000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v1
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s9, v1
-; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x411a209b
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v1, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6
-; VI-GISEL-NEXT: v_ldexp_f32 v6, s10, v6
-; VI-GISEL-NEXT: v_log_f32_e32 v6, v6
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v7, v6, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s6, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; VI-GISEL-NEXT: s_and_b32 s4, s9, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s4, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v7, s4, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
+; VI-GISEL-NEXT: v_mul_f32_e32 v9, s4, v3
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_ldexp_f32 v2, s11, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_log_f32_e32 v7, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5
-; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v7, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
;
@@ -2078,68 +2360,100 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; GFX900-GISEL-LABEL: s_log10_v4f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
+; GFX900-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v7, v1
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v7
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v1
-; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s9, v1
-; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v3, -v8
-; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v9, 5, v9
-; GFX900-GISEL-NEXT: v_ldexp_f32 v9, s10, v9
-; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v9
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v9
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v3, -v8
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s11, v2
-; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v10
-; GFX900-GISEL-NEXT: v_log_f32_e32 v10, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v10
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v3, -v8
-; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v5, v3
-; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v8, v3
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v10|, v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v5
-; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log10_v4f32:
@@ -2206,69 +2520,104 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-LABEL: s_log10_v4f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x411a209b, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x411a209b, s9
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v3
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
-; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v7
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s8
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v8
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v7, v7, v12
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, s9, s8
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
-; GFX1100-GISEL-NEXT: v_add_f32_e32 v8, v8, v13
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3e9a209a, v0, -v5
-; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3e9a209a, v1, -v6
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v10, 0x3284fbcf, v0 :: v_dual_fmac_f32 v11, 0x3284fbcf, v1
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_sub_f32 v0, v0, v4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v9 :: v_dual_sub_f32 v2, v2, v14
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v3, v3, v15
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s10, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s10, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s10, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s7, s6
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s10
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s8, s9
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s11, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v3, s3, s4
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: global_store_b128 v5, v[0:3], s[0:1]
+; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_v4f32:
@@ -7446,23 +7795,42 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_v3f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX900-NEXT: v_log_f32_e32 v2, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2
-; GFX900-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1
-; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_v3f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1
+; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log10_v3f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
@@ -7524,21 +7892,24 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3e9a209b
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v3, 0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, 0
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v3, 0
; GFX1100-GISEL-FAKE16-NEXT: v_fma_mixlo_f16 v2, v2, v3, 0
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_v3f16:
@@ -7588,17 +7959,30 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_v3f16_fast:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_log_f16_e32 v2, v0
-; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX900-NEXT: v_log_f16_e32 v1, v1
-; GFX900-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
-; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX900-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
-; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_v3f16_fast:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_log_f16_e32 v2, v0
+; GFX900-SDAG-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-SDAG-NEXT: v_log_f16_e32 v1, v1
+; GFX900-SDAG-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
+; GFX900-SDAG-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
+; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
+; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log10_v3f16_fast:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_log_f16_e32 v2, v0
+; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
+; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
+; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
@@ -7646,16 +8030,18 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_v3f16_fast:
@@ -8377,6 +8763,7 @@ define <3 x half> @v_log10_v3f16_fpmath(<3 x half> %x) {
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x34d134d1
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x34d1
; GFX900-GISEL-NEXT: v_pk_mul_f16 v1, v1, v2
@@ -8427,14 +8814,17 @@ define <3 x half> @v_log10_v3f16_fpmath(<3 x half> %x) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-FAKE16-NEXT: v_pk_mul_f16 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_pk_mul_f16 v0, 0x34d134d1, v0
+; GFX1100-GISEL-FAKE16-NEXT: v_pk_mul_f16 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_v3f16_fpmath:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index b2ec9534aa848..4a5e11ebb984e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -36,20 +36,23 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
;
; SI-GISEL-LABEL: s_log2_f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x42000000, 0
; SI-GISEL-NEXT: s_mov_b32 s2, -1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -78,15 +81,18 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
@@ -113,19 +119,23 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
;
; GFX900-GISEL-LABEL: s_log2_f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
@@ -150,22 +160,24 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
;
; GFX1100-GISEL-LABEL: s_log2_f32:
; GFX1100-GISEL: ; %bb.0:
-; GFX1100-GISEL-NEXT: s_clause 0x1
-; GFX1100-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s3
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_f32:
@@ -245,27 +257,34 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
;
; SI-GISEL-LABEL: s_log2_v2f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s6, v2
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s7, v0
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v2
-; SI-GISEL-NEXT: v_log_f32_e32 v3, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v1
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log2_v2f32:
@@ -297,26 +316,33 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
;
; VI-GISEL-LABEL: s_log2_v2f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v2, s6, v2
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s7, v0
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v2
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v1
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
;
@@ -348,26 +374,33 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
;
; GFX900-GISEL-LABEL: s_log2_v2f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v3, s10, v3
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s11, v0
-; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v3
-; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v3, v0
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1
-; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log2_v2f32:
@@ -397,28 +430,30 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-LABEL: s_log2_v2f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s6
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX1100-GISEL-NEXT: global_store_b64 v4, v[0:1], s[0:1]
+; GFX1100-GISEL-NEXT: v_dual_subrev_f32 v0, s4, v0 :: v_dual_subrev_f32 v1, s2, v1
+; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v2f32:
@@ -527,31 +562,42 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; SI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, s9, v3
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s9, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v2
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_log_f32_e32 v4, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2
+; SI-GISEL-NEXT: v_log_f32_e32 v3, v1
+; SI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
; SI-GISEL-NEXT: s_endpgm
@@ -597,29 +643,40 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_ldexp_f32 v2, s9, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v2
; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
-; VI-GISEL-NEXT: v_log_f32_e32 v4, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2
+; VI-GISEL-NEXT: v_log_f32_e32 v3, v1
+; VI-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v2
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
@@ -662,34 +719,45 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; GFX900-GISEL-LABEL: s_log2_v3f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX900-GISEL-NEXT: v_ldexp_f32 v4, s1, v4
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
-; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v4
-; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2
-; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s9, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log2_v3f32:
@@ -728,40 +796,43 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; GFX1100-GISEL-LABEL: s_log2_v3f32:
; GFX1100-GISEL: ; %bb.0:
-; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s3
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, s0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, s8
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX1100-GISEL-NEXT: global_store_b96 v6, v[0:2], s[4:5]
+; GFX1100-GISEL-NEXT: v_dual_subrev_f32 v0, s3, v0 :: v_dual_subrev_f32 v1, s6, v1
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v2, s2, v2
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v3f32:
@@ -898,41 +969,56 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-LABEL: s_log2_v4f32:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000
-; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s9, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1
; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[0:1]
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v4, s10, v4
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s11, v2
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, s10, v3
; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2
-; SI-GISEL-NEXT: v_log_f32_e32 v4, v4
-; SI-GISEL-NEXT: v_log_f32_e32 v5, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1]
-; SI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2
-; SI-GISEL-NEXT: v_sub_f32_e32 v3, v5, v3
-; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_log_f32_e32 v4, v2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v2, s4, v3
+; SI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v4
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_log2_v4f32:
@@ -981,41 +1067,56 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; VI-GISEL-LABEL: s_log2_v4f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s9, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s7
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; VI-GISEL-NEXT: v_ldexp_f32 v4, s10, v4
-; VI-GISEL-NEXT: v_ldexp_f32 v2, s11, v2
-; VI-GISEL-NEXT: v_log_f32_e32 v4, v4
-; VI-GISEL-NEXT: v_log_f32_e32 v5, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v5, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v1
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v3, s2, v3
+; VI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v2, s3, v2
+; VI-GISEL-NEXT: v_log_f32_e32 v4, v2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s0, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
;
@@ -1064,41 +1165,56 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; GFX900-GISEL-LABEL: s_log2_v4f32:
; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s9, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v3, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
-; GFX900-GISEL-NEXT: v_ldexp_f32 v5, s10, v5
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s11, v2
-; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5
-; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1]
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v6, v3
-; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, s2, v3
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s3, v2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v3, s0, v4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX900-GISEL-NEXT: s_endpgm
;
; GFX1100-SDAG-LABEL: s_log2_v4f32:
@@ -1142,46 +1258,52 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; GFX1100-GISEL-LABEL: s_log2_v4f32:
; GFX1100-GISEL: ; %bb.0:
-; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX1100-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s8
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s3
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s10, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s9, 0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v3, v3, v7 :: v_dual_lshlrev_b32 v2, 5, v2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, s1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v0, s6, v0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
-; GFX1100-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5]
+; GFX1100-GISEL-NEXT: v_dual_subrev_f32 v1, s10, v1 :: v_dual_subrev_f32 v2, s8, v2
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v3
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v4f32:
@@ -4545,6 +4667,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v3f16:
@@ -4579,12 +4702,14 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_v3f16:
@@ -4652,6 +4777,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v2, v0
+; GFX900-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v3f16_fast:
@@ -4686,12 +4812,14 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_v3f16_fast:
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