[llvm] [AMDGPU][GISel] Add register bank legalization rules for amdgcn_cvt_sr_f16_f32. (PR #203253)

[via llvm-commits]

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@@ -2276,6 +2276,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_set_inactive_chain_arg}, Standard)
       .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32}});
 
+  addRulesForIOpcs({amdgcn_cvt_sr_f16_f32}, Standard)
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anjenner wrote:

Done. Looks like amdgcn_cvt_scalef32_f16_fp8 and amdgcn_cvt_scalef32_f16_bf8 are missing the dst_lo_hi_sel operand. Should I open a separate PR to add it there too?

https://github.com/llvm/llvm-project/pull/203253