[llvm] [AArch64][SVE] Use ADD/ADR instead of MUL/MLA for x*N (PR #198566)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,233 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 4 x i32> @mul_i32_by_2(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: mul_i32_by_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.s, z0.s, #1
+; CHECK-NEXT:    ret
+  %out = mul <vscale x 4 x i32> %x, splat(i32 2)
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @mul_i32_by_3(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: mul_i32_by_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adr z0.s, [z0.s, z0.s, lsl #1]
+; CHECK-NEXT:    ret
+  %out = mul <vscale x 4 x i32> %x, splat(i32 3)
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @mul_i32_by_5(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: mul_i32_by_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adr z0.s, [z0.s, z0.s, lsl #2]
+; CHECK-NEXT:    ret
+  %out = mul <vscale x 4 x i32> %x, splat(i32 5)
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @mul_i32_by_9(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: mul_i32_by_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adr z0.s, [z0.s, z0.s, lsl #3]
+; CHECK-NEXT:    ret
+  %out = mul <vscale x 4 x i32> %x, splat(i32 9)
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 2 x i64> @mul_i64_by_5_commuted(<vscale x 2 x i64> %x) {
+; CHECK-LABEL: mul_i64_by_5_commuted:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adr z0.d, [z0.d, z0.d, lsl #2]
+; CHECK-NEXT:    ret
+  %out = mul <vscale x 2 x i64> splat(i64 5), %x
+  ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 4 x i32> @mla_i32_by_2(<vscale x 4 x i32> %a,
+                                        <vscale x 4 x i32> %x) {
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paulwalker-arm wrote:

I recall splitting function definitions across multiple lines like this causing trouble when somebody then tries to update the file using update_llc_test_checks.py.

https://github.com/llvm/llvm-project/pull/198566