[llvm] AMDGPU: Shrink extracted dword vector loads (PR #203484)

[Matt Arsenault via llvm-commits]

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@@ -16518,6 +16505,171 @@ bool SITargetLowering::shouldExpandVectorDynExt(SDNode *N) const {
       EltSize, NumElem, Idx->isDivergent(), getSubtarget());
 }
 
+// Return true if this load may select to an SMRD instruction.
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arsenm wrote:

We repeat these conditions in several places 

https://github.com/llvm/llvm-project/pull/203484