[llvm] AMDGPU/GlobalISel: Fix regBankLegalize rules for uniform cvt_pkrtz (PR #203283)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 03:32:32 PDT 2026
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/203283
>From 3c4ac7d8561c993230a8de6081b9be6a8fcbb0f3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Wed, 10 Jun 2026 17:49:33 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Fix regBankLegalize rules for uniform
cvt_pkrtz
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 7 +-
llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll | 276 ++++++------------
2 files changed, 90 insertions(+), 193 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index ece2552ef32ae..344059d8df1c3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2046,11 +2046,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr32, Vgpr32}, V_BFE});
addRulesForIOpcs({amdgcn_cvt_pk_i16, amdgcn_cvt_pk_u16, amdgcn_cvt_pknorm_i16,
- amdgcn_cvt_pknorm_u16, amdgcn_cvt_pkrtz},
+ amdgcn_cvt_pknorm_u16},
Standard)
.Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32}})
.Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32}});
+ addRulesForIOpcs({amdgcn_cvt_pkrtz}, Standard)
+ .Uni(V2S16, {{SgprV2S16}, {IntrId, Sgpr32, Sgpr32}}, hasSALUFloat)
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32}}, !hasSALUFloat)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32}});
+
addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk32_bf6_f16,
amdgcn_cvt_scalef32_sr_pk32_fp6_f16,
amdgcn_cvt_scalef32_sr_pk32_bf6_bf16,
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
index c01356a0b73ce..9deb70bae8e81 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck -check-prefixes=CHECK,GFX1150-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel -new-reg-bank-select < %s | FileCheck -check-prefixes=CHECK,GFX1150-GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=CHECK,GFX12-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel -new-reg-bank-select < %s | FileCheck -check-prefixes=CHECK,GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck -check-prefixes=CHECK,GFX1150 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel -new-reg-bank-select < %s | FileCheck -check-prefixes=CHECK,GFX1150 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=CHECK,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel -new-reg-bank-select < %s | FileCheck -check-prefixes=CHECK,GFX12 %s
define amdgpu_vs float @fadd_f32(float inreg %a, float inreg %b) {
; CHECK-LABEL: fadd_f32:
@@ -38,67 +38,35 @@ define amdgpu_vs float @fmul_f32(float inreg %a, float inreg %b) {
}
define amdgpu_vs float @fmin_f32(float inreg %a, float inreg %b) {
-;
-; GFX1150-SDAG-LABEL: fmin_f32:
-; GFX1150-SDAG: ; %bb.0:
-; GFX1150-SDAG-NEXT: s_min_f32 s0, s0, s1
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX1150-GISEL-LABEL: fmin_f32:
-; GFX1150-GISEL: ; %bb.0:
-; GFX1150-GISEL-NEXT: s_min_f32 s0, s0, s1
-; GFX1150-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX12-SDAG-LABEL: fmin_f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_min_num_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: fmin_f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_min_num_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX1150-LABEL: fmin_f32:
+; GFX1150: ; %bb.0:
+; GFX1150-NEXT: s_min_f32 s0, s0, s1
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-NEXT: v_mov_b32_e32 v0, s0
+; GFX1150-NEXT: ; return to shader part epilog
+; GFX12-LABEL: fmin_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%min = call float @llvm.minnum.f32(float %a, float %b)
ret float %min
}
define amdgpu_vs float @fmax_f32(float inreg %a, float inreg %b) {
-;
-; GFX1150-SDAG-LABEL: fmax_f32:
-; GFX1150-SDAG: ; %bb.0:
-; GFX1150-SDAG-NEXT: s_max_f32 s0, s0, s1
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX1150-GISEL-LABEL: fmax_f32:
-; GFX1150-GISEL: ; %bb.0:
-; GFX1150-GISEL-NEXT: s_max_f32 s0, s0, s1
-; GFX1150-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX12-SDAG-LABEL: fmax_f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_max_num_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: fmax_f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_max_num_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX1150-LABEL: fmax_f32:
+; GFX1150: ; %bb.0:
+; GFX1150-NEXT: s_max_f32 s0, s0, s1
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-NEXT: v_mov_b32_e32 v0, s0
+; GFX1150-NEXT: ; return to shader part epilog
+; GFX12-LABEL: fmax_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%max = call float @llvm.maxnum.f32(float %a, float %b)
ret float %max
}
@@ -137,94 +105,47 @@ define amdgpu_vs half @fmul_f16(half inreg %a, half inreg %b) {
}
define amdgpu_vs half @fmin_f16(half inreg %a, half inreg %b) {
-; GFX1150-SDAG-LABEL: fmin_f16:
-; GFX1150-SDAG: ; %bb.0:
-; GFX1150-SDAG-NEXT: s_min_f16 s0, s0, s1
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX1150-GISEL-LABEL: fmin_f16:
-; GFX1150-GISEL: ; %bb.0:
-; GFX1150-GISEL-NEXT: s_min_f16 s0, s0, s1
-; GFX1150-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX12-SDAG-LABEL: fmin_f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_min_num_f16 s0, s0, s1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: fmin_f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_min_num_f16 s0, s0, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX1150-LABEL: fmin_f16:
+; GFX1150: ; %bb.0:
+; GFX1150-NEXT: s_min_f16 s0, s0, s1
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-NEXT: v_mov_b32_e32 v0, s0
+; GFX1150-NEXT: ; return to shader part epilog
+; GFX12-LABEL: fmin_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_min_num_f16 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%min = call half @llvm.minnum.f16(half %a, half %b)
ret half %min
}
define amdgpu_vs half @fmax_f16(half inreg %a, half inreg %b) {
-; GFX1150-SDAG-LABEL: fmax_f16:
-; GFX1150-SDAG: ; %bb.0:
-; GFX1150-SDAG-NEXT: s_max_f16 s0, s0, s1
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX1150-GISEL-LABEL: fmax_f16:
-; GFX1150-GISEL: ; %bb.0:
-; GFX1150-GISEL-NEXT: s_max_f16 s0, s0, s1
-; GFX1150-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX12-SDAG-LABEL: fmax_f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_max_num_f16 s0, s0, s1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: fmax_f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_max_num_f16 s0, s0, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX1150-LABEL: fmax_f16:
+; GFX1150: ; %bb.0:
+; GFX1150-NEXT: s_max_f16 s0, s0, s1
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-NEXT: v_mov_b32_e32 v0, s0
+; GFX1150-NEXT: ; return to shader part epilog
+; GFX12-LABEL: fmax_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_max_num_f16 s0, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
%max = call half @llvm.maxnum.f16(half %a, half %b)
ret half %max
}
; TODO: Fix GISEL RB legalize rule for amdgcn_cvt_pkrtz to select s_cvt_pk_rtz_f16_f32
define amdgpu_vs <2 x half> @s_cvt_pkrtz_v2f16_f32(float inreg %x, float inreg %y) {
-; GFX1150-SDAG-LABEL: s_cvt_pkrtz_v2f16_f32:
-; GFX1150-SDAG: ; %bb.0:
-; GFX1150-SDAG-NEXT: s_cvt_pk_rtz_f16_f32 s0, s0, s1
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX1150-GISEL-LABEL: s_cvt_pkrtz_v2f16_f32:
-; GFX1150-GISEL: ; %bb.0:
-; GFX1150-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e64 v0, s0, s1
-; GFX1150-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX12-SDAG-LABEL: s_cvt_pkrtz_v2f16_f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_cvt_pk_rtz_f16_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: s_cvt_pkrtz_v2f16_f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e64 v0, s0, s1
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; CHECK-LABEL: s_cvt_pkrtz_v2f16_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_cvt_pk_rtz_f16_f32 s0, s0, s1
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float %y)
ret <2 x half> %result
}
@@ -285,61 +206,32 @@ define amdgpu_vs half @fmac_f16_with_mov(half inreg %a, half inreg %b, half inre
; Regression test for crash in SIFoldOperands
define amdgpu_ps float @_amdgpu_ps_main() {
-; GFX1150-SDAG-LABEL: _amdgpu_ps_main:
-; GFX1150-SDAG: ; %bb.0: ; %bb
-; GFX1150-SDAG-NEXT: s_mov_b32 s0, 0
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-SDAG-NEXT: s_mov_b32 s1, s0
-; GFX1150-SDAG-NEXT: s_mov_b32 s2, s0
-; GFX1150-SDAG-NEXT: s_mov_b32 s3, s0
-; GFX1150-SDAG-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0
-; GFX1150-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1150-SDAG-NEXT: s_fmac_f32 s0, s1, 4.0
-; GFX1150-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX1150-GISEL-LABEL: _amdgpu_ps_main:
-; GFX1150-GISEL: ; %bb.0: ; %bb
-; GFX1150-GISEL-NEXT: s_mov_b32 s0, 0
-; GFX1150-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-GISEL-NEXT: s_mov_b32 s1, s0
-; GFX1150-GISEL-NEXT: s_mov_b32 s2, s0
-; GFX1150-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX1150-GISEL-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0
-; GFX1150-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1150-GISEL-NEXT: s_fmac_f32 s0, s1, 4.0
-; GFX1150-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1150-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX12-SDAG-LABEL: _amdgpu_ps_main:
-; GFX12-SDAG: ; %bb.0: ; %bb
-; GFX12-SDAG-NEXT: s_mov_b32 s0, 0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-SDAG-NEXT: s_mov_b32 s1, s0
-; GFX12-SDAG-NEXT: s_mov_b32 s2, s0
-; GFX12-SDAG-NEXT: s_mov_b32 s3, s0
-; GFX12-SDAG-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: s_fmac_f32 s0, s1, 4.0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: _amdgpu_ps_main:
-; GFX12-GISEL: ; %bb.0: ; %bb
-; GFX12-GISEL-NEXT: s_mov_b32 s0, 0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: s_mov_b32 s1, s0
-; GFX12-GISEL-NEXT: s_mov_b32 s2, s0
-; GFX12-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX12-GISEL-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: s_fmac_f32 s0, s1, 4.0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX1150-LABEL: _amdgpu_ps_main:
+; GFX1150: ; %bb.0: ; %bb
+; GFX1150-NEXT: s_mov_b32 s0, 0
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT: s_mov_b32 s1, s0
+; GFX1150-NEXT: s_mov_b32 s2, s0
+; GFX1150-NEXT: s_mov_b32 s3, s0
+; GFX1150-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0
+; GFX1150-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1150-NEXT: s_fmac_f32 s0, s1, 4.0
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-NEXT: v_mov_b32_e32 v0, s0
+; GFX1150-NEXT: ; return to shader part epilog
+; GFX12-LABEL: _amdgpu_ps_main:
+; GFX12: ; %bb.0: ; %bb
+; GFX12-NEXT: s_mov_b32 s0, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_mov_b32 s1, s0
+; GFX12-NEXT: s_mov_b32 s2, s0
+; GFX12-NEXT: s_mov_b32 s3, s0
+; GFX12-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_fmac_f32 s0, s1, 4.0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
bb:
%i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0)
%i1 = bitcast i32 %i to float
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