[llvm] [GlobalISel][IRTranslator] Lower ptr/non-ptr bitcasts via G_INTTOPTR/G_PTRTOINT (PR #203335)

[Petar Avramovic via llvm-commits]

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@@ -1596,16 +1598,71 @@ bool IRTranslator::translateBitCast(const User &U,
     return translateCopy(U, *U.getOperand(0), MIRBuilder);
   }
 
-  // Only the scalar byte<->ptr crossing is redirected to G_INTTOPTR/G_PTRTOINT,
-  // which is the well-typed MIR shape for that boundary. Vector byte<->ptr
-  // (e.g. <N x b32> -> ptr produced by mixed-type load coalescing) and other
-  // legacy ptr/non-ptr IR bitcasts (AMDGPU iN<->p3 kernarg packing, etc.)
-  // keep their historical G_BITCAST lowering — G_INTTOPTR has no vector-src
-  // -> scalar-ptr form, and downstream passes already handle G_BITCAST.
-  if (DstTy->isPointerTy() && SrcTy->isByteTy())
-    return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
-  if (SrcTy->isPointerTy() && DstTy->isByteTy())
-    return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
+  // Emit G_INTTOPTR
+  if (!SrcTy->isPointerTy() && DstTy->isPointerTy()) {
+    if (DstTyBits == SrcTyBits) {
+      if (!mayTranslateUserTypes(U))
+        return false;
+
+      uint32_t Flags = 0;
+      if (const Instruction *I = dyn_cast<Instruction>(&U))
+        Flags = MachineInstr::copyFlagsFromInstruction(*I);
+
+      Register SrcReg = getOrCreateVReg(*U.getOperand(0));
+      Register DstReg = getOrCreateVReg(U);
+      MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+      LLT IntLLT = LLT::scalar(DstTyBits);
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petar-avramovic wrote:

LLT::integer ? or actually calculate from type

https://github.com/llvm/llvm-project/pull/203335