[llvm] 81e9fa8 - AMDGPU/GlobalISel: RegBankLegalize rules for global_load_async_lds (#203280)
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Fri Jun 12 02:03:50 PDT 2026
Author: Petar Avramovic
Date: 2026-06-12T11:03:46+02:00
New Revision: 81e9fa8d82fd2b6277362c9f27f25ffd24723cb0
URL: https://github.com/llvm/llvm-project/commit/81e9fa8d82fd2b6277362c9f27f25ffd24723cb0
DIFF: https://github.com/llvm/llvm-project/commit/81e9fa8d82fd2b6277362c9f27f25ffd24723cb0.diff
LOG: AMDGPU/GlobalISel: RegBankLegalize rules for global_load_async_lds (#203280)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 3c4c1674d37a8..a7af7ae543576 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2227,6 +2227,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
amdgcn_global_store_async_from_lds_b128})
.Any({{}, {{}, {IntrId, VgprP1, VgprP3}}});
+ addRulesForIOpcs({amdgcn_global_load_async_lds})
+ .Any({{}, {{}, {IntrId, VgprP1, SgprB32_M0}}});
+
addRulesForIOpcs({amdgcn_tensor_load_to_lds, amdgcn_tensor_store_from_lds})
.Any({{},
{{},
diff --git a/llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll b/llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
index ee4f1b3982378..b34d3866a0b75 100644
--- a/llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
+++ b/llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
@@ -1,9 +1,9 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s
; Loop body exceeds MaxAsyncMarkers on first iteration
; Preloop: 5 markers
diff --git a/llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll b/llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
index 46af269d0a0a6..e649208656118 100644
--- a/llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+++ b/llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=SDAG
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GISEL
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GISEL
; Demonstrate that wait.asyncmark is a code motion barrier for loads from LDS.
; This is the simplest demo possible. We don't actually use async ops, but just
@@ -411,26 +411,25 @@ define void @test_pipelined_loop(ptr addrspace(1) %foo, ptr addrspace(3) %lds, p
; GISEL-NEXT: global_load_dword v[0:1], off lds
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: global_load_dword v[0:1], off lds
-; GISEL-NEXT: s_mov_b32 s6, 0
-; GISEL-NEXT: s_mov_b32 s7, 2
+; GISEL-NEXT: s_mov_b32 s7, 0
+; GISEL-NEXT: s_mov_b32 s6, 2
; GISEL-NEXT: s_mov_b64 s[4:5], 0
-; GISEL-NEXT: v_mov_b32_e32 v6, s7
-; GISEL-NEXT: v_mov_b32_e32 v5, s6
+; GISEL-NEXT: v_mov_b32_e32 v5, s7
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: .LBB4_1: ; %loop_body
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: v_readfirstlane_b32 s6, v2
-; GISEL-NEXT: s_mov_b32 m0, s6
-; GISEL-NEXT: v_add_u32_e32 v6, 1, v6
+; GISEL-NEXT: v_readfirstlane_b32 s7, v2
+; GISEL-NEXT: s_mov_b32 m0, s7
+; GISEL-NEXT: s_add_i32 s6, s6, 1
; GISEL-NEXT: global_load_dword v[0:1], off lds
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: ; wait_asyncmark(2)
; GISEL-NEXT: s_waitcnt vmcnt(2)
-; GISEL-NEXT: ds_read_b32 v8, v2
-; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, v6, v7
+; GISEL-NEXT: ds_read_b32 v6, v2
+; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, s6, v7
; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-NEXT: v_add_u32_e32 v5, v5, v8
+; GISEL-NEXT: v_add_u32_e32 v5, v5, v6
; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GISEL-NEXT: s_cbranch_execnz .LBB4_1
; GISEL-NEXT: ; %bb.2: ; %epilog
@@ -567,7 +566,6 @@ define void @test_pipelined_loop_with_global(ptr addrspace(1) %foo, ptr addrspac
; GISEL-NEXT: global_load_dword v9, v[3:4], off
; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: global_load_dword v[0:1], off lds
-; GISEL-NEXT: v_mov_b32_e32 v16, s6
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: s_waitcnt vmcnt(2)
; GISEL-NEXT: v_mov_b32_e32 v13, v8
@@ -575,18 +573,18 @@ define void @test_pipelined_loop_with_global(ptr addrspace(1) %foo, ptr addrspac
; GISEL-NEXT: v_mov_b32_e32 v15, v9
; GISEL-NEXT: .LBB5_1: ; %loop_body
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GISEL-NEXT: v_readfirstlane_b32 s7, v2
; GISEL-NEXT: s_waitcnt vmcnt(1)
; GISEL-NEXT: v_mov_b32_e32 v12, v15
; GISEL-NEXT: v_mov_b32_e32 v11, v13
; GISEL-NEXT: global_load_dword v13, v[0:1], off
; GISEL-NEXT: global_load_dword v15, v[3:4], off
-; GISEL-NEXT: s_mov_b32 m0, s6
-; GISEL-NEXT: v_add_u32_e32 v16, 1, v16
+; GISEL-NEXT: s_mov_b32 m0, s7
+; GISEL-NEXT: s_add_i32 s6, s6, 1
; GISEL-NEXT: global_load_dword v[0:1], off lds
-; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, v16, v7
-; GISEL-NEXT: v_mov_b32_e32 v17, v14
-; GISEL-NEXT: v_mov_b32_e32 v18, v10
+; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, s6, v7
+; GISEL-NEXT: v_mov_b32_e32 v16, v14
+; GISEL-NEXT: v_mov_b32_e32 v17, v10
; GISEL-NEXT: v_mov_b32_e32 v10, v8
; GISEL-NEXT: v_mov_b32_e32 v14, v9
; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -603,7 +601,7 @@ define void @test_pipelined_loop_with_global(ptr addrspace(1) %foo, ptr addrspac
; GISEL-NEXT: ; wait_asyncmark(0)
; GISEL-NEXT: s_waitcnt vmcnt(0)
; GISEL-NEXT: ds_read_b32 v2, v2
-; GISEL-NEXT: v_add_u32_e32 v3, v18, v17
+; GISEL-NEXT: v_add_u32_e32 v3, v17, v16
; GISEL-NEXT: s_waitcnt lgkmcnt(2)
; GISEL-NEXT: v_add3_u32 v0, v3, v0, v12
; GISEL-NEXT: s_waitcnt lgkmcnt(1)
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