[llvm] [RISCV][P-ext] packed exchanged add/sub codegen (PR #203473)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 12 00:30:48 PDT 2026
https://github.com/sihuan updated https://github.com/llvm/llvm-project/pull/203473
>From cd62e6a5d8d4605ad82c8e47b1763feb1f3447cb Mon Sep 17 00:00:00 2001
From: SiHuaN <liyongtai at iscas.ac.cn>
Date: Fri, 12 Jun 2026 15:27:23 +0800
Subject: [PATCH] [RISCV][P-ext] packed exchanged add/sub codegen
Wire up the already-defined exchanged add/sub instructions
pas/psa/psas/pssa/paas/pasa with llvm.riscv.* intrinsics and isel patterns.
---
llvm/include/llvm/IR/IntrinsicsRISCV.td | 8 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 66 +++++++-
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 24 +++
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 54 ++++++
llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 174 ++++++++++++++++++++
5 files changed, 325 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index b2add44b19a5e..56a55a14b60b6 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2056,6 +2056,14 @@ class RVPBinaryIntrinsic
def int_riscv_paaddu : RVPBinaryIntrinsic;
def int_riscv_pasub : RVPBinaryIntrinsic;
def int_riscv_pasubu : RVPBinaryIntrinsic;
+
+ // Packed Exchanged Addition and Subtraction.
+ def int_riscv_pas : RVPBinaryIntrinsic;
+ def int_riscv_psa : RVPBinaryIntrinsic;
+ def int_riscv_psas : RVPBinaryIntrinsic;
+ def int_riscv_pssa : RVPBinaryIntrinsic;
+ def int_riscv_paas : RVPBinaryIntrinsic;
+ def int_riscv_pasa : RVPBinaryIntrinsic;
} // TargetPrefix = "riscv"
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 57af056c2d3c0..b265365794dc2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -650,6 +650,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
setOperationAction({ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT},
{MVT::v4i16, MVT::v8i8}, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, {MVT::v4i16, MVT::v8i8}, Legal);
setOperationAction(ISD::EXTRACT_SUBVECTOR, {MVT::v2i16, MVT::v4i8},
Legal);
@@ -11687,6 +11688,63 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
EVT PtrVT = getPointerTy(DAG.getDataLayout());
return DAG.getRegister(RISCV::X4, PtrVT);
}
+ case Intrinsic::riscv_pas:
+ case Intrinsic::riscv_psa:
+ case Intrinsic::riscv_psas:
+ case Intrinsic::riscv_pssa:
+ case Intrinsic::riscv_paas:
+ case Intrinsic::riscv_pasa: {
+ // v2i32 has no paired instruction on RV32; split into a pair of i32 ops
+ // with cross-lane operands. The exchange shape is: even result uses
+ // (S1[0], S2[1]); odd result uses (S1[1], S2[0]).
+ if (Subtarget.is64Bit() || Op.getSimpleValueType() != MVT::v2i32)
+ break;
+
+ unsigned EvenOpc, OddOpc;
+ switch (IntNo) {
+ case Intrinsic::riscv_pas:
+ EvenOpc = ISD::SUB;
+ OddOpc = ISD::ADD;
+ break;
+ case Intrinsic::riscv_psa:
+ EvenOpc = ISD::ADD;
+ OddOpc = ISD::SUB;
+ break;
+ case Intrinsic::riscv_psas:
+ EvenOpc = ISD::SSUBSAT;
+ OddOpc = ISD::SADDSAT;
+ break;
+ case Intrinsic::riscv_pssa:
+ EvenOpc = ISD::SADDSAT;
+ OddOpc = ISD::SSUBSAT;
+ break;
+ case Intrinsic::riscv_paas:
+ EvenOpc = RISCVISD::ASUB;
+ OddOpc = ISD::AVGFLOORS;
+ break;
+ case Intrinsic::riscv_pasa:
+ EvenOpc = ISD::AVGFLOORS;
+ OddOpc = RISCVISD::ASUB;
+ break;
+ default:
+ llvm_unreachable("Unexpected exchanged add/sub intrinsic");
+ }
+
+ SDValue S1 = Op.getOperand(1);
+ SDValue S2 = Op.getOperand(2);
+ SDValue Zero = DAG.getVectorIdxConstant(0, DL);
+ SDValue One = DAG.getVectorIdxConstant(1, DL);
+ SDValue S1Even =
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S1, Zero);
+ SDValue S1Odd = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S1, One);
+ SDValue S2Even =
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S2, Zero);
+ SDValue S2Odd = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S2, One);
+
+ SDValue REven = DAG.getNode(EvenOpc, DL, MVT::i32, S1Even, S2Odd);
+ SDValue ROdd = DAG.getNode(OddOpc, DL, MVT::i32, S1Odd, S2Even);
+ return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, REven, ROdd);
+ }
case Intrinsic::riscv_orc_b:
case Intrinsic::riscv_brev8:
case Intrinsic::riscv_sha256sig0:
@@ -15643,7 +15701,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case Intrinsic::riscv_paadd:
case Intrinsic::riscv_paaddu:
case Intrinsic::riscv_pasub:
- case Intrinsic::riscv_pasubu: {
+ case Intrinsic::riscv_pasubu:
+ case Intrinsic::riscv_pas:
+ case Intrinsic::riscv_psa:
+ case Intrinsic::riscv_psas:
+ case Intrinsic::riscv_pssa:
+ case Intrinsic::riscv_paas:
+ case Intrinsic::riscv_pasa: {
EVT VT = N->getValueType(0);
if (!Subtarget.is64Bit() || (VT != MVT::v4i8 && VT != MVT::v2i16))
return;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index fe1e459967e92..ad7df97e1349c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1984,6 +1984,14 @@ let Predicates = [HasStdExtP] in {
def : PatPSh1Add<PSH1ADD_H, XLenVecI16VT>;
def : PatPSSh1SAdd<PSSH1SADD_H, XLenVecI16VT>;
+ // 16-bit exchanged add/sub patterns
+ def : PatGprGpr<int_riscv_pas, PAS_HX, XLenVecI16VT>;
+ def : PatGprGpr<int_riscv_psa, PSA_HX, XLenVecI16VT>;
+ def : PatGprGpr<int_riscv_psas, PSAS_HX, XLenVecI16VT>;
+ def : PatGprGpr<int_riscv_pssa, PSSA_HX, XLenVecI16VT>;
+ def : PatGprGpr<int_riscv_paas, PAAS_HX, XLenVecI16VT>;
+ def : PatGprGpr<int_riscv_pasa, PASA_HX, XLenVecI16VT>;
+
// 8-bit averaging patterns
def : PatGprGpr<avgfloors, PAADD_B, XLenVecI8VT>;
def : PatGprGpr<avgflooru, PAADDU_B, XLenVecI8VT>;
@@ -2262,6 +2270,14 @@ let append Predicates = [IsRV32] in {
def : PatPSh1AddPair<PSH1ADD_DW, v2i32>;
def : PatPSSh1SAddPair<PSSH1SADD_DW, v2i32>;
+ // 16-bit exchanged add/sub patterns
+ def : PatGprPairGprPair<int_riscv_pas, PAS_DHX, v4i16>;
+ def : PatGprPairGprPair<int_riscv_psa, PSA_DHX, v4i16>;
+ def : PatGprPairGprPair<int_riscv_psas, PSAS_DHX, v4i16>;
+ def : PatGprPairGprPair<int_riscv_pssa, PSSA_DHX, v4i16>;
+ def : PatGprPairGprPair<int_riscv_paas, PAAS_DHX, v4i16>;
+ def : PatGprPairGprPair<int_riscv_pasa, PASA_DHX, v4i16>;
+
// 8-bit averaging patterns
def : PatGprPairGprPair<avgfloors, PAADD_DB, v8i8>;
def : PatGprPairGprPair<avgflooru, PAADDU_DB, v8i8>;
@@ -2498,6 +2514,14 @@ let append Predicates = [IsRV64] in {
def : PatPSh1Add<PSH1ADD_W, v2i32>;
def : PatPSSh1SAdd<PSSH1SADD_W, v2i32>;
+ // 32-bit exchanged add/sub patterns
+ def : PatGprGpr<int_riscv_pas, PAS_WX, v2i32>;
+ def : PatGprGpr<int_riscv_psa, PSA_WX, v2i32>;
+ def : PatGprGpr<int_riscv_psas, PSAS_WX, v2i32>;
+ def : PatGprGpr<int_riscv_pssa, PSSA_WX, v2i32>;
+ def : PatGprGpr<int_riscv_paas, PAAS_WX, v2i32>;
+ def : PatGprGpr<int_riscv_pasa, PASA_WX, v2i32>;
+
// 32-bit averaging patterns
def : PatGprGpr<avgfloors, PAADD_W, v2i32>;
def : PatGprGpr<avgflooru, PAADDU_W, v2i32>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index cddea9ae32d25..f94342fc757b8 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2758,3 +2758,57 @@ define <2 x i16> @test_pasubu_v2i16(<2 x i16> %a, <2 x i16> %b) {
%res = call <2 x i16> @llvm.riscv.pasubu.v2i16(<2 x i16> %a, <2 x i16> %b)
ret <2 x i16> %res
}
+
+define <2 x i16> @test_pas_x_h(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pas_x_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pas.hx a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psa_x_h(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_psa_x_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psa.hx a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psas_x_h(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_psas_x_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psas.hx a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pssa_x_h(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pssa_x_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pssa.hx a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_paas_x_h(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_paas_x_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: paas.hx a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pasa_x_h(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pasa_x_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pasa.hx a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 2fcbc7bfec7f2..6d6a5b80f7ce0 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -4888,3 +4888,177 @@ define <2 x i32> @test_pasubu_v2i32(<2 x i32> %a, <2 x i32> %b) {
%res = call <2 x i32> @llvm.riscv.pasubu.v2i32(<2 x i32> %a, <2 x i32> %b)
ret <2 x i32> %res
}
+
+define <4 x i16> @test_pas_x_h(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pas_x_h:
+; RV32: # %bb.0:
+; RV32-NEXT: pas.dhx a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pas_x_h:
+; RV64: # %bb.0:
+; RV64-NEXT: pas.hx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_psa_x_h(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_psa_x_h:
+; RV32: # %bb.0:
+; RV32-NEXT: psa.dhx a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psa_x_h:
+; RV64: # %bb.0:
+; RV64-NEXT: psa.hx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_psas_x_h(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_psas_x_h:
+; RV32: # %bb.0:
+; RV32-NEXT: psas.dhx a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psas_x_h:
+; RV64: # %bb.0:
+; RV64-NEXT: psas.hx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pssa_x_h(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pssa_x_h:
+; RV32: # %bb.0:
+; RV32-NEXT: pssa.dhx a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssa_x_h:
+; RV64: # %bb.0:
+; RV64-NEXT: pssa.hx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_paas_x_h(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_paas_x_h:
+; RV32: # %bb.0:
+; RV32-NEXT: paas.dhx a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_paas_x_h:
+; RV64: # %bb.0:
+; RV64-NEXT: paas.hx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pasa_x_h(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pasa_x_h:
+; RV32: # %bb.0:
+; RV32-NEXT: pasa.dhx a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pasa_x_h:
+; RV64: # %bb.0:
+; RV64-NEXT: pasa.hx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pasa.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_pas_x_w(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pas_x_w:
+; RV32: # %bb.0:
+; RV32-NEXT: add a1, a1, a2
+; RV32-NEXT: sub a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pas_x_w:
+; RV64: # %bb.0:
+; RV64-NEXT: pas.wx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pas.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_psa_x_w(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_psa_x_w:
+; RV32: # %bb.0:
+; RV32-NEXT: sub a1, a1, a2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psa_x_w:
+; RV64: # %bb.0:
+; RV64-NEXT: psa.wx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psa.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_psas_x_w(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_psas_x_w:
+; RV32: # %bb.0:
+; RV32-NEXT: sadd a1, a1, a2
+; RV32-NEXT: ssub a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psas_x_w:
+; RV64: # %bb.0:
+; RV64-NEXT: psas.wx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psas.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pssa_x_w(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pssa_x_w:
+; RV32: # %bb.0:
+; RV32-NEXT: ssub a1, a1, a2
+; RV32-NEXT: sadd a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssa_x_w:
+; RV64: # %bb.0:
+; RV64-NEXT: pssa.wx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pssa.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_paas_x_w(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_paas_x_w:
+; RV32: # %bb.0:
+; RV32-NEXT: aadd a1, a1, a2
+; RV32-NEXT: asub a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_paas_x_w:
+; RV64: # %bb.0:
+; RV64-NEXT: paas.wx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.paas.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pasa_x_w(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pasa_x_w:
+; RV32: # %bb.0:
+; RV32-NEXT: asub a1, a1, a2
+; RV32-NEXT: aadd a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pasa_x_w:
+; RV64: # %bb.0:
+; RV64-NEXT: pasa.wx a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pasa.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
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