[llvm] [RISCV][P-ext] packed exchanged add/sub codegen (PR #203473)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 161b9811e..b26536579 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11703,17 +11703,29 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     unsigned EvenOpc, OddOpc;
     switch (IntNo) {
     case Intrinsic::riscv_pas:
-      EvenOpc = ISD::SUB;        OddOpc = ISD::ADD;        break;
+      EvenOpc = ISD::SUB;
+      OddOpc = ISD::ADD;
+      break;
     case Intrinsic::riscv_psa:
-      EvenOpc = ISD::ADD;        OddOpc = ISD::SUB;        break;
+      EvenOpc = ISD::ADD;
+      OddOpc = ISD::SUB;
+      break;
     case Intrinsic::riscv_psas:
-      EvenOpc = ISD::SSUBSAT;    OddOpc = ISD::SADDSAT;    break;
+      EvenOpc = ISD::SSUBSAT;
+      OddOpc = ISD::SADDSAT;
+      break;
     case Intrinsic::riscv_pssa:
-      EvenOpc = ISD::SADDSAT;    OddOpc = ISD::SSUBSAT;    break;
+      EvenOpc = ISD::SADDSAT;
+      OddOpc = ISD::SSUBSAT;
+      break;
     case Intrinsic::riscv_paas:
-      EvenOpc = RISCVISD::ASUB;  OddOpc = ISD::AVGFLOORS;  break;
+      EvenOpc = RISCVISD::ASUB;
+      OddOpc = ISD::AVGFLOORS;
+      break;
     case Intrinsic::riscv_pasa:
-      EvenOpc = ISD::AVGFLOORS;  OddOpc = RISCVISD::ASUB;  break;
+      EvenOpc = ISD::AVGFLOORS;
+      OddOpc = RISCVISD::ASUB;
+      break;
     default:
       llvm_unreachable("Unexpected exchanged add/sub intrinsic");
     }
@@ -11722,13 +11734,15 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     SDValue S2 = Op.getOperand(2);
     SDValue Zero = DAG.getVectorIdxConstant(0, DL);
     SDValue One = DAG.getVectorIdxConstant(1, DL);
-    SDValue S1Even = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S1, Zero);
-    SDValue S1Odd  = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S1, One);
-    SDValue S2Even = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S2, Zero);
-    SDValue S2Odd  = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S2, One);
+    SDValue S1Even =
+        DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S1, Zero);
+    SDValue S1Odd = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S1, One);
+    SDValue S2Even =
+        DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S2, Zero);
+    SDValue S2Odd = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, S2, One);
 
     SDValue REven = DAG.getNode(EvenOpc, DL, MVT::i32, S1Even, S2Odd);
-    SDValue ROdd  = DAG.getNode(OddOpc,  DL, MVT::i32, S1Odd,  S2Even);
+    SDValue ROdd = DAG.getNode(OddOpc, DL, MVT::i32, S1Odd, S2Even);
     return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, REven, ROdd);
   }
   case Intrinsic::riscv_orc_b:

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https://github.com/llvm/llvm-project/pull/203473