[compiler-rt] [llvm] [RISC-V] Add newer Linux hwprobe extensions detection (PR #192761)
Jiaqi He via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 22:27:05 PDT 2026
https://github.com/heturing updated https://github.com/llvm/llvm-project/pull/192761
>From c9d61b83c2a1833afa8a106d45a4cf5d3a1fdf87 Mon Sep 17 00:00:00 2001
From: Jiaqi He <heturing at gmail.com>
Date: Fri, 17 Apr 2026 19:26:22 -0600
Subject: [PATCH 1/3] [RISC-V] Update linux feature detection
---
compiler-rt/lib/builtins/cpu_model/riscv.c | 419 +++++++++++++++++++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 36 +-
llvm/lib/TargetParser/Host.cpp | 38 +-
3 files changed, 469 insertions(+), 24 deletions(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 8b4cc957a9784..93cc25c5a60df 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -24,6 +24,7 @@ struct {
unsigned long long mimpid;
} __riscv_cpu_model __attribute__((visibility("hidden"), nocommon));
+<<<<<<< HEAD
// The formatter wants to re-order these includes, but doing so is incorrect:
// clang-format off
#if defined(__linux__)
@@ -32,3 +33,421 @@ struct {
#include "riscv/unimplemented.inc"
#endif
// clang-format on
+=======
+// NOTE: Should sync-up with RISCVFeatures.td
+// TODO: Maybe generate a header from tablegen then include it.
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 0)
+#define B_GROUPID 0
+#define B_BITMASK (1ULL << 1)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 2)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 3)
+#define E_GROUPID 0
+#define E_BITMASK (1ULL << 4)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 5)
+#define H_GROUPID 0
+#define H_BITMASK (1ULL << 7)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 8)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 12)
+#define Q_GROUPID 0
+#define Q_BITMASK (1ULL << 16)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 26)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 27)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 28)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 29)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 30)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 31)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 32)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 33)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 34)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 35)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 36)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 37)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 38)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 39)
+#define ZIHINTPAUSE_GROUPID 0
+#define ZIHINTPAUSE_BITMASK (1ULL << 40)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 41)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 42)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 43)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 44)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 45)
+#define ZKT_GROUPID 0
+#define ZKT_BITMASK (1ULL << 46)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 47)
+#define ZVBB_GROUPID 0
+#define ZVBB_BITMASK (1ULL << 48)
+#define ZVBC_GROUPID 0
+#define ZVBC_BITMASK (1ULL << 49)
+#define ZVFH_GROUPID 0
+#define ZVFH_BITMASK (1ULL << 50)
+#define ZVFHMIN_GROUPID 0
+#define ZVFHMIN_BITMASK (1ULL << 51)
+#define ZVKB_GROUPID 0
+#define ZVKB_BITMASK (1ULL << 52)
+#define ZVKG_GROUPID 0
+#define ZVKG_BITMASK (1ULL << 53)
+#define ZVKNED_GROUPID 0
+#define ZVKNED_BITMASK (1ULL << 54)
+#define ZVKNHA_GROUPID 0
+#define ZVKNHA_BITMASK (1ULL << 55)
+#define ZVKNHB_GROUPID 0
+#define ZVKNHB_BITMASK (1ULL << 56)
+#define ZVKSED_GROUPID 0
+#define ZVKSED_BITMASK (1ULL << 57)
+#define ZVKSH_GROUPID 0
+#define ZVKSH_BITMASK (1ULL << 58)
+#define ZVKT_GROUPID 0
+#define ZVKT_BITMASK (1ULL << 59)
+#define ZVE32X_GROUPID 0
+#define ZVE32X_BITMASK (1ULL << 60)
+#define ZVE32F_GROUPID 0
+#define ZVE32F_BITMASK (1ULL << 61)
+#define ZVE64X_GROUPID 0
+#define ZVE64X_BITMASK (1ULL << 62)
+#define ZVE64F_GROUPID 0
+#define ZVE64F_BITMASK (1ULL << 63)
+#define ZVE64D_GROUPID 1
+#define ZVE64D_BITMASK (1ULL << 0)
+#define ZIMOP_GROUPID 1
+#define ZIMOP_BITMASK (1ULL << 1)
+#define ZCA_GROUPID 1
+#define ZCA_BITMASK (1ULL << 2)
+#define ZCB_GROUPID 1
+#define ZCB_BITMASK (1ULL << 3)
+#define ZCD_GROUPID 1
+#define ZCD_BITMASK (1ULL << 4)
+#define ZCF_GROUPID 1
+#define ZCF_BITMASK (1ULL << 5)
+#define ZCMOP_GROUPID 1
+#define ZCMOP_BITMASK (1ULL << 6)
+#define ZAWRS_GROUPID 1
+#define ZAWRS_BITMASK (1ULL << 7)
+#define ZILSD_GROUPID 1
+#define ZILSD_BITMASK (1ULL << 8)
+#define ZCLSD_GROUPID 1
+#define ZCLSD_BITMASK (1ULL << 9)
+#define ZCMP_GROUPID 1
+#define ZCMP_BITMASK (1ULL << 10)
+#define ZIFENCEI_GROUPID 1
+#define ZIFENCEI_BITMASK (1ULL << 11)
+#define ZMMUL_GROUPID 1
+#define ZMMUL_BITMASK (1ULL << 12)
+#define SUPM_GROUPID 1
+#define SUPM_BITMASK (1ULL << 14)
+#define ZICNTR_GROUPID 1
+#define ZICNTR_BITMASK (1ULL << 15)
+#define ZIHPM_GROUPID 1
+#define ZIHPM_BITMASK (1ULL << 16)
+#define ZFBFMIN_GROUPID 1
+#define ZFBFMIN_BITMASK (1ULL << 17)
+#define ZVFBFMIN_GROUPID 1
+#define ZVFBFMIN_BITMASK (1ULL << 18)
+#define ZVFBFWMA_GROUPID 1
+#define ZVFBFWMA_BITMASK (1ULL << 19)
+#define ZICBOM_GROUPID 1
+#define ZICBOM_BITMASK (1ULL << 20)
+#define ZAAMO_GROUPID 1
+#define ZAAMO_BITMASK (1ULL << 21)
+#define ZALRSC_GROUPID 1
+#define ZALRSC_BITMASK (1ULL << 22)
+#define ZABHA_GROUPID 1
+#define ZABHA_BITMASK (1ULL << 23)
+#define ZALASR_GROUPID 1
+#define ZALASR_BITMASK (1ULL << 24)
+#define ZICBOP_GROUPID 1
+#define ZICBOP_BITMASK (1ULL << 25)
+
+#if defined(__linux__)
+
+// The RISC-V hwprobe interface is documented here:
+// <https://docs.kernel.org/arch/riscv/hwprobe.html>.
+
+static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
+ long arg4, long arg5) {
+ register long a7 __asm__("a7") = number;
+ register long a0 __asm__("a0") = arg1;
+ register long a1 __asm__("a1") = arg2;
+ register long a2 __asm__("a2") = arg3;
+ register long a3 __asm__("a3") = arg4;
+ register long a4 __asm__("a4") = arg5;
+ __asm__ __volatile__("ecall\n\t"
+ : "=r"(a0)
+ : "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
+ : "memory");
+ return a0;
+}
+
+#define RISCV_HWPROBE_KEY_MVENDORID 0
+#define RISCV_HWPROBE_KEY_MARCHID 1
+#define RISCV_HWPROBE_KEY_MIMPID 2
+#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
+#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1ULL << 0)
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
+#define RISCV_HWPROBE_IMA_FD (1ULL << 0)
+#define RISCV_HWPROBE_IMA_C (1ULL << 1)
+#define RISCV_HWPROBE_IMA_V (1ULL << 2)
+#define RISCV_HWPROBE_EXT_ZBA (1ULL << 3)
+#define RISCV_HWPROBE_EXT_ZBB (1ULL << 4)
+#define RISCV_HWPROBE_EXT_ZBS (1ULL << 5)
+#define RISCV_HWPROBE_EXT_ZICBOZ (1ULL << 6)
+#define RISCV_HWPROBE_EXT_ZBC (1ULL << 7)
+#define RISCV_HWPROBE_EXT_ZBKB (1ULL << 8)
+#define RISCV_HWPROBE_EXT_ZBKC (1ULL << 9)
+#define RISCV_HWPROBE_EXT_ZBKX (1ULL << 10)
+#define RISCV_HWPROBE_EXT_ZKND (1ULL << 11)
+#define RISCV_HWPROBE_EXT_ZKNE (1ULL << 12)
+#define RISCV_HWPROBE_EXT_ZKNH (1ULL << 13)
+#define RISCV_HWPROBE_EXT_ZKSED (1ULL << 14)
+#define RISCV_HWPROBE_EXT_ZKSH (1ULL << 15)
+#define RISCV_HWPROBE_EXT_ZKT (1ULL << 16)
+#define RISCV_HWPROBE_EXT_ZVBB (1ULL << 17)
+#define RISCV_HWPROBE_EXT_ZVBC (1ULL << 18)
+#define RISCV_HWPROBE_EXT_ZVKB (1ULL << 19)
+#define RISCV_HWPROBE_EXT_ZVKG (1ULL << 20)
+#define RISCV_HWPROBE_EXT_ZVKNED (1ULL << 21)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1ULL << 22)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1ULL << 23)
+#define RISCV_HWPROBE_EXT_ZVKSED (1ULL << 24)
+#define RISCV_HWPROBE_EXT_ZVKSH (1ULL << 25)
+#define RISCV_HWPROBE_EXT_ZVKT (1ULL << 26)
+#define RISCV_HWPROBE_EXT_ZFH (1ULL << 27)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1ULL << 28)
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1ULL << 29)
+#define RISCV_HWPROBE_EXT_ZVFH (1ULL << 30)
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
+#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
+#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
+#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
+#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
+#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 37)
+#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 38)
+#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39)
+#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40)
+#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41)
+#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 42)
+#define RISCV_HWPROBE_EXT_ZCA (1ULL << 43)
+#define RISCV_HWPROBE_EXT_ZCB (1ULL << 44)
+#define RISCV_HWPROBE_EXT_ZCD (1ULL << 45)
+#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
+#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
+#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
+#define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
+#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 50)
+#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 51)
+#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 52)
+#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53)
+#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54)
+#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
+#define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
+#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
+#define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
+#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
+#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 60)
+#define RISCV_HWPROBE_EXT_ZILSD (1ULL << 61)
+#define RISCV_HWPROBE_EXT_ZCLSD (1ULL << 62)
+#define RISCV_HWPROBE_KEY_CPUPERF_0 5
+#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
+#define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
+#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
+#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
+#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
+#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
+#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
+/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
+
+struct riscv_hwprobe {
+ long long key;
+ unsigned long long value;
+};
+
+#define __NR_riscv_hwprobe 258
+static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
+ return syscall_impl_5_args(__NR_riscv_hwprobe, (long)Hwprobes, len, 0, 0, 0);
+}
+
+#define SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(EXTNAME) \
+ SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_EXT_##EXTNAME, EXTNAME)
+
+#define SET_SINGLE_IMAEXT_RISCV_FEATURE(HWPROBE_BITMASK, EXT) \
+ SET_SINGLE_RISCV_FEATURE(IMAEXT0Value &HWPROBE_BITMASK, EXT)
+
+#define SET_SINGLE_RISCV_FEATURE(COND, EXT) \
+ if (COND) { \
+ SET_RISCV_FEATURE(EXT); \
+ }
+
+#define SET_RISCV_FEATURE(EXT) features[EXT##_GROUPID] |= EXT##_BITMASK
+
+static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
+
+ // Note: If a hwprobe key is unknown to the kernel, its key field
+ // will be cleared to -1, and its value set to 0.
+ // This unsets all extension bitmask bits.
+
+ // Init VendorID, ArchID, ImplID
+ __riscv_cpu_model.mvendorid = Hwprobes[2].value;
+ __riscv_cpu_model.marchid = Hwprobes[3].value;
+ __riscv_cpu_model.mimpid = Hwprobes[4].value;
+
+ // Init standard extension
+ // TODO: Maybe Extension implied generate from tablegen?
+
+ unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
+ int i;
+
+ for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
+ features[i] = 0;
+
+ // Check RISCV_HWPROBE_KEY_BASE_BEHAVIOR
+ unsigned long long BaseValue = Hwprobes[0].value;
+ if (BaseValue & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) {
+ SET_RISCV_FEATURE(I);
+ SET_RISCV_FEATURE(M);
+ SET_RISCV_FEATURE(A);
+ }
+
+ // Check RISCV_HWPROBE_KEY_IMA_EXT_0
+ unsigned long long IMAEXT0Value = Hwprobes[1].value;
+ if (IMAEXT0Value & RISCV_HWPROBE_IMA_FD) {
+ SET_RISCV_FEATURE(F);
+ SET_RISCV_FEATURE(D);
+ }
+
+ SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_C, C);
+ SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_V, V);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBB);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBS);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOZ);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBC);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKB);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKC);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKX);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKND);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNE);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNH);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSED);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSH);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKT);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBB);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBC);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKB);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKG);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNED);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHB);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSED);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSH);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKT);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFH);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFHMIN);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTNTL);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTPAUSE);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFH);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFHMIN);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZTSO);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZACAS);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICOND);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE32X);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE32F);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64X);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64F);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64D);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIMOP);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCB);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCD);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCF);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCMOP);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAWRS);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(SUPM);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICNTR);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHPM);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFBFMIN);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFBFMIN);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFBFWMA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOM);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAAMO);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZALRSC);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZABHA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZALASR);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOP);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZILSD);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCLSD);
+
+ for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
+ __riscv_feature_bits.features[i] = features[i];
+
+ __riscv_feature_bits.length = RISCV_FEATURE_BITS_LENGTH;
+}
+
+#endif // defined(__linux__)
+
+static int FeaturesBitCached = 0;
+
+void __init_riscv_feature_bits(void *);
+static void __init_riscv_feature_bits_ctor(void) CONSTRUCTOR_ATTRIBUTE;
+
+// A constructor function that sets __riscv_feature_bits
+// to the right values. This needs to run only once. This constructor is given
+// the highest priority and it should run before constructors without the
+// priority set. However, it still runs after ifunc initializers and needs to
+// be called explicitly there.
+
+static void CONSTRUCTOR_ATTRIBUTE __init_riscv_feature_bits_ctor(void) {
+ __init_riscv_feature_bits(0);
+}
+
+// PlatformArgs allows the platform to provide pre-computed data and access it
+// without extra effort. For example, Linux could pass the vDSO object to avoid
+// an extra system call.
+void __init_riscv_feature_bits(void *PlatformArgs) {
+
+ if (FeaturesBitCached)
+ return;
+
+#if defined(__linux__)
+ struct riscv_hwprobe Hwprobes[] = {
+ {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0}, {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
+ {RISCV_HWPROBE_KEY_MVENDORID, 0}, {RISCV_HWPROBE_KEY_MARCHID, 0},
+ {RISCV_HWPROBE_KEY_MIMPID, 0},
+ };
+ if (initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0])))
+ return;
+
+ initRISCVFeature(Hwprobes);
+#endif // defined(__linux__)
+
+ FeaturesBitCached = 1;
+}
+>>>>>>> adcbaac7da3f ([RISC-V] Update linux feature detection)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4025b39401b2b..7a49f73d8cb7d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -88,13 +88,15 @@ def FeatureStdExtZic64b
: RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
def FeatureStdExtZicbom
- : RISCVExtension<1, 0, "Cache-Block Management Instructions">;
+ : RISCVExtension<1, 0, "Cache-Block Management Instructions">,
+ RISCVExtensionBitmask<1, 20>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
- : RISCVExtension<1, 0, "Cache-Block Prefetch Instructions">;
+ : RISCVExtension<1, 0, "Cache-Block Prefetch Instructions">,
+ RISCVExtensionBitmask<1, 25>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
@@ -135,7 +137,8 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
def FeatureStdExtZicntr
: RISCVExtension<2, 0, "Base Counters and Timers",
- [FeatureStdExtZicsr]>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<1, 15>;
def FeatureStdExtZicond
: RISCVExtension<1, 0, "Integer Conditional Operations">,
@@ -167,7 +170,8 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
def FeatureStdExtZihpm
: RISCVExtension<2, 0, "Hardware Performance Counters",
- [FeatureStdExtZicsr]>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<1, 16>;
def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">,
RISCVExtensionBitmask<1, 1>;
@@ -218,7 +222,8 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
// Atomic Extensions
def FeatureStdExtZaamo
- : RISCVExtension<1, 0, "Atomic Memory Operations">;
+ : RISCVExtension<1, 0, "Atomic Memory Operations">,
+ RISCVExtensionBitmask<1, 21>;
def HasStdExtZaamo
: Predicate<"Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtZaamo),
@@ -226,7 +231,8 @@ def HasStdExtZaamo
def NoStdExtZaamo : Predicate<"!Subtarget->hasStdExtZaamo()">;
def FeatureStdExtZalrsc
- : RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">;
+ : RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">,
+ RISCVExtensionBitmask<1, 22>;
def HasStdExtZalrsc
: Predicate<"Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtZalrsc),
@@ -256,7 +262,8 @@ def FeatureStdExtZa128rs
def FeatureStdExtZabha
: RISCVExtension<1, 0, "Byte and Halfword Atomic Memory Operations",
- [FeatureStdExtZaamo]>;
+ [FeatureStdExtZaamo]>,
+ RISCVExtensionBitmask<1, 23>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
@@ -271,7 +278,8 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
- : RISCVExtension<1, 0, "Load-Acquire and Store-Release Instructions">;
+ : RISCVExtension<1, 0, "Load-Acquire and Store-Release Instructions">,
+ RISCVExtensionBitmask<1, 24>;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
@@ -329,7 +337,8 @@ def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
- : RISCVExtension<1, 0, "Scalar BF16 Converts", [FeatureStdExtF]>;
+ : RISCVExtension<1, 0, "Scalar BF16 Converts", [FeatureStdExtF]>,
+ RISCVExtensionBitmask<1, 17>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -720,14 +729,16 @@ def FeatureStdExtZvfbfa
[FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
def FeatureStdExtZvfbfmin
- : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>;
+ : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>,
+ RISCVExtensionBitmask<1, 18>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
def FeatureStdExtZvfbfwma
: RISCVExtension<1, 0, "Vector BF16 widening mul-add",
- [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
+ [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>,
+ RISCVExtensionBitmask<1, 19>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -1198,7 +1209,8 @@ def FeatureStdExtSspm
// environment to control pointer masking.
def FeatureStdExtSupm
: RISCVExtension<1, 0,
- "Indicates User-mode Pointer Masking">;
+ "Indicates User-mode Pointer Masking">,
+ RISCVExtensionBitmask<1, 14>;
def FeatureStdExtSmctr
: RISCVExtension<1, 0,
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 9557aa41a4326..5bc66c5598a21 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -2563,18 +2563,32 @@ StringMap<bool> sys::getHostCPUFeatures() {
Features["zicond"] = ExtMask & (1ULL << 35); // RISCV_HWPROBE_EXT_ZICOND
Features["zihintpause"] =
ExtMask & (1ULL << 36); // RISCV_HWPROBE_EXT_ZIHINTPAUSE
- Features["zve32x"] = ExtMask & (1ULL << 37); // RISCV_HWPROBE_EXT_ZVE32X
- Features["zve32f"] = ExtMask & (1ULL << 38); // RISCV_HWPROBE_EXT_ZVE32F
- Features["zve64x"] = ExtMask & (1ULL << 39); // RISCV_HWPROBE_EXT_ZVE64X
- Features["zve64f"] = ExtMask & (1ULL << 40); // RISCV_HWPROBE_EXT_ZVE64F
- Features["zve64d"] = ExtMask & (1ULL << 41); // RISCV_HWPROBE_EXT_ZVE64D
- Features["zimop"] = ExtMask & (1ULL << 42); // RISCV_HWPROBE_EXT_ZIMOP
- Features["zca"] = ExtMask & (1ULL << 43); // RISCV_HWPROBE_EXT_ZCA
- Features["zcb"] = ExtMask & (1ULL << 44); // RISCV_HWPROBE_EXT_ZCB
- Features["zcd"] = ExtMask & (1ULL << 45); // RISCV_HWPROBE_EXT_ZCD
- Features["zcf"] = ExtMask & (1ULL << 46); // RISCV_HWPROBE_EXT_ZCF
- Features["zcmop"] = ExtMask & (1ULL << 47); // RISCV_HWPROBE_EXT_ZCMOP
- Features["zawrs"] = ExtMask & (1ULL << 48); // RISCV_HWPROBE_EXT_ZAWRS
+ Features["zve32x"] = ExtMask & (1ULL << 37); // RISCV_HWPROBE_EXT_ZVE32X
+ Features["zve32f"] = ExtMask & (1ULL << 38); // RISCV_HWPROBE_EXT_ZVE32F
+ Features["zve64x"] = ExtMask & (1ULL << 39); // RISCV_HWPROBE_EXT_ZVE64X
+ Features["zve64f"] = ExtMask & (1ULL << 40); // RISCV_HWPROBE_EXT_ZVE64F
+ Features["zve64d"] = ExtMask & (1ULL << 41); // RISCV_HWPROBE_EXT_ZVE64D
+ Features["zimop"] = ExtMask & (1ULL << 42); // RISCV_HWPROBE_EXT_ZIMOP
+ Features["zca"] = ExtMask & (1ULL << 43); // RISCV_HWPROBE_EXT_ZCA
+ Features["zcb"] = ExtMask & (1ULL << 44); // RISCV_HWPROBE_EXT_ZCB
+ Features["zcd"] = ExtMask & (1ULL << 45); // RISCV_HWPROBE_EXT_ZCD
+ Features["zcf"] = ExtMask & (1ULL << 46); // RISCV_HWPROBE_EXT_ZCF
+ Features["zcmop"] = ExtMask & (1ULL << 47); // RISCV_HWPROBE_EXT_ZCMOP
+ Features["zawrs"] = ExtMask & (1ULL << 48); // RISCV_HWPROBE_EXT_ZAWRS
+ Features["supm"] = ExtMask & (1ULL << 49); // RISCV_HWPROBE_EXT_SUPM
+ Features["zicntr"] = ExtMask & (1ULL << 50); // RISCV_HWPROBE_EXT_ZICNTR
+ Features["zihpm"] = ExtMask & (1ULL << 51); // RISCV_HWPROBE_EXT_ZIHPM
+ Features["zfbfmin"] = ExtMask & (1ULL << 52); // RISCV_HWPROBE_EXT_ZFBFMIN
+ Features["zvfbfmin"] = ExtMask & (1ULL << 53); // RISCV_HWPROBE_EXT_ZVFBFMIN
+ Features["zvfbfwma"] = ExtMask & (1ULL << 54); // RISCV_HWPROBE_EXT_ZVFBFWMA
+ Features["zicbom"] = ExtMask & (1ULL << 55); // RISCV_HWPROBE_EXT_ZICBOM
+ Features["zaamo"] = ExtMask & (1ULL << 56); // RISCV_HWPROBE_EXT_ZAAMO
+ Features["zalrsc"] = ExtMask & (1ULL << 57); // RISCV_HWPROBE_EXT_ZALRSC
+ Features["zabha"] = ExtMask & (1ULL << 58); // RISCV_HWPROBE_EXT_ZABHA
+ Features["zalasr"] = ExtMask & (1ULL << 59); // RISCV_HWPROBE_EXT_ZALASR
+ Features["zicbop"] = ExtMask & (1ULL << 60); // RISCV_HWPROBE_EXT_ZICBOP
+ Features["zilsd"] = ExtMask & (1ULL << 61); // RISCV_HWPROBE_EXT_ZILSD
+ Features["zclsd"] = ExtMask & (1ULL << 62); // RISCV_HWPROBE_EXT_ZCLSD
// Check whether the processor supports fast misaligned scalar memory access.
// NOTE: RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF is only available on
>From 0dd00467835a375ee9dd8dd60e513feb559d2370 Mon Sep 17 00:00:00 2001
From: Jiaqi He <heturing at gmail.com>
Date: Tue, 21 Apr 2026 23:28:41 -0600
Subject: [PATCH 2/3] [RISC-V] add support for zibi
---
compiler-rt/lib/builtins/cpu_model/riscv.c | 2 ++
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 93cc25c5a60df..47621d9439cfb 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -160,6 +160,8 @@ struct {
#define ZIFENCEI_BITMASK (1ULL << 11)
#define ZMMUL_GROUPID 1
#define ZMMUL_BITMASK (1ULL << 12)
+#define ZIBI_GROUPID 1
+#define ZIBI_BITMASK (1ULL << 13)
#define SUPM_GROUPID 1
#define SUPM_BITMASK (1ULL << 14)
#define ZICNTR_GROUPID 1
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 7a49f73d8cb7d..871579ee53743 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -79,7 +79,8 @@ def FeatureStdExtE
RISCVExtensionBitmask<0, 4>;
def FeatureStdExtZibi
- : RISCVExperimentalExtension<0, 1, "Branch with Immediate">;
+ : RISCVExperimentalExtension<0, 1, "Branch with Immediate">,
+ RISCVExtensionBitmask<1, 13>;
def HasStdExtZibi : Predicate<"Subtarget->hasStdExtZibi()">,
AssemblerPredicate<(all_of FeatureStdExtZibi),
"'Zibi' (Branch with Immediate)">;
>From 89e9dbdbda9f7e524262beab8ccb7cd04b786808 Mon Sep 17 00:00:00 2001
From: Jiaqi He <heturing at gmail.com>
Date: Thu, 11 Jun 2026 23:15:26 -0600
Subject: [PATCH 3/3] rebase to landed PR
---
compiler-rt/lib/builtins/cpu_model/riscv.c | 421 ------------------
.../lib/builtins/cpu_model/riscv/hwprobe.inc | 54 +++
2 files changed, 54 insertions(+), 421 deletions(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 47621d9439cfb..8b4cc957a9784 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -24,7 +24,6 @@ struct {
unsigned long long mimpid;
} __riscv_cpu_model __attribute__((visibility("hidden"), nocommon));
-<<<<<<< HEAD
// The formatter wants to re-order these includes, but doing so is incorrect:
// clang-format off
#if defined(__linux__)
@@ -33,423 +32,3 @@ struct {
#include "riscv/unimplemented.inc"
#endif
// clang-format on
-=======
-// NOTE: Should sync-up with RISCVFeatures.td
-// TODO: Maybe generate a header from tablegen then include it.
-#define A_GROUPID 0
-#define A_BITMASK (1ULL << 0)
-#define B_GROUPID 0
-#define B_BITMASK (1ULL << 1)
-#define C_GROUPID 0
-#define C_BITMASK (1ULL << 2)
-#define D_GROUPID 0
-#define D_BITMASK (1ULL << 3)
-#define E_GROUPID 0
-#define E_BITMASK (1ULL << 4)
-#define F_GROUPID 0
-#define F_BITMASK (1ULL << 5)
-#define H_GROUPID 0
-#define H_BITMASK (1ULL << 7)
-#define I_GROUPID 0
-#define I_BITMASK (1ULL << 8)
-#define M_GROUPID 0
-#define M_BITMASK (1ULL << 12)
-#define Q_GROUPID 0
-#define Q_BITMASK (1ULL << 16)
-#define V_GROUPID 0
-#define V_BITMASK (1ULL << 21)
-#define ZACAS_GROUPID 0
-#define ZACAS_BITMASK (1ULL << 26)
-#define ZBA_GROUPID 0
-#define ZBA_BITMASK (1ULL << 27)
-#define ZBB_GROUPID 0
-#define ZBB_BITMASK (1ULL << 28)
-#define ZBC_GROUPID 0
-#define ZBC_BITMASK (1ULL << 29)
-#define ZBKB_GROUPID 0
-#define ZBKB_BITMASK (1ULL << 30)
-#define ZBKC_GROUPID 0
-#define ZBKC_BITMASK (1ULL << 31)
-#define ZBKX_GROUPID 0
-#define ZBKX_BITMASK (1ULL << 32)
-#define ZBS_GROUPID 0
-#define ZBS_BITMASK (1ULL << 33)
-#define ZFA_GROUPID 0
-#define ZFA_BITMASK (1ULL << 34)
-#define ZFH_GROUPID 0
-#define ZFH_BITMASK (1ULL << 35)
-#define ZFHMIN_GROUPID 0
-#define ZFHMIN_BITMASK (1ULL << 36)
-#define ZICBOZ_GROUPID 0
-#define ZICBOZ_BITMASK (1ULL << 37)
-#define ZICOND_GROUPID 0
-#define ZICOND_BITMASK (1ULL << 38)
-#define ZIHINTNTL_GROUPID 0
-#define ZIHINTNTL_BITMASK (1ULL << 39)
-#define ZIHINTPAUSE_GROUPID 0
-#define ZIHINTPAUSE_BITMASK (1ULL << 40)
-#define ZKND_GROUPID 0
-#define ZKND_BITMASK (1ULL << 41)
-#define ZKNE_GROUPID 0
-#define ZKNE_BITMASK (1ULL << 42)
-#define ZKNH_GROUPID 0
-#define ZKNH_BITMASK (1ULL << 43)
-#define ZKSED_GROUPID 0
-#define ZKSED_BITMASK (1ULL << 44)
-#define ZKSH_GROUPID 0
-#define ZKSH_BITMASK (1ULL << 45)
-#define ZKT_GROUPID 0
-#define ZKT_BITMASK (1ULL << 46)
-#define ZTSO_GROUPID 0
-#define ZTSO_BITMASK (1ULL << 47)
-#define ZVBB_GROUPID 0
-#define ZVBB_BITMASK (1ULL << 48)
-#define ZVBC_GROUPID 0
-#define ZVBC_BITMASK (1ULL << 49)
-#define ZVFH_GROUPID 0
-#define ZVFH_BITMASK (1ULL << 50)
-#define ZVFHMIN_GROUPID 0
-#define ZVFHMIN_BITMASK (1ULL << 51)
-#define ZVKB_GROUPID 0
-#define ZVKB_BITMASK (1ULL << 52)
-#define ZVKG_GROUPID 0
-#define ZVKG_BITMASK (1ULL << 53)
-#define ZVKNED_GROUPID 0
-#define ZVKNED_BITMASK (1ULL << 54)
-#define ZVKNHA_GROUPID 0
-#define ZVKNHA_BITMASK (1ULL << 55)
-#define ZVKNHB_GROUPID 0
-#define ZVKNHB_BITMASK (1ULL << 56)
-#define ZVKSED_GROUPID 0
-#define ZVKSED_BITMASK (1ULL << 57)
-#define ZVKSH_GROUPID 0
-#define ZVKSH_BITMASK (1ULL << 58)
-#define ZVKT_GROUPID 0
-#define ZVKT_BITMASK (1ULL << 59)
-#define ZVE32X_GROUPID 0
-#define ZVE32X_BITMASK (1ULL << 60)
-#define ZVE32F_GROUPID 0
-#define ZVE32F_BITMASK (1ULL << 61)
-#define ZVE64X_GROUPID 0
-#define ZVE64X_BITMASK (1ULL << 62)
-#define ZVE64F_GROUPID 0
-#define ZVE64F_BITMASK (1ULL << 63)
-#define ZVE64D_GROUPID 1
-#define ZVE64D_BITMASK (1ULL << 0)
-#define ZIMOP_GROUPID 1
-#define ZIMOP_BITMASK (1ULL << 1)
-#define ZCA_GROUPID 1
-#define ZCA_BITMASK (1ULL << 2)
-#define ZCB_GROUPID 1
-#define ZCB_BITMASK (1ULL << 3)
-#define ZCD_GROUPID 1
-#define ZCD_BITMASK (1ULL << 4)
-#define ZCF_GROUPID 1
-#define ZCF_BITMASK (1ULL << 5)
-#define ZCMOP_GROUPID 1
-#define ZCMOP_BITMASK (1ULL << 6)
-#define ZAWRS_GROUPID 1
-#define ZAWRS_BITMASK (1ULL << 7)
-#define ZILSD_GROUPID 1
-#define ZILSD_BITMASK (1ULL << 8)
-#define ZCLSD_GROUPID 1
-#define ZCLSD_BITMASK (1ULL << 9)
-#define ZCMP_GROUPID 1
-#define ZCMP_BITMASK (1ULL << 10)
-#define ZIFENCEI_GROUPID 1
-#define ZIFENCEI_BITMASK (1ULL << 11)
-#define ZMMUL_GROUPID 1
-#define ZMMUL_BITMASK (1ULL << 12)
-#define ZIBI_GROUPID 1
-#define ZIBI_BITMASK (1ULL << 13)
-#define SUPM_GROUPID 1
-#define SUPM_BITMASK (1ULL << 14)
-#define ZICNTR_GROUPID 1
-#define ZICNTR_BITMASK (1ULL << 15)
-#define ZIHPM_GROUPID 1
-#define ZIHPM_BITMASK (1ULL << 16)
-#define ZFBFMIN_GROUPID 1
-#define ZFBFMIN_BITMASK (1ULL << 17)
-#define ZVFBFMIN_GROUPID 1
-#define ZVFBFMIN_BITMASK (1ULL << 18)
-#define ZVFBFWMA_GROUPID 1
-#define ZVFBFWMA_BITMASK (1ULL << 19)
-#define ZICBOM_GROUPID 1
-#define ZICBOM_BITMASK (1ULL << 20)
-#define ZAAMO_GROUPID 1
-#define ZAAMO_BITMASK (1ULL << 21)
-#define ZALRSC_GROUPID 1
-#define ZALRSC_BITMASK (1ULL << 22)
-#define ZABHA_GROUPID 1
-#define ZABHA_BITMASK (1ULL << 23)
-#define ZALASR_GROUPID 1
-#define ZALASR_BITMASK (1ULL << 24)
-#define ZICBOP_GROUPID 1
-#define ZICBOP_BITMASK (1ULL << 25)
-
-#if defined(__linux__)
-
-// The RISC-V hwprobe interface is documented here:
-// <https://docs.kernel.org/arch/riscv/hwprobe.html>.
-
-static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
- long arg4, long arg5) {
- register long a7 __asm__("a7") = number;
- register long a0 __asm__("a0") = arg1;
- register long a1 __asm__("a1") = arg2;
- register long a2 __asm__("a2") = arg3;
- register long a3 __asm__("a3") = arg4;
- register long a4 __asm__("a4") = arg5;
- __asm__ __volatile__("ecall\n\t"
- : "=r"(a0)
- : "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
- : "memory");
- return a0;
-}
-
-#define RISCV_HWPROBE_KEY_MVENDORID 0
-#define RISCV_HWPROBE_KEY_MARCHID 1
-#define RISCV_HWPROBE_KEY_MIMPID 2
-#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
-#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1ULL << 0)
-#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
-#define RISCV_HWPROBE_IMA_FD (1ULL << 0)
-#define RISCV_HWPROBE_IMA_C (1ULL << 1)
-#define RISCV_HWPROBE_IMA_V (1ULL << 2)
-#define RISCV_HWPROBE_EXT_ZBA (1ULL << 3)
-#define RISCV_HWPROBE_EXT_ZBB (1ULL << 4)
-#define RISCV_HWPROBE_EXT_ZBS (1ULL << 5)
-#define RISCV_HWPROBE_EXT_ZICBOZ (1ULL << 6)
-#define RISCV_HWPROBE_EXT_ZBC (1ULL << 7)
-#define RISCV_HWPROBE_EXT_ZBKB (1ULL << 8)
-#define RISCV_HWPROBE_EXT_ZBKC (1ULL << 9)
-#define RISCV_HWPROBE_EXT_ZBKX (1ULL << 10)
-#define RISCV_HWPROBE_EXT_ZKND (1ULL << 11)
-#define RISCV_HWPROBE_EXT_ZKNE (1ULL << 12)
-#define RISCV_HWPROBE_EXT_ZKNH (1ULL << 13)
-#define RISCV_HWPROBE_EXT_ZKSED (1ULL << 14)
-#define RISCV_HWPROBE_EXT_ZKSH (1ULL << 15)
-#define RISCV_HWPROBE_EXT_ZKT (1ULL << 16)
-#define RISCV_HWPROBE_EXT_ZVBB (1ULL << 17)
-#define RISCV_HWPROBE_EXT_ZVBC (1ULL << 18)
-#define RISCV_HWPROBE_EXT_ZVKB (1ULL << 19)
-#define RISCV_HWPROBE_EXT_ZVKG (1ULL << 20)
-#define RISCV_HWPROBE_EXT_ZVKNED (1ULL << 21)
-#define RISCV_HWPROBE_EXT_ZVKNHA (1ULL << 22)
-#define RISCV_HWPROBE_EXT_ZVKNHB (1ULL << 23)
-#define RISCV_HWPROBE_EXT_ZVKSED (1ULL << 24)
-#define RISCV_HWPROBE_EXT_ZVKSH (1ULL << 25)
-#define RISCV_HWPROBE_EXT_ZVKT (1ULL << 26)
-#define RISCV_HWPROBE_EXT_ZFH (1ULL << 27)
-#define RISCV_HWPROBE_EXT_ZFHMIN (1ULL << 28)
-#define RISCV_HWPROBE_EXT_ZIHINTNTL (1ULL << 29)
-#define RISCV_HWPROBE_EXT_ZVFH (1ULL << 30)
-#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
-#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
-#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
-#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
-#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
-#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
-#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 37)
-#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 38)
-#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39)
-#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40)
-#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41)
-#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 42)
-#define RISCV_HWPROBE_EXT_ZCA (1ULL << 43)
-#define RISCV_HWPROBE_EXT_ZCB (1ULL << 44)
-#define RISCV_HWPROBE_EXT_ZCD (1ULL << 45)
-#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
-#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
-#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
-#define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
-#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 50)
-#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 51)
-#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 52)
-#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53)
-#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54)
-#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
-#define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
-#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
-#define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
-#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
-#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 60)
-#define RISCV_HWPROBE_EXT_ZILSD (1ULL << 61)
-#define RISCV_HWPROBE_EXT_ZCLSD (1ULL << 62)
-#define RISCV_HWPROBE_KEY_CPUPERF_0 5
-#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
-#define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
-#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
-#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
-#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
-#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
-#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
-/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
-
-struct riscv_hwprobe {
- long long key;
- unsigned long long value;
-};
-
-#define __NR_riscv_hwprobe 258
-static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
- return syscall_impl_5_args(__NR_riscv_hwprobe, (long)Hwprobes, len, 0, 0, 0);
-}
-
-#define SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(EXTNAME) \
- SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_EXT_##EXTNAME, EXTNAME)
-
-#define SET_SINGLE_IMAEXT_RISCV_FEATURE(HWPROBE_BITMASK, EXT) \
- SET_SINGLE_RISCV_FEATURE(IMAEXT0Value &HWPROBE_BITMASK, EXT)
-
-#define SET_SINGLE_RISCV_FEATURE(COND, EXT) \
- if (COND) { \
- SET_RISCV_FEATURE(EXT); \
- }
-
-#define SET_RISCV_FEATURE(EXT) features[EXT##_GROUPID] |= EXT##_BITMASK
-
-static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
-
- // Note: If a hwprobe key is unknown to the kernel, its key field
- // will be cleared to -1, and its value set to 0.
- // This unsets all extension bitmask bits.
-
- // Init VendorID, ArchID, ImplID
- __riscv_cpu_model.mvendorid = Hwprobes[2].value;
- __riscv_cpu_model.marchid = Hwprobes[3].value;
- __riscv_cpu_model.mimpid = Hwprobes[4].value;
-
- // Init standard extension
- // TODO: Maybe Extension implied generate from tablegen?
-
- unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
- int i;
-
- for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
- features[i] = 0;
-
- // Check RISCV_HWPROBE_KEY_BASE_BEHAVIOR
- unsigned long long BaseValue = Hwprobes[0].value;
- if (BaseValue & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) {
- SET_RISCV_FEATURE(I);
- SET_RISCV_FEATURE(M);
- SET_RISCV_FEATURE(A);
- }
-
- // Check RISCV_HWPROBE_KEY_IMA_EXT_0
- unsigned long long IMAEXT0Value = Hwprobes[1].value;
- if (IMAEXT0Value & RISCV_HWPROBE_IMA_FD) {
- SET_RISCV_FEATURE(F);
- SET_RISCV_FEATURE(D);
- }
-
- SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_C, C);
- SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_V, V);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBA);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBB);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBS);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOZ);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBC);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKB);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKC);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKX);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKND);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNE);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNH);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSED);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSH);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKT);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBB);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBC);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKB);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKG);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNED);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHA);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHB);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSED);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSH);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKT);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFH);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFHMIN);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTNTL);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTPAUSE);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFH);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFHMIN);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFA);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZTSO);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZACAS);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICOND);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE32X);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE32F);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64X);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64F);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64D);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIMOP);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCA);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCB);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCD);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCF);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCMOP);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAWRS);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(SUPM);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICNTR);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHPM);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFBFMIN);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFBFMIN);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFBFWMA);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOM);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAAMO);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZALRSC);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZABHA);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZALASR);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOP);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZILSD);
- SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCLSD);
-
- for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
- __riscv_feature_bits.features[i] = features[i];
-
- __riscv_feature_bits.length = RISCV_FEATURE_BITS_LENGTH;
-}
-
-#endif // defined(__linux__)
-
-static int FeaturesBitCached = 0;
-
-void __init_riscv_feature_bits(void *);
-static void __init_riscv_feature_bits_ctor(void) CONSTRUCTOR_ATTRIBUTE;
-
-// A constructor function that sets __riscv_feature_bits
-// to the right values. This needs to run only once. This constructor is given
-// the highest priority and it should run before constructors without the
-// priority set. However, it still runs after ifunc initializers and needs to
-// be called explicitly there.
-
-static void CONSTRUCTOR_ATTRIBUTE __init_riscv_feature_bits_ctor(void) {
- __init_riscv_feature_bits(0);
-}
-
-// PlatformArgs allows the platform to provide pre-computed data and access it
-// without extra effort. For example, Linux could pass the vDSO object to avoid
-// an extra system call.
-void __init_riscv_feature_bits(void *PlatformArgs) {
-
- if (FeaturesBitCached)
- return;
-
-#if defined(__linux__)
- struct riscv_hwprobe Hwprobes[] = {
- {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0}, {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
- {RISCV_HWPROBE_KEY_MVENDORID, 0}, {RISCV_HWPROBE_KEY_MARCHID, 0},
- {RISCV_HWPROBE_KEY_MIMPID, 0},
- };
- if (initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0])))
- return;
-
- initRISCVFeature(Hwprobes);
-#endif // defined(__linux__)
-
- FeaturesBitCached = 1;
-}
->>>>>>> adcbaac7da3f ([RISC-V] Update linux feature detection)
diff --git a/compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc b/compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
index 45508af13ceb3..d34b815cde7da 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
+++ b/compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
@@ -124,6 +124,32 @@
#define ZIFENCEI_BITMASK (1ULL << 11)
#define ZMMUL_GROUPID 1
#define ZMMUL_BITMASK (1ULL << 12)
+#define ZIBI_GROUPID 1
+#define ZIBI_BITMASK (1ULL << 13)
+#define SUPM_GROUPID 1
+#define SUPM_BITMASK (1ULL << 14)
+#define ZICNTR_GROUPID 1
+#define ZICNTR_BITMASK (1ULL << 15)
+#define ZIHPM_GROUPID 1
+#define ZIHPM_BITMASK (1ULL << 16)
+#define ZFBFMIN_GROUPID 1
+#define ZFBFMIN_BITMASK (1ULL << 17)
+#define ZVFBFMIN_GROUPID 1
+#define ZVFBFMIN_BITMASK (1ULL << 18)
+#define ZVFBFWMA_GROUPID 1
+#define ZVFBFWMA_BITMASK (1ULL << 19)
+#define ZICBOM_GROUPID 1
+#define ZICBOM_BITMASK (1ULL << 20)
+#define ZAAMO_GROUPID 1
+#define ZAAMO_BITMASK (1ULL << 21)
+#define ZALRSC_GROUPID 1
+#define ZALRSC_BITMASK (1ULL << 22)
+#define ZABHA_GROUPID 1
+#define ZABHA_BITMASK (1ULL << 23)
+#define ZALASR_GROUPID 1
+#define ZALASR_BITMASK (1ULL << 24)
+#define ZICBOP_GROUPID 1
+#define ZICBOP_BITMASK (1ULL << 25)
// The RISC-V hwprobe interface is documented here:
// <https://docs.kernel.org/arch/riscv/hwprobe.html>.
@@ -198,6 +224,20 @@ static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
+#define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
+#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 50)
+#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 51)
+#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 52)
+#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53)
+#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54)
+#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
+#define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
+#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
+#define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
+#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
+#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 60)
+#define RISCV_HWPROBE_EXT_ZILSD (1ULL << 61)
+#define RISCV_HWPROBE_EXT_ZCLSD (1ULL << 62)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
@@ -314,6 +354,20 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCF);
SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCMOP);
SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAWRS);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(SUPM);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICNTR);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHPM);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFBFMIN);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFBFMIN);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFBFWMA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOM);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAAMO);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZALRSC);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZABHA);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZALASR);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOP);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZILSD);
+ SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCLSD);
for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
__riscv_feature_bits.features[i] = features[i];
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