[llvm] f3f7317 - [AMDGPU] Add MC clamp support for bf16 trans instructions (#203433)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 21:03:17 PDT 2026
Author: Changpeng Fang
Date: 2026-06-11T21:03:11-07:00
New Revision: f3f7317aaf39928329dd453a6a340e6ddd027b81
URL: https://github.com/llvm/llvm-project/commit/f3f7317aaf39928329dd453a6a340e6ddd027b81
DIFF: https://github.com/llvm/llvm-project/commit/f3f7317aaf39928329dd453a6a340e6ddd027b81.diff
LOG: [AMDGPU] Add MC clamp support for bf16 trans instructions (#203433)
Based on recent gfx1250 sp3 update. Refer to DEGFXSP3-664
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/test/CodeGen/AMDGPU/bf16-math.ll
llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 2bc828576e9c7..d504b440b4fe4 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -534,7 +534,7 @@ defm V_CVT_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_i16_f16",
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, fp_to_sint>;
-let HasClamp = 0, HasOMod = 0 in {
+let HasOMod = 0 in {
def V_TRANS_BF16_Profile : VOPProfile <[bf16, bf16, untyped, untyped]>;
def V_TRANS_BF16_t16_Profile : VOPProfile_True16 <VOP_BF16_BF16>;
def V_TRANS_BF16_fake16_Profile : VOPProfile_Fake16 <VOP_BF16_BF16>;
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-math.ll b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
index 4434d8a496a27..fd1db62371aa9 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-math.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
@@ -492,10 +492,7 @@ define amdgpu_ps bfloat @test_clamp_bf16_folding(bfloat %src) {
; FAKE16-LABEL: test_clamp_bf16_folding:
; FAKE16: ; %bb.0:
; FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; FAKE16-NEXT: v_exp_bf16_e32 v0, v0
-; FAKE16-NEXT: v_nop
-; FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; FAKE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 clamp
+; FAKE16-NEXT: v_exp_bf16_e64 v0, v0 clamp
; FAKE16-NEXT: ; return to shader part epilog
%exp = call bfloat @llvm.exp2.bf16(bfloat %src)
%max = call bfloat @llvm.maxnum.bf16(bfloat %exp, bfloat 0.0)
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
index feff79ad59b0b..43733c28be642 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
@@ -35,81 +35,41 @@ v_cvt_f32_bf16 v5, v1 div:2
// GFX1250-ERR-NEXT:{{^}}v_cvt_f32_bf16 v5, v1 div:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_cos_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_cos_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_cos_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_cos_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_exp_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_exp_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_exp_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_exp_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_log_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_log_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_log_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_log_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_rcp_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_rcp_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_rcp_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_rcp_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_rsq_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_rsq_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_rsq_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_rsq_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_sin_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_sin_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_sin_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_sin_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_sqrt_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_sqrt_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_sqrt_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_sqrt_bf16 v1, v2 mul:2
// GFX1250-ERR-NEXT:{{^}} ^
-v_tanh_bf16 v1, v2 clamp
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX1250-ERR-NEXT:{{^}}v_tanh_bf16 v1, v2 clamp
-// GFX1250-ERR-NEXT:{{^}} ^
-
v_tanh_bf16 v1, v2 mul:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_tanh_bf16 v1, v2 mul:2
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
index a879ae1f13cdd..61497adad6206 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
@@ -3748,6 +3748,9 @@ v_tanh_f16_e64 v255, -|0x8000| clamp div:2
v_tanh_bf16_e64 v5, v1
// GFX1250: v_tanh_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x02]
+v_tanh_bf16_e64 v5, v1 clamp
+// GFX1250: v_tanh_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+
v_tanh_bf16_e64 v5, v255
// GFX1250: v_tanh_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xca,0xd5,0xff,0x01,0x01,0x02]
@@ -3820,6 +3823,9 @@ v_prng_b32_e64 v5, -1
v_rcp_bf16_e64 v5, v1
// GFX1250: v_rcp_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x02]
+v_rcp_bf16_e64 v5, v1 clamp
+// GFX1250: v_rcp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+
v_rcp_bf16_e64 v5, v255
// GFX1250: v_rcp_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xf9,0xd5,0xff,0x01,0x01,0x02]
@@ -3856,6 +3862,9 @@ v_rcp_bf16_e64 v5, -1
v_sqrt_bf16_e64 v5, v1
// GFX1250: v_sqrt_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x02]
+v_sqrt_bf16_e64 v5, v1 clamp
+// GFX1250: v_sqrt_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+
v_sqrt_bf16_e64 v5, v255
// GFX1250: v_sqrt_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfa,0xd5,0xff,0x01,0x01,0x02]
@@ -3892,6 +3901,9 @@ v_sqrt_bf16_e64 v5, -1
v_rsq_bf16_e64 v5, v1
// GFX1250: v_rsq_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x02]
+v_rsq_bf16_e64 v5, v1 clamp
+// GFX1250: v_rsq_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+
v_rsq_bf16_e64 v5, v255
// GFX1250: v_rsq_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfb,0xd5,0xff,0x01,0x01,0x02]
@@ -3928,6 +3940,9 @@ v_rsq_bf16_e64 v5, -1
v_log_bf16_e64 v5, v1
// GFX1250: v_log_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x02]
+v_log_bf16_e64 v5, v1 clamp
+// GFX1250: v_log_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+
v_log_bf16_e64 v5, v255
// GFX1250: v_log_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfc,0xd5,0xff,0x01,0x01,0x02]
@@ -3964,6 +3979,9 @@ v_log_bf16_e64 v5, -1
v_exp_bf16_e64 v5, v1
// GFX1250: v_exp_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x02]
+v_exp_bf16_e64 v5, v1 clamp
+// GFX1250: v_exp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+
v_exp_bf16_e64 v5, v255
// GFX1250: v_exp_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfd,0xd5,0xff,0x01,0x01,0x02]
@@ -4000,6 +4018,9 @@ v_exp_bf16_e64 v5, -1
v_sin_bf16_e64 v5, v1
// GFX1250: v_sin_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x02]
+v_sin_bf16_e64 v5, v1 clamp
+// GFX1250: v_sin_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+
v_sin_bf16_e64 v5, v255
// GFX1250: v_sin_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfe,0xd5,0xff,0x01,0x01,0x02]
@@ -4036,6 +4057,9 @@ v_sin_bf16_e64 v5, -1
v_cos_bf16_e64 v5, v1
// GFX1250: v_cos_bf16_e64 v5, v1 ; encoding: [0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x02]
+v_cos_bf16_e64 v5, v1 clamp
+// GFX1250: v_cos_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+
v_cos_bf16_e64 v5, v255
// GFX1250: v_cos_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xff,0xd5,0xff,0x01,0x01,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
index d1bc282cc82ea..e31a644345d70 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
@@ -3919,6 +3919,9 @@ v_tanh_f16 v5.l, v128.h
v_tanh_bf16_e64 v5.l, v1.l
// GFX1250: v_tanh_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x02]
+v_tanh_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_tanh_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+
v_tanh_bf16_e64 v5.l, v255.l
// GFX1250: v_tanh_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xca,0xd5,0xff,0x01,0x01,0x02]
@@ -3994,6 +3997,9 @@ v_prng_b32_e64 v5, -1
v_rcp_bf16_e64 v5.l, v1.l
// GFX1250: v_rcp_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x02]
+v_rcp_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_rcp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+
v_rcp_bf16_e64 v5.l, v255.l
// GFX1250: v_rcp_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xf9,0xd5,0xff,0x01,0x01,0x02]
@@ -4033,6 +4039,9 @@ v_rcp_bf16 v5.h, v128.h
v_sqrt_bf16_e64 v5.l, v1.l
// GFX1250: v_sqrt_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x02]
+v_sqrt_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_sqrt_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+
v_sqrt_bf16_e64 v5.l, v255.l
// GFX1250: v_sqrt_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfa,0xd5,0xff,0x01,0x01,0x02]
@@ -4072,6 +4081,9 @@ v_sqrt_bf16 v5.h, v128.h
v_rsq_bf16_e64 v5.l, v1.l
// GFX1250: v_rsq_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x02]
+v_rsq_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_rsq_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+
v_rsq_bf16_e64 v5.l, v255.l
// GFX1250: v_rsq_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfb,0xd5,0xff,0x01,0x01,0x02]
@@ -4111,6 +4123,9 @@ v_rsq_bf16 v5.h, v128.h
v_log_bf16_e64 v5.l, v1.l
// GFX1250: v_log_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x02]
+v_log_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_log_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+
v_log_bf16_e64 v5.l, v255.l
// GFX1250: v_log_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfc,0xd5,0xff,0x01,0x01,0x02]
@@ -4150,6 +4165,9 @@ v_log_bf16 v5.h, v128.h
v_exp_bf16_e64 v5.l, v1.l
// GFX1250: v_exp_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x02]
+v_exp_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_exp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+
v_exp_bf16_e64 v5.l, v255.l
// GFX1250: v_exp_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfd,0xd5,0xff,0x01,0x01,0x02]
@@ -4189,6 +4207,9 @@ v_exp_bf16 v5.h, v128.h
v_sin_bf16_e64 v5.l, v1.l
// GFX1250: v_sin_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x02]
+v_sin_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_sin_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+
v_sin_bf16_e64 v5.l, v255.l
// GFX1250: v_sin_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfe,0xd5,0xff,0x01,0x01,0x02]
@@ -4228,6 +4249,9 @@ v_sin_bf16 v5.h, v128.h
v_cos_bf16_e64 v5.l, v1.l
// GFX1250: v_cos_bf16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x02]
+v_cos_bf16_e64 v5.l, v1.l clamp
+// GFX1250: v_cos_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+
v_cos_bf16_e64 v5.l, v255.l
// GFX1250: v_cos_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xff,0xd5,0xff,0x01,0x01,0x02]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
index 1b0e9997bcc76..73a38bfcce68d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
@@ -4130,6 +4130,10 @@
# GFX1250-FAKE16: v_tanh_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xca,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xca,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_tanh_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xca,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xca,0xd5,0x7f,0x00,0x01,0x02]
@@ -4218,6 +4222,10 @@
# GFX1250-FAKE16: v_rcp_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xf9,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_rcp_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xf9,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_rcp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_rcp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xf9,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_rcp_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xf9,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_rcp_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xf9,0xd5,0x7f,0x00,0x01,0x02]
@@ -4270,6 +4278,10 @@
# GFX1250-FAKE16: v_sqrt_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xfa,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_sqrt_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xfa,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_sqrt_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_sqrt_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xfa,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_sqrt_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfa,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_sqrt_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfa,0xd5,0x7f,0x00,0x01,0x02]
@@ -4322,6 +4334,10 @@
# GFX1250-FAKE16: v_rsq_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xfb,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_rsq_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xfb,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_rsq_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_rsq_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xfb,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_rsq_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfb,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_rsq_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfb,0xd5,0x7f,0x00,0x01,0x02]
@@ -4374,6 +4390,10 @@
# GFX1250-FAKE16: v_log_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xfc,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_log_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xfc,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_log_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_log_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xfc,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_log_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfc,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_log_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfc,0xd5,0x7f,0x00,0x01,0x02]
@@ -4426,6 +4446,10 @@
# GFX1250-FAKE16: v_exp_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xfd,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_exp_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xfd,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_exp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_exp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xfd,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_exp_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfd,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_exp_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfd,0xd5,0x7f,0x00,0x01,0x02]
@@ -4478,6 +4502,10 @@
# GFX1250-FAKE16: v_sin_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xfe,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_sin_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xfe,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_sin_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_sin_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xfe,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_sin_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfe,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_sin_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfe,0xd5,0x7f,0x00,0x01,0x02]
@@ -4530,6 +4558,10 @@
# GFX1250-FAKE16: v_cos_bf16_e64 v5, -1 ; encoding: [0x05,0x00,0xff,0xd5,0xc1,0x00,0x01,0x02]
# GFX1250-REAL16: v_cos_bf16_e64 v5.l, -1 ; encoding: [0x05,0x00,0xff,0xd5,0xc1,0x00,0x01,0x02]
+0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02
+# GFX1250-FAKE16: v_cos_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+# GFX1250-REAL16: v_cos_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+
0x05,0x00,0xff,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_cos_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xff,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_cos_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xff,0xd5,0x7f,0x00,0x01,0x02]
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