[llvm] 3397635 - [AMDGPU] Add gfx1251 V_PK_MUL_F64 (#203410)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 15:47:00 PDT 2026
Author: Stanislav Mekhanoshin
Date: 2026-06-11T15:46:56-07:00
New Revision: 3397635cb50abdc9413246a3810f7d1701211f0b
URL: https://github.com/llvm/llvm-project/commit/3397635cb50abdc9413246a3810f7d1701211f0b
DIFF: https://github.com/llvm/llvm-project/commit/3397635cb50abdc9413246a3810f7d1701211f0b.diff
LOG: [AMDGPU] Add gfx1251 V_PK_MUL_F64 (#203410)
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
llvm/test/CodeGen/AMDGPU/packed-fp64.ll
llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
llvm/test/MC/AMDGPU/gfx1251_err.s
llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 76934dc6ec5d9..269f694b20b6b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -905,8 +905,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
Custom);
}
if (Subtarget->hasPackedFP64Ops()) {
- setOperationAction(ISD::FADD, MVT::v2f64, Legal);
- setOperationAction(ISD::FADD,
+ setOperationAction({ISD::FADD, ISD::FMUL}, MVT::v2f64, Legal);
+ setOperationAction({ISD::FADD, ISD::FMUL},
{MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64},
Custom);
}
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index f8ceb047b8f21..18a3fd761e173 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -3814,6 +3814,8 @@ bool isPacked64BitInst(unsigned Opc) {
switch (Opc) {
case AMDGPU::V_PK_ADD_F64:
case AMDGPU::V_PK_ADD_F64_gfx1250:
+ case AMDGPU::V_PK_MUL_F64:
+ case AMDGPU::V_PK_MUL_F64_gfx1250:
return true;
default:
return false;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 6948e216eb3ad..cdd483426fc78 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -1392,6 +1392,7 @@ let isCommutable = 1, isReMaterializable = 1 in {
}
let SubtargetPredicate = HasPackedFP64Ops, SchedRW = [WriteDouble] in {
+ defm V_PK_MUL_F64 : VOP3PInst<"v_pk_mul_f64", V_PK_VOP2_F64_Profile, any_fmul>;
defm V_PK_ADD_F64 : VOP3PInst<"v_pk_add_f64", V_PK_VOP2_F64_Profile, any_fadd>;
} // End SubtargetPredicate = HasPackedFP64Ops, SchedRW = [WriteDouble]
} // End isCommutable = 1, isReMaterializable = 1
@@ -2692,6 +2693,7 @@ let PostEncoderMethod = "postEncodeVOP3<true, true, false>" in {
defm V_WMMA_LD_SCALE16_PAIRED_B64 : VOP3P_Real_gfx1250<0x3a>;
}
+defm V_PK_MUL_F64 : VOP3P_Real_gfx1250<0x3c>;
defm V_PK_ADD_F64 : VOP3P_Real_gfx1250<0x4b>;
let AssemblerPredicate = isGFX1250Plus in
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
index d23f98e1acdc4..998342ac113e3 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
@@ -854,3 +854,598 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, double %x, do
store <2 x double> %add, ptr addrspace(1) %gep, align 8
ret void
}
+
+define amdgpu_kernel void @fmul_v2_vv(ptr addrspace(1) %a) {
+; GFX1251-LABEL: fmul_v2_vv:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-NEXT: v_and_b32_e32 v4, 0x3ff, v0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: global_load_b128 v[0:3], v4, s[0:1] scale_offset
+; GFX1251-NEXT: s_wait_loadcnt 0x0
+; GFX1251-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[0:3]
+; GFX1251-NEXT: global_store_b128 v4, v[0:3], s[0:1] scale_offset
+; GFX1251-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %mul = fmul <2 x double> %load, %load
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_vs(ptr addrspace(1) %a, <2 x double> %x) {
+; GFX1251-LABEL: fmul_v2_vs:
+; GFX1251: ; %bb.0:
+; GFX1251-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-NEXT: s_clause 0x1
+; GFX1251-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX1251-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-NEXT: s_wait_kmcnt 0x0
+; GFX1251-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-NEXT: s_wait_loadcnt 0x0
+; GFX1251-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %mul = fmul <2 x double> %load, %x
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x double> %y) {
+; GFX1251-SDAG-LABEL: fmul_v2_ss:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX1251-SDAG-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v2_ss:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: s_endpgm
+ %mul = fmul <2 x double> %x, %y
+ store <2 x double> %mul, ptr addrspace(1) %a, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v4_vs(ptr addrspace(1) %a, <4 x double> %x) {
+; GFX1251-SDAG-LABEL: fmul_v4_vs:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x44 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_lshlrev_b32 v16, 5, v0 :: v_dual_mov_b32 v8, s12
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v16, s[0:1]
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v16, s[0:1] offset:16
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v11, s15
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x1
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[12:15]
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[4:7], v[4:7], v[8:11]
+; GFX1251-SDAG-NEXT: s_clause 0x1
+; GFX1251-SDAG-NEXT: global_store_b128 v16, v[0:3], s[0:1]
+; GFX1251-SDAG-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v4_vs:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x44 nv
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_lshlrev_b32_e32 v16, 5, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v16, s[0:1]
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v16, s[0:1] offset:16
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[8:11]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[4:7], v[4:7], v[12:15]
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: global_store_b128 v16, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <4 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <4 x double>, ptr addrspace(1) %gep, align 16
+ %mul = fmul <4 x double> %load, %x
+ store <4 x double> %mul, ptr addrspace(1) %gep, align 16
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v32_vs(ptr addrspace(1) %a, <32 x double> %x) {
+; GFX1251-SDAG-LABEL: fmul_v32_vs:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_clause 0x4
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[68:83], s[4:5], 0x1a4 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[52:67], s[4:5], 0x1e4 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x124 nv
+; GFX1251-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0x164 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_lshlrev_b32 v44, 8, v0 :: v_dual_mov_b32 v66, s72
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v67, s73 :: v_dual_mov_b32 v68, s74
+; GFX1251-SDAG-NEXT: s_clause 0xf
+; GFX1251-SDAG-NEXT: global_load_b128 v[40:43], v44, s[0:1] offset:144
+; GFX1251-SDAG-NEXT: global_load_b128 v[36:39], v44, s[0:1] offset:128
+; GFX1251-SDAG-NEXT: global_load_b128 v[32:35], v44, s[0:1] offset:176
+; GFX1251-SDAG-NEXT: global_load_b128 v[28:31], v44, s[0:1] offset:160
+; GFX1251-SDAG-NEXT: global_load_b128 v[24:27], v44, s[0:1] offset:208
+; GFX1251-SDAG-NEXT: global_load_b128 v[20:23], v44, s[0:1] offset:192
+; GFX1251-SDAG-NEXT: global_load_b128 v[16:19], v44, s[0:1] offset:240
+; GFX1251-SDAG-NEXT: global_load_b128 v[12:15], v44, s[0:1] offset:224
+; GFX1251-SDAG-NEXT: global_load_b128 v[8:11], v44, s[0:1] offset:16
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v44, s[0:1]
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v44, s[0:1] offset:80
+; GFX1251-SDAG-NEXT: global_load_b128 v[46:49], v44, s[0:1] offset:64
+; GFX1251-SDAG-NEXT: global_load_b128 v[50:53], v44, s[0:1] offset:112
+; GFX1251-SDAG-NEXT: global_load_b128 v[54:57], v44, s[0:1] offset:96
+; GFX1251-SDAG-NEXT: global_load_b128 v[58:61], v44, s[0:1] offset:32
+; GFX1251-SDAG-NEXT: global_load_b128 v[62:65], v44, s[0:1] offset:48
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v69, s75 :: v_dual_mov_b32 v70, s68
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v71, s69 :: v_dual_mov_b32 v72, s70
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v73, s71
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xf
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[40:43], v[40:43], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s80 :: v_dual_mov_b32 v67, s81
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s82 :: v_dual_mov_b32 v69, s83
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xe
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[36:39], v[36:39], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s76 :: v_dual_mov_b32 v71, s77
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s78 :: v_dual_mov_b32 v73, s79
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xd
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[32:35], v[32:35], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s56 :: v_dual_mov_b32 v67, s57
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s58 :: v_dual_mov_b32 v69, s59
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xc
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[28:31], v[28:31], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s52 :: v_dual_mov_b32 v71, s53
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s54 :: v_dual_mov_b32 v73, s55
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xb
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[24:27], v[24:27], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s64 :: v_dual_mov_b32 v67, s65
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s66 :: v_dual_mov_b32 v69, s67
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0xa
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[20:23], v[20:23], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s60 :: v_dual_mov_b32 v71, s61
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s62 :: v_dual_mov_b32 v73, s63
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x9
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[16:19], v[16:19], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s12 :: v_dual_mov_b32 v67, s13
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s14 :: v_dual_mov_b32 v69, s15
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x8
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[12:15], v[12:15], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s8 :: v_dual_mov_b32 v71, s9
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s10 :: v_dual_mov_b32 v73, s11
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x7
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[8:11], v[8:11], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s40 :: v_dual_mov_b32 v67, s41
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s42 :: v_dual_mov_b32 v69, s43
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x6
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[4:7], v[4:7], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s36 :: v_dual_mov_b32 v71, s37
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s38 :: v_dual_mov_b32 v73, s39
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x5
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s48 :: v_dual_mov_b32 v67, s49
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s50 :: v_dual_mov_b32 v69, s51
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x4
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[46:49], v[46:49], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s44 :: v_dual_mov_b32 v71, s45
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s46 :: v_dual_mov_b32 v73, s47
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x3
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[50:53], v[50:53], v[66:69]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v66, s16 :: v_dual_mov_b32 v67, s17
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v68, s18 :: v_dual_mov_b32 v69, s19
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x2
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[54:57], v[54:57], v[70:73]
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v70, s20 :: v_dual_mov_b32 v71, s21
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v72, s22 :: v_dual_mov_b32 v73, s23
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x1
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[58:61], v[58:61], v[66:69]
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[62:65], v[62:65], v[70:73]
+; GFX1251-SDAG-NEXT: s_clause 0xf
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[54:57], s[0:1] offset:96
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[50:53], s[0:1] offset:112
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[46:49], s[0:1] offset:64
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[0:3], s[0:1] offset:80
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[58:61], s[0:1] offset:32
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[62:65], s[0:1] offset:48
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[4:7], s[0:1]
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[8:11], s[0:1] offset:16
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[12:15], s[0:1] offset:224
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[16:19], s[0:1] offset:240
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[20:23], s[0:1] offset:192
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[24:27], s[0:1] offset:208
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[28:31], s[0:1] offset:160
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[32:35], s[0:1] offset:176
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[36:39], s[0:1] offset:128
+; GFX1251-SDAG-NEXT: global_store_b128 v44, v[40:43], s[0:1] offset:144
+; GFX1251-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v32_vs:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_clause 0x1
+; GFX1251-GISEL-NEXT: s_load_b512 s[16:31], s[4:5], 0x124 nv
+; GFX1251-GISEL-NEXT: s_load_b512 s[44:59], s[4:5], 0x164 nv
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_lshlrev_b32_e32 v72, 8, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: s_clause 0xf
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v72, s[0:1]
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v72, s[0:1] offset:16
+; GFX1251-GISEL-NEXT: global_load_b128 v[8:11], v72, s[0:1] offset:32
+; GFX1251-GISEL-NEXT: global_load_b128 v[12:15], v72, s[0:1] offset:48
+; GFX1251-GISEL-NEXT: global_load_b128 v[16:19], v72, s[0:1] offset:64
+; GFX1251-GISEL-NEXT: global_load_b128 v[20:23], v72, s[0:1] offset:80
+; GFX1251-GISEL-NEXT: global_load_b128 v[24:27], v72, s[0:1] offset:96
+; GFX1251-GISEL-NEXT: global_load_b128 v[28:31], v72, s[0:1] offset:112
+; GFX1251-GISEL-NEXT: global_load_b128 v[32:35], v72, s[0:1] offset:128
+; GFX1251-GISEL-NEXT: global_load_b128 v[36:39], v72, s[0:1] offset:144
+; GFX1251-GISEL-NEXT: global_load_b128 v[40:43], v72, s[0:1] offset:160
+; GFX1251-GISEL-NEXT: global_load_b128 v[44:47], v72, s[0:1] offset:176
+; GFX1251-GISEL-NEXT: global_load_b128 v[48:51], v72, s[0:1] offset:192
+; GFX1251-GISEL-NEXT: global_load_b128 v[52:55], v72, s[0:1] offset:208
+; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
+; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
+; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[4:7], v[4:7], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[8:11], v[8:11], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[12:15], v[12:15], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
+; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[16:19], v[16:19], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[20:23], v[20:23], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[24:27], v[24:27], v[64:67]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[28:31], v[28:31], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[32:35], v[32:35], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[36:39], v[36:39], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[40:43], v[40:43], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[44:47], v[44:47], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[48:51], v[48:51], v[64:67]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[52:55], v[52:55], v[68:71]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[56:59], v[56:59], v[64:67]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[60:63], v[60:63], v[68:71]
+; GFX1251-GISEL-NEXT: s_clause 0xf
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[4:7], s[0:1] offset:16
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[8:11], s[0:1] offset:32
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[12:15], s[0:1] offset:48
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[16:19], s[0:1] offset:64
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[20:23], s[0:1] offset:80
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[24:27], s[0:1] offset:96
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[28:31], s[0:1] offset:112
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[32:35], s[0:1] offset:128
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[36:39], s[0:1] offset:144
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[40:43], s[0:1] offset:160
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[44:47], s[0:1] offset:176
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[48:51], s[0:1] offset:192
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[52:55], s[0:1] offset:208
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[56:59], s[0:1] offset:224
+; GFX1251-GISEL-NEXT: global_store_b128 v72, v[60:63], s[0:1] offset:240
+; GFX1251-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <32 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <32 x double>, ptr addrspace(1) %gep, align 128
+ %mul = fmul <32 x double> %load, %x
+ store <32 x double> %mul, ptr addrspace(1) %gep, align 128
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_v_imm(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: fmul_v2_v_imm:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40590000
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v2_v_imm:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0x4059000000000000
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %mul = fmul <2 x double> %load, <double 100.0, double 100.0>
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_v_v_splat(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: fmul_v2_v_v_splat:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v0
+; GFX1251-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[4:7], v0, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[2:5], v[4:7], v[0:3]
+; GFX1251-SDAG-NEXT: global_store_b128 v0, v[2:5], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v2_v_v_splat:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1251-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[4:7], v0, s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[2:5], v[4:7], v[0:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v0, v[2:5], s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %id.1 = zext i32 %id to i64
+ %fid = bitcast i64 %id.1 to double
+ %tmp1 = insertelement <2 x double> poison, double %fid, i64 0
+ %k = insertelement <2 x double> %tmp1, double %fid, i64 1
+ %mul = fmul <2 x double> %load, %k
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_v_lit_splat(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: fmul_v2_v_lit_splat:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40100000
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v5
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v2_v_lit_splat:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 4.0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %mul = fmul <2 x double> %load, <double 4.0, double 4.0>
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_v_unfoldable_lit(ptr addrspace(1) %a) {
+; GFX1251-SDAG-LABEL: fmul_v2_v_unfoldable_lit:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40100000
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v7, 0x40080000 :: v_dual_mov_b32 v6, v4
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v2_v_unfoldable_lit:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 0x4008000000000000
+; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 4.0
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[6:7] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %mul = fmul <2 x double> %load, <double 4.0, double 3.0>
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+define amdgpu_kernel void @fmul_v2_v_fneg(ptr addrspace(1) %a, double %x) {
+; GFX1251-SDAG-LABEL: fmul_v2_v_fneg:
+; GFX1251-SDAG: ; %bb.0:
+; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1251-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1251-SDAG-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_xor_b32 s3, s3, 0x80000000
+; GFX1251-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1251-SDAG-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3
+; GFX1251-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1251-SDAG-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-SDAG-NEXT: s_endpgm
+;
+; GFX1251-GISEL-LABEL: fmul_v2_v_fneg:
+; GFX1251-GISEL: ; %bb.0:
+; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1251-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
+; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: v_max_num_f64_e64 v[4:5], -s[2:3], -s[2:3]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
+; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
+; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
+; GFX1251-GISEL-NEXT: s_endpgm
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x double>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x double>, ptr addrspace(1) %gep, align 8
+ %fneg = fsub double -0.0, %x
+ %tmp1 = insertelement <2 x double> poison, double %fneg, i64 0
+ %k = insertelement <2 x double> %tmp1, double %fneg, i64 1
+ %mul = fmul <2 x double> %load, %k
+ store <2 x double> %mul, ptr addrspace(1) %gep, align 8
+ ret void
+}
diff --git a/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
index 8a0b645ce9c21..63d33122067b3 100644
--- a/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
+++ b/llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
@@ -49,3 +49,51 @@ v_pk_add_f64 v[4:7], 101.0, v[8:11]
v_pk_add_f64 v[4:7], v[8:11], 101.0
// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
// GFX1251: v_pk_add_f64 v[4:7], v[8:11], 0x40594000 ; encoding: [0x04,0x40,0x4b,0xcc,0x08,0xff,0x01,0x1a,0x00,0x40,0x59,0x40]
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x19,0x02,0x1a]
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x04,0x41,0x3c,0xcc,0x08,0x19,0x02,0x3a]
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x04,0x42,0x3c,0xcc,0x08,0x19,0x02,0x5a]
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] clamp
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] clamp ; encoding: [0x04,0xc0,0x3c,0xcc,0x08,0x19,0x02,0x1a]
+
+v_pk_mul_f64 v[4:7], s[8:11], s[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], s[8:11], s[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x18,0x00,0x1a]
+
+v_pk_mul_f64 v[4:7], v[8:11], s[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], s[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x19,0x00,0x1a]
+
+v_pk_mul_f64 v[4:7], s[8:11], v[12:15]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], s[8:11], v[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x18,0x02,0x1a]
+
+v_pk_mul_f64 v[4:7], v[8:11], null
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], null ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0xf9,0x00,0x1a]
+
+v_pk_mul_f64 v[4:7], v[8:11], 1.0
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], 1.0 ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0xe5,0x01,0x1a]
+
+v_pk_mul_f64 v[4:7], 1.0, v[8:11]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], 1.0, v[8:11] ; encoding: [0x04,0x40,0x3c,0xcc,0xf2,0x10,0x02,0x1a]
+
+v_pk_mul_f64 v[4:7], 101.0, v[8:11]
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], 0x40594000, v[8:11] ; encoding: [0x04,0x40,0x3c,0xcc,0xff,0x10,0x02,0x1a,0x00,0x40,0x59,0x40]
+
+v_pk_mul_f64 v[4:7], v[8:11], 101.0
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// GFX1251: v_pk_mul_f64 v[4:7], v[8:11], 0x40594000 ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0xff,0x01,0x1a,0x00,0x40,0x59,0x40]
diff --git a/llvm/test/MC/AMDGPU/gfx1251_err.s b/llvm/test/MC/AMDGPU/gfx1251_err.s
index ece1ff2e0b1a0..541cf0740c975 100644
--- a/llvm/test/MC/AMDGPU/gfx1251_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1251_err.s
@@ -43,3 +43,42 @@ v_pk_add_f64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
v_pk_add_f64 v[4:7], v[5:8], null
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
// GFX1251-ERR: v_pk_add_f64 v[4:7], v[5:8], null
+
+v_pk_mul_f64 v[4:7], |v[8:11]|, v[12:15]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], |v[8:11]|, v[12:15]
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] mul:2
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] mul:2
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] row_share:2
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] row_share:2
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], lit64(0x12345678a), v[8:11]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], lit64(0x12345678a), v[8:11]
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], v[8:11], lit64(0x12345678a)
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], v[8:11], lit64(0x12345678a)
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] op_sel:[1,0]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] op_sel:[1,0]
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] op_sel_hi:[1,0]
+// GFX1251-ERR: ^
+
+v_pk_mul_f64 v[4:7], v[5:8], null
+// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
+// GFX1251-ERR: v_pk_mul_f64 v[4:7], v[5:8], null
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
index e8d7048ebb6bd..17f8df56b0194 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
@@ -36,3 +36,39 @@
0x04,0x40,0x4b,0xcc,0x08,0xff,0x01,0x18,0x00,0x40,0x59,0x40
# GFX1251: v_pk_add_f64 v[4:7], v[8:11], 0x40594000 ; encoding: [0x04,0x40,0x4b,0xcc,0x08,0xff,0x01,0x1a,0x00,0x40,0x59,0x40]
+
+0x04,0x40,0x3c,0xcc,0x08,0x19,0x02,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x19,0x02,0x1a]
+
+0x04,0x41,0x3c,0xcc,0x08,0x19,0x02,0x38
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x04,0x41,0x3c,0xcc,0x08,0x19,0x02,0x3a]
+
+0x04,0x42,0x3c,0xcc,0x08,0x19,0x02,0x58
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x04,0x42,0x3c,0xcc,0x08,0x19,0x02,0x5a]
+
+0x04,0xc0,0x3c,0xcc,0x08,0x19,0x02,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], v[12:15] clamp ; encoding: [0x04,0xc0,0x3c,0xcc,0x08,0x19,0x02,0x1a]
+
+0x04,0x40,0x3c,0xcc,0x08,0x18,0x00,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], s[8:11], s[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x18,0x00,0x1a]
+
+0x04,0x40,0x3c,0xcc,0x08,0x19,0x00,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], s[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x19,0x00,0x1a]
+
+0x04,0x40,0x3c,0xcc,0x08,0x18,0x02,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], s[8:11], v[12:15] ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0x18,0x02,0x1a]
+
+0x04,0x40,0x3c,0xcc,0x08,0xf9,0x00,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], null ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0xf9,0x00,0x1a]
+
+0x04,0x40,0x3c,0xcc,0x08,0xe5,0x01,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], 1.0 ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0xe5,0x01,0x1a]
+
+0x04,0x40,0x3c,0xcc,0xf2,0x10,0x02,0x18
+# GFX1251: v_pk_mul_f64 v[4:7], 1.0, v[8:11] ; encoding: [0x04,0x40,0x3c,0xcc,0xf2,0x10,0x02,0x1a]
+
+0x04,0x40,0x3c,0xcc,0xff,0x10,0x02,0x18,0x00,0x40,0x59,0x40
+# GFX1251: v_pk_mul_f64 v[4:7], 0x40594000, v[8:11] ; encoding: [0x04,0x40,0x3c,0xcc,0xff,0x10,0x02,0x1a,0x00,0x40,0x59,0x40]
+
+0x04,0x40,0x3c,0xcc,0x08,0xff,0x01,0x18,0x00,0x40,0x59,0x40
+# GFX1251: v_pk_mul_f64 v[4:7], v[8:11], 0x40594000 ; encoding: [0x04,0x40,0x3c,0xcc,0x08,0xff,0x01,0x1a,0x00,0x40,0x59,0x40]
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