[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)
Nashe Mncube via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 08:59:41 PDT 2026
================
@@ -1959,131 +2548,147 @@ def : InstRW<[C1UWrite_2c_1V0], (instregex "^N?MATCH_PPzZZ_[BH]")>;
def : InstRW<[C1UWr_ZMMA, C1URd_ZMMA, C1URd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
// Move prefix
-def : InstRW<[C1UWrite_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",
- "^MOVPRFX_ZZ")>;
+def : InstRW<[C1UWrite_2c_1V_CMEVXALU], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",
+ "^MOVPRFX_ZZ")>;
// Multiply
-def : InstRW<[C1UWrite_4c_1V0134], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHSD]",
- "^MUL_ZPZZ_[BHSD]",
- "^[SU]MULH_(ZPmZ|ZZZ)_[BHSD]",
- "^[SU]MULH_ZPZZ_[BHSD]")>;
+def : InstRW<[C1UWrite_4c_1V0134_CMEVXMUL],
+ (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHSD]",
+ "^MUL_ZPZZ_[BHSD]",
+ "^[SU]MULH_(ZPmZ|ZZZ)_[BHSD]",
+ "^[SU]MULH_ZPZZ_[BHSD]")>;
// Multiply long
-def : InstRW<[C1UWrite_4c_1V0134], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",
- "^[SU]MULL[BT]_ZZZ_[HSD]")>;
+def : InstRW<[C1UWrite_4c_1V0134_CMEVXMUL],
+ (instregex "^[SU]MULL[BT]_ZZZI_[SD]",
+ "^[SU]MULL[BT]_ZZZ_[HSD]")>;
// Multiply accumulate, B, H, S element size
-def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+def : InstRW<[C1UWr_ZMA_CME, ReadDefault, C1URd_ZMA, C1URd_ZMA],
(instregex "^ML[AS]_ZZZI_[HS]", "^ML[AS]_ZPZZZ_[BHS]")>;
-def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+def : InstRW<[C1UWr_ZMA_CME, ReadDefault, C1URd_ZMA, C1URd_ZMA],
(instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;
// Multiply accumulate, D element size
-def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+def : InstRW<[C1UWr_ZMA_CME, ReadDefault, C1URd_ZMA, C1URd_ZMA],
(instregex "^ML[AS]_ZZZI_D", "^ML[AS]_ZPZZZ_D")>;
-def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+def : InstRW<[C1UWr_ZMA_CME, ReadDefault, C1URd_ZMA, C1URd_ZMA],
(instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;
// Multiply accumulate long
-def : InstRW<[C1UWr_ZMA, C1URd_ZMA, C1URd_ZMA], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",
+def : InstRW<[C1UWr_ZMA_CME, C1URd_ZMA, C1URd_ZMA], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",
"^[SU]ML[AS]L[BT]_ZZZI_[SD]")>;
// Multiply accumulate saturating doubling long regular
-def : InstRW<[C1UWr_ZMASQL, C1URd_ZMASQL, C1URd_ZMASQL],
+def : InstRW<[C1UWr_ZMASQL_CME, C1URd_ZMASQL, C1URd_ZMASQL],
(instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]",
"^SQDML[AS]L[BT]_ZZZI_[SD]")>;
// Multiply saturating doubling high
-def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQDMULH_ZZZ_[BHSD]",
- "^SQDMULH_ZZZI_[HSD]")>;
+def : InstRW<[C1UWrite_4c_1V0134_CMEVXMUL],
+ (instregex "^SQDMULH_ZZZ_[BHSD]",
+ "^SQDMULH_ZZZI_[HSD]")>;
// Multiply saturating doubling long
-def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",
- "^SQDMULL[BT]_ZZZI_[SD]")>;
+def : InstRW<[C1UWrite_4c_1V0134_CMEVXMUL],
+ (instregex "^SQDMULL[BT]_ZZZ_[HSD]",
+ "^SQDMULL[BT]_ZZZI_[SD]")>;
// Multiply saturating rounding doubling regular/complex accumulate
-def : InstRW<[C1UWr_ZMASQL, C1URd_ZMASQL, C1URd_ZMASQL], (instregex "^SQRDML[AS]H_ZZZ_[BHSD]",
+def : InstRW<[C1UWr_ZMASQL_CME, C1URd_ZMASQL, C1URd_ZMASQL], (instregex "^SQRDML[AS]H_ZZZ_[BHSD]",
"^SQRDCMLAH_ZZZ_[BHSD]",
"^SQRDML[AS]H_ZZZI_[HSD]",
"^SQRDCMLAH_ZZZI_[HSD]")>;
// Multiply saturating rounding doubling regular/complex, B, H, S element size
-def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQRDMULH_ZZZ_[BHS]",
- "^SQRDMULH_ZZZI_[HS]",
- "^SQRDMULH_ZZZI?_D")>;
+def : InstRW<[C1UWrite_4c_1V0134_CMEVXMUL],
+ (instregex "^SQRDMULH_ZZZ_[BHS]",
+ "^SQRDMULH_ZZZI_[HS]",
+ "^SQRDMULH_ZZZI?_D")>;
// Multiply/multiply long, (8x8) polynomial
def : InstRW<[C1UWrite_2c_1V0134], (instregex "^PMUL_ZZZ_B",
- "^PMULL[BT]_ZZZ_[HDQ]")>;
+ "^PMULL[BT]_ZZZ_[HDQ]")>;
// Predicate counting vector
-def : InstRW<[C1UWrite_2c_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;
+def : InstRW<[C1UWrite_2c_1V_CME], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;
// Reciprocal estimate
-def : InstRW<[C1UWrite_4c_1V0134], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
+def : InstRW<[C1UWrite_4c_1V0134_CMEVXMUL],
+ (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
// Reduction, arithmetic, B form
-def : InstRW<[C1UWrite_8c_1V_3V0134], (instregex "^[SU]ADDV_VPZ_B")>;
-def : InstRW<[C1UWrite_6c_1V_2V0134], (instregex "^[SU](MAX|MIN)V_VPZ_B")>;
+def : InstRW<[C1UWrite_8c_1V_3V0134_CMEIntReduce],
+ (instregex "^[SU]ADDV_VPZ_B")>;
+def : InstRW<[C1UWrite_6c_1V_2V0134_CMEIntReduce],
+ (instregex "^[SU](MAX|MIN)V_VPZ_B")>;
// // Reduction, arithmetic, H form
-def : InstRW<[C1UWrite_6c_1V_2V0134], (instregex "^[SU]ADDV_VPZ_H")>;
-def : InstRW<[C1UWrite_6c_2V_1V0134], (instregex "^[SU](MAX|MIN)V_VPZ_H")>;
+def : InstRW<[C1UWrite_6c_1V_2V0134_CMEIntReduce],
+ (instregex "^[SU]ADDV_VPZ_H")>;
+def : InstRW<[C1UWrite_6c_2V_1V0134_CMEIntReduce],
+ (instregex "^[SU](MAX|MIN)V_VPZ_H")>;
// Reduction, arithmetic, S form
-def : InstRW<[C1UWrite_6c_2V_1V0134], (instregex "^[SU]ADDV_VPZ_S")>;
-def : InstRW<[C1UWrite_4c_1V_1V0134], (instregex "^[SU](MAX|MIN)V_VPZ_S")>;
+def : InstRW<[C1UWrite_6c_2V_1V0134_CMEIntReduce],
+ (instregex "^[SU]ADDV_VPZ_S")>;
+def : InstRW<[C1UWrite_4c_1V_1V0134_CMEIntReduce],
+ (instregex "^[SU](MAX|MIN)V_VPZ_S")>;
// Reduction, arithmetic, D form
-def : InstRW<[C1UWrite_4c_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
+def : InstRW<[C1UWrite_4c_2V_CMEIntReduce],
+ (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
// Reduction, logical
-def : InstRW<[C1UWrite_4c_1V_1V0134], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;
+def : InstRW<[C1UWrite_4c_1V_1V0134_CMEIntReduce],
+ (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;
// Reverse, vector
-def : InstRW<[C1UWrite_2c_1V], (instregex "^REV_ZZ_[BHSD]",
- "^REVB_ZPmZ_[HSD]",
- "^REVH_ZPmZ_[SD]",
- "^REVW_ZPmZ_D")>;
+def : InstRW<[C1UWrite_2c_1V_StreamingCMEPERMS], (instregex "^REV_ZZ_[BHSD]",
+ "^REVB_ZPmZ_[HSD]",
+ "^REVH_ZPmZ_[SD]",
+ "^REVW_ZPmZ_D")>;
----------------
nasherm wrote:
Added
https://github.com/llvm/llvm-project/pull/194850
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