[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)

[Nashe Mncube via llvm-commits]

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@@ -2454,14 +3068,222 @@ def : InstRW<[C1UWrite_4c_1L], (instregex "^PRF[BHWD]")>;
 
 // Crypto AES ops
 def : InstRW<[C1UWrite_2c_1V0134], (instregex "^AES[DE]_ZZZ_B$",
-                                         "^AESI?MC_ZZ_B$")>;
+                                     "^AESI?MC_ZZ_B$")>;
 
 // Crypto SHA3 ops
 def : InstRW<[C1UWrite_2c_1V], (instregex "^(BCAX|EOR3)_ZZZZ$",
-                                         "^RAX1_ZZZ_D$",
-                                         "^XAR_ZZZI_[BHSD]$")>;
+                                 "^RAX1_ZZZ_D$",
+                                 "^XAR_ZZZI_[BHSD]$")>;
 
 // Crypto SM4 ops
 def : InstRW<[C1UWrite_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
 
+// SVE instructions added by SME and available when not in Streaming SVE mode
+// -----------------------------------------------------------------------------
+// BFloat16 floating-point multiply-subtract long from single-precision vector and indexed form
+def : InstRW<[C1UWrite_4c_1V_StreamingCMEMML0], (instregex "^BFMLSLB_",
+                                                           "^BFMLSLT_")>;
+
+// Floating-point clamp to minimum/maximu m number
+def : InstRW<[C1UWrite_2c_1V_StreamingCMEVXALU_5c], (instregex "^FCLAMP_ZZZ")>;
+
+// Half-precision floating-point indexed or vector forms dot product
+def : InstRW<[C1UWrite_4c_1V_StreamingCMEMML0], (instregex "^FDOT_ZZZI?_S$")>;
+
+// Predicate selection
+def : InstRW<[C1UWrite_2c_2M_StreamingCMEPERMS], (instregex "^PSEL_PPPRI")>;
+
+// Reverse doubleword elements
+def : InstRW<[C1UWrite_2c_1V_StreamingCMEPERMS], (instregex "^REVD_ZPmZ")>;
+
+// Signed/unsigned clamp
+def : InstRW<[C1UWrite_2c_1V_StreamingCME], (instregex "^(S|U)CLAMP_ZZZ")>;
+
+// Half-precision signed/unsigned dot product vector and indexed forms
+def : InstRW<[C1UWrite_3c_1V01_StreamingCME], (instregex "^(S|U)DOT_ZZZI?_HtoS")>;
+
+// Signed/unsigned saturating narrow conversion
+def : InstRW<[C1UWrite_2c_1V_StreamingCMEVXALU_PERMS],
+             (instregex "^(SQCVTN|SQCVTUN|UQCVTN)_Z2Z_StoH")>;
+
+// Signed/unsigned saturating rounding shift-right narrow
+def : InstRW<[C1UWrite_3c_1V01_StreamingCME], (instregex "^(SQRSHRN|SQRSHRUN|UQRSHRN)_Z2ZI_StoH")>;
+
+// Signed/unsigned pair-producing while compare
+def : InstRW<[C1UWrite_2c_1M_StreamingCMEVX0ALU],
+             (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_2PXX")>;
+
+// SVE instructions added by SME but not sent to CME when in Streaming SVE mode
+// -----------------------------------------------------------------------------
+
+// Add/Read multiple of streaming SVE Predicate/vector register size to scalar register
+def : InstRW<[C1UWrite_1c_1I_Streaming], (instrs ADDSPL_XXI, ADDSVL_XXI, RDSVLI_XI)>;
+
+// Predicate counting scalar to count from predicate-as-counter
+def : InstRW<[C1UWrite_2c_1M_Streaming], (instregex "^CNTP_XCI_[BHSD]$")>;
+
+// Set predicates from predicate-as-counter
+def : InstRW<[C1UWrite_2c_1M_Streaming], (instregex "^PEXT_PCI_[BHSD]$")>;
+
+// Set pair of predicates from predicate-as-counter
+def : InstRW<[C1UWrite_3c_1M_Streaming], (instregex "^PEXT_2PCI_[BHSD]$")>;
+
+// Predicate as counter set
+def : InstRW<[C1UWrite_1c_1M_Streaming], (instregex "^PTRUE_C_[BHSD]$")>;
+
+// Loop control, based on GPR generating predicate as counter
+def : InstRW<[C1UWrite_1c_1M_Streaming], (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_CXX_[BHSD]$")>;
+
+// SVE instructions added by SME and only available in Streaming SVE mode
+// -----------------------------------------------------------------------------
+
+// Horizontal and vertical ZA reductions.
+def : InstRW<[C1UStreamingOnlySchedWrite<C1UWrite_4c_CMEVXALU_4rc>],
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nasherm wrote:

I've added a generic 1-cycle type for these. LMK if you think there should be something more subtle

https://github.com/llvm/llvm-project/pull/194850