[llvm] [AArch64][SVE] Enable known bits for predicated shifts (PR #200347)

[Harry Ramsey via llvm-commits]

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@@ -2937,6 +2937,26 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
     }
     break;
   }
+  case AArch64ISD::SHL_PRED:
+  case AArch64ISD::SRL_PRED:
+  case AArch64ISD::SRA_PRED: {
+    SDValue Pg = Op->getOperand(0);
+    if (!isAllActivePredicate(DAG, Pg) && (Pg.getOpcode() != AArch64ISD::PTRUE))
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Harry-Ramsey wrote:

This should enable fixed-length vectors that are converted to SVE to calculate known bits where applicable. Let me know if this check is ideal?

https://github.com/llvm/llvm-project/pull/200347