[llvm] [AMDGPU] Select uniform (shl, or) to a scalar S_LSHL_OR_B32 pseudo (PR #202585)

[Barbara Mitic via llvm-commits]

barbara-amd wrote:

This new change now handles the uniform (or (shl x, y), z) case that is visible as such in the SelectionDAG (single-use shift). 
It may be worth noting that it does not cover the high-half packing idiom case, where the value is bitcast(BUILD_VECTOR<2 x i16>{0, hi}) rather than an shl node - there is no (or (shl …)) in the DAG to match, so that case can't be reached by an ISel pattern.
The earlier (reverted) attempt was a post-RA peephole which works on the materialized instructions, so it could cover both this uniform case and the packing case in one place. We've moved the uniform case to ISel here since it's cleanly expressible as a pattern; the packing case is left out and likely wants a different solution
 

https://github.com/llvm/llvm-project/pull/202585