[llvm] [AMDGPU] Enable WMMA256bInsts + Wave32 for gfx1200/gfx1201 + SISchedule fix + TargetParser gfx1200 propagation (PR #202093)

[via llvm-commits]

clearnature wrote:

@Malexandra-de  Clarification: The K9 kernel possesses native INT4 throughput capabilities, rather than relying on floating-point emulation.

// mxfp4_swmmac_op.cpp — Comments explicitly state:
// Forward pass: INT4 weights × INT4 activations (using UE8M0 block scaling factors)
//               Dispatched via rocBLAS using the v_swmmac_i32_16x16x64_iu4 instruction

The value 4326 represents INT4 throughput—specifically, native IU4 SWMMAC performance on the gfx1200 architecture,
not FP4 emulation. The hardware features best-in-class support for 4-bit integer matrix operations.
The scheduling model describes INT4 pipeline latency; according to ISA specifications,
latencies are identical across various SWMMAC variants, including IU4, IU8, FP8, and FP16.
Regarding mxfp4, ​​a previous submission argued against a software implementation, noting a lack of precedent. The code was submitted to AMD; the original submission here was rejected. mxfp4 is analogous to nvfp4, given that floating-point quantization supports a broader range of use cases than integer quantization.

https://github.com/llvm/llvm-project/pull/202093