[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for init_whole_wave intrinsic (PR #203286)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 07:14:37 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/203286
None
>From 132d10270a95a6155059607d1fa1facad623f907 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Thu, 11 Jun 2026 15:01:43 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for init_whole_wave
intrinsic
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +
.../AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll | 102 ++++++++----------
.../AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll | 28 ++---
3 files changed, 54 insertions(+), 78 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 838951bcd8d26..3b935e75d0dca 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2287,6 +2287,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniB512}, {{SgprB512}, {IntrId, SgprB512}}})
.Any({{DivB512}, {{VgprB512}, {IntrId, VgprB512}}});
+ addRulesForIOpcs({amdgcn_init_whole_wave}).Any({{DivS1}, {{Vcc}, {IntrId}}});
+
addRulesForIOpcs({amdgcn_kill, amdgcn_wqm_demote})
.Any({{}, {{}, {IntrId, Vcc}}});
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
index a6659b2b1dd0d..025cccfb94e59 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GISEL12 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -O2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GISEL12 %s
; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=DAGISEL12 %s
-; RUN: llc -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=GISEL10 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -O2 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=GISEL10 %s
; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=DAGISEL10 %s
define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i32 inreg %exec, { i32, ptr addrspace(5), i32, i32 } %vgpr, i32 %x, i32 %y) {
@@ -121,13 +121,10 @@ define amdgpu_cs_chain void @wwm_in_shader(<3 x i32> inreg %sgpr, ptr inreg %cal
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v10, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
-; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL12-NEXT: v_mov_b32_e32 v0, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL12-NEXT: v_dual_mov_b32 v11, v0 :: v_dual_add_nc_u32 v10, 42, v10
+; GISEL12-NEXT: v_dual_mov_b32 v11, s8 :: v_dual_add_nc_u32 v10, 42, v10
; GISEL12-NEXT: ; %bb.2: ; %tail
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL12-NEXT: s_mov_b32 exec_lo, s5
@@ -172,10 +169,9 @@ define amdgpu_cs_chain void @wwm_in_shader(<3 x i32> inreg %sgpr, ptr inreg %cal
; GISEL10-NEXT: s_or_saveexec_b32 s4, -1
; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v10, s4
; GISEL10-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
-; GISEL10-NEXT: v_mov_b32_e32 v0, s8
; GISEL10-NEXT: s_mov_b32 exec_lo, s4
; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v10
-; GISEL10-NEXT: v_mov_b32_e32 v11, v0
+; GISEL10-NEXT: v_mov_b32_e32 v11, s8
; GISEL10-NEXT: ; %bb.2: ; %tail
; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL10-NEXT: s_mov_b32 exec_lo, s5
@@ -241,13 +237,10 @@ define amdgpu_cs_chain void @phi_whole_struct(<3 x i32> inreg %sgpr, ptr inreg %
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v12, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
-; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL12-NEXT: v_mov_b32_e32 v0, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL12-NEXT: v_dual_mov_b32 v11, v0 :: v_dual_add_nc_u32 v10, 42, v12
+; GISEL12-NEXT: v_dual_mov_b32 v11, s8 :: v_dual_add_nc_u32 v10, 42, v12
; GISEL12-NEXT: ; %bb.2: ; %tail
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL12-NEXT: s_mov_b32 exec_lo, s5
@@ -289,10 +282,9 @@ define amdgpu_cs_chain void @phi_whole_struct(<3 x i32> inreg %sgpr, ptr inreg %
; GISEL10-NEXT: s_or_saveexec_b32 s4, -1
; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v12, s4
; GISEL10-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
-; GISEL10-NEXT: v_mov_b32_e32 v0, s8
; GISEL10-NEXT: s_mov_b32 exec_lo, s4
; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v12
-; GISEL10-NEXT: v_mov_b32_e32 v11, v0
+; GISEL10-NEXT: v_mov_b32_e32 v11, s8
; GISEL10-NEXT: ; %bb.2: ; %tail
; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL10-NEXT: s_mov_b32 exec_lo, s5
@@ -358,50 +350,47 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL12-NEXT: s_mov_b32 s4, 0
; GISEL12-NEXT: .LBB3_2: ; %shader
; GISEL12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GISEL12-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL12-NEXT: v_mov_b32_e32 v2, v1
+; GISEL12-NEXT: v_add_nc_u32_e32 v1, 1, v2
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
-; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL12-NEXT: v_mov_b32_e32 v0, s9
; GISEL12-NEXT: s_mov_b32 exec_lo, s8
; GISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL12-NEXT: v_mov_b32_e32 v11, v0
+; GISEL12-NEXT: v_mov_b32_e32 v11, s9
; GISEL12-NEXT: s_or_b32 s4, vcc_lo, s4
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GISEL12-NEXT: s_cbranch_execnz .LBB3_2
; GISEL12-NEXT: ; %bb.3: ; %tail.loopexit
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v1
+; GISEL12-NEXT: v_add_nc_u32_e32 v10, 43, v2
; GISEL12-NEXT: .LBB3_4: ; %Flow1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL12-NEXT: s_mov_b32 s3, exec_lo
-; GISEL12-NEXT: ; implicit-def: $vgpr8
+; GISEL12-NEXT: s_mov_b32 s4, exec_lo
+; GISEL12-NEXT: ; implicit-def: $sgpr3
; GISEL12-NEXT: v_cmpx_lt_i32_e64 v12, v13
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GISEL12-NEXT: s_xor_b32 s3, exec_lo, s3
+; GISEL12-NEXT: s_xor_b32 s4, exec_lo, s4
; GISEL12-NEXT: ; %bb.5: ; %tail.else
-; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; GISEL12-NEXT: v_mov_b32_e32 v0, 15
-; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GISEL12-NEXT: s_mov_b32 exec_lo, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL12-NEXT: v_mov_b32_e32 v8, v0
+; GISEL12-NEXT: s_mov_b32 s3, 15
; GISEL12-NEXT: ; %bb.6: ; %Flow
-; GISEL12-NEXT: s_and_not1_saveexec_b32 s3, s3
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL12-NEXT: s_or_saveexec_b32 s4, s4
+; GISEL12-NEXT: v_mov_b32_e32 v8, s3
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL12-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GISEL12-NEXT: ; %bb.7: ; %tail.then
-; GISEL12-NEXT: s_mov_b32 s4, 44
+; GISEL12-NEXT: s_mov_b32 s3, 44
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GISEL12-NEXT: v_mov_b32_e32 v8, s4
+; GISEL12-NEXT: v_mov_b32_e32 v8, s3
; GISEL12-NEXT: ; %bb.8: ; %tail.end
-; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GISEL12-NEXT: s_mov_b32 exec_lo, s5
; GISEL12-NEXT: s_setpc_b64 s[6:7]
;
@@ -476,38 +465,37 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL10-NEXT: s_mov_b32 s4, 0
; GISEL10-NEXT: .LBB3_2: ; %shader
; GISEL10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL10-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GISEL10-NEXT: v_mov_b32_e32 v2, v1
+; GISEL10-NEXT: v_add_nc_u32_e32 v1, 1, v2
; GISEL10-NEXT: s_or_saveexec_b32 s8, -1
; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
; GISEL10-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
-; GISEL10-NEXT: v_mov_b32_e32 v0, s9
; GISEL10-NEXT: s_mov_b32 exec_lo, s8
; GISEL10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
-; GISEL10-NEXT: v_mov_b32_e32 v11, v0
+; GISEL10-NEXT: v_mov_b32_e32 v11, s9
; GISEL10-NEXT: s_or_b32 s4, vcc_lo, s4
; GISEL10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
; GISEL10-NEXT: s_cbranch_execnz .LBB3_2
; GISEL10-NEXT: ; %bb.3: ; %tail.loopexit
; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v1
+; GISEL10-NEXT: v_add_nc_u32_e32 v10, 43, v2
; GISEL10-NEXT: .LBB3_4: ; %Flow1
; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s3
-; GISEL10-NEXT: s_mov_b32 s3, exec_lo
-; GISEL10-NEXT: ; implicit-def: $vgpr8
+; GISEL10-NEXT: s_mov_b32 s4, exec_lo
+; GISEL10-NEXT: ; implicit-def: $sgpr3
; GISEL10-NEXT: v_cmpx_lt_i32_e64 v12, v13
-; GISEL10-NEXT: s_xor_b32 s3, exec_lo, s3
+; GISEL10-NEXT: s_xor_b32 s4, exec_lo, s4
; GISEL10-NEXT: ; %bb.5: ; %tail.else
-; GISEL10-NEXT: s_or_saveexec_b32 s4, -1
-; GISEL10-NEXT: v_mov_b32_e32 v0, 15
-; GISEL10-NEXT: s_mov_b32 exec_lo, s4
-; GISEL10-NEXT: v_mov_b32_e32 v8, v0
+; GISEL10-NEXT: s_mov_b32 s3, 15
; GISEL10-NEXT: ; %bb.6: ; %Flow
-; GISEL10-NEXT: s_andn2_saveexec_b32 s3, s3
+; GISEL10-NEXT: s_or_saveexec_b32 s4, s4
+; GISEL10-NEXT: v_mov_b32_e32 v8, s3
+; GISEL10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GISEL10-NEXT: ; %bb.7: ; %tail.then
-; GISEL10-NEXT: s_mov_b32 s4, 44
-; GISEL10-NEXT: v_mov_b32_e32 v8, s4
+; GISEL10-NEXT: s_mov_b32 s3, 44
+; GISEL10-NEXT: v_mov_b32_e32 v8, s3
; GISEL10-NEXT: ; %bb.8: ; %tail.end
-; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GISEL10-NEXT: s_mov_b32 exec_lo, s5
; GISEL10-NEXT: s_setpc_b64 s[6:7]
;
@@ -614,13 +602,10 @@ define amdgpu_cs_chain void @use_v0_7(<3 x i32> inreg %sgpr, ptr inreg %callee,
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v13, 0x47, v12, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v13
-; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL12-NEXT: v_mov_b32_e32 v13, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL12-NEXT: v_dual_mov_b32 v11, v13 :: v_dual_add_nc_u32 v10, 42, v12
+; GISEL12-NEXT: v_dual_mov_b32 v11, s8 :: v_dual_add_nc_u32 v10, 42, v12
; GISEL12-NEXT: ;;#ASMSTART
; GISEL12-NEXT: ; use v0-7
; GISEL12-NEXT: ;;#ASMEND
@@ -672,10 +657,9 @@ define amdgpu_cs_chain void @use_v0_7(<3 x i32> inreg %sgpr, ptr inreg %callee,
; GISEL10-NEXT: s_or_saveexec_b32 s4, -1
; GISEL10-NEXT: v_cndmask_b32_e64 v13, 0x47, v12, s4
; GISEL10-NEXT: v_cmp_ne_u32_e64 s8, 0, v13
-; GISEL10-NEXT: v_mov_b32_e32 v13, s8
; GISEL10-NEXT: s_mov_b32 exec_lo, s4
; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v12
-; GISEL10-NEXT: v_mov_b32_e32 v11, v13
+; GISEL10-NEXT: v_mov_b32_e32 v11, s8
; GISEL10-NEXT: ;;#ASMSTART
; GISEL10-NEXT: ; use v0-7
; GISEL10-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
index 4131ac744945e..db76e430ac977 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL12 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL12 %s
; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL12 %s
-; RUN: llc -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL10 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL10 %s
; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL10 %s
; This shouldn't be too different from wave32, so we'll only test one case.
@@ -21,24 +21,17 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; GISEL12-NEXT: s_mov_b32 s5, s6
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
-; GISEL12-NEXT: s_cbranch_execz .LBB0_2
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: s_or_saveexec_b64 s[10:11], -1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
-; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL12-NEXT: v_mov_b32_e32 v0, s12
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GISEL12-NEXT: v_mov_b32_e32 v1, s13
; GISEL12-NEXT: s_mov_b64 exec, s[10:11]
+; GISEL12-NEXT: v_mov_b32_e32 v11, s12
; GISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v13
-; GISEL12-NEXT: v_mov_b32_e32 v11, v0
-; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GISEL12-NEXT: v_mov_b32_e32 v12, v1
-; GISEL12-NEXT: .LBB0_2: ; %tail
-; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL12-NEXT: v_mov_b32_e32 v12, s13
+; GISEL12-NEXT: ; %bb.2: ; %tail
; GISEL12-NEXT: s_or_b64 exec, exec, s[6:7]
; GISEL12-NEXT: s_mov_b64 exec, s[4:5]
; GISEL12-NEXT: s_setpc_b64 s[8:9]
@@ -81,18 +74,15 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; GISEL10-NEXT: s_mov_b32 s4, s5
; GISEL10-NEXT: s_mov_b32 s5, s6
; GISEL10-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
-; GISEL10-NEXT: s_cbranch_execz .LBB0_2
; GISEL10-NEXT: ; %bb.1: ; %shader
; GISEL10-NEXT: s_or_saveexec_b64 s[10:11], -1
; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
; GISEL10-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
-; GISEL10-NEXT: v_mov_b32_e32 v0, s12
-; GISEL10-NEXT: v_mov_b32_e32 v1, s13
; GISEL10-NEXT: s_mov_b64 exec, s[10:11]
+; GISEL10-NEXT: v_mov_b32_e32 v11, s12
; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v13
-; GISEL10-NEXT: v_mov_b32_e32 v11, v0
-; GISEL10-NEXT: v_mov_b32_e32 v12, v1
-; GISEL10-NEXT: .LBB0_2: ; %tail
+; GISEL10-NEXT: v_mov_b32_e32 v12, s13
+; GISEL10-NEXT: ; %bb.2: ; %tail
; GISEL10-NEXT: s_or_b64 exec, exec, s[6:7]
; GISEL10-NEXT: s_mov_b64 exec, s[4:5]
; GISEL10-NEXT: s_setpc_b64 s[8:9]
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