[llvm] [AMDGPU] Enable WMMA256bInsts + Wave32 for gfx1200/gfx1201 + SISchedule fix + TargetParser gfx1200 propagation (PR #202093)

[via llvm-commits]

clearnature wrote:

@Malexandra-de You are correct; the constraint check in `tryMatchVOPDPair`
only verifies the interaction between the two VALU instructions
—it does not consider their relationship with subsequent (downstream) instructions.

The register changed from v48 to v33 because `GCNCreateVOPD`
replaced the destination operands of both instructions with
the register pair required for `V_DUAL` encoding (v0 and v33 on GFX12).
The SWMMAC instruction still references v48 as its sparse index—but the
`mov` instruction that initialized v48 no longer exists. This is an oversight
in liveness tracking, not a failure of the constraint check.
Post-fusion replacement (v48 → v33): ❌ LLVM defect — downstream references were not checked.

Breakpoint: `GCNCreateVOPD::doReplace()` unconditionally replaces the destination register,
without scanning the source operands of subsequent instructions. v48 is referenced
by the subsequent SWMMAC, but `doReplace` ignores this.

We didn't introduce the bug—this gap has always existed in LLVM. It’s just that no one had added a latency table for gfx1200 before, so no one had encountered it. We are the first to expose it.

The test case has been reverted to work around this issue. The SISchedule entries
remain unchanged.
It’s not a matter of irresponsibility; we simply ran into this inherent LLVM bug. As mentioned earlier, we just happened to hit this problem—much like others have noted—and there are likely many other scenarios where this issue could arise.

https://github.com/llvm/llvm-project/pull/202093