[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for G_PREFETCH (PR #203265)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 06:31:16 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/203265
None
>From 709bb796d893c5060ef7808486103fab882d4dbb Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Thu, 11 Jun 2026 14:54:14 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for G_PREFETCH
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 8 ++++++
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 27 +++++++++++++++++++
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 5 +++-
llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll | 12 ++++-----
4 files changed, 45 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 07e71b24c59f9..ea3d44488cd65 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1505,6 +1505,9 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
return lowerAbsToNegMax(MI);
case AbsToS32:
return lowerAbsToS32(MI);
+ case DeletePrefetch:
+ MI.eraseFromParent();
+ return true;
}
return true;
@@ -1561,6 +1564,8 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case SgprP5:
case VgprP5:
return LLT::pointer(5, 32);
+ case SgprP6:
+ return LLT::pointer(6, 32);
case SgprP8:
return LLT::pointer(8, 128);
case SgprV2S16:
@@ -1712,6 +1717,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case SgprP4:
case SgprP4Call_WF:
case SgprP5:
+ case SgprP6:
case SgprP8:
case SgprPtr32:
case SgprPtr64:
@@ -1830,6 +1836,7 @@ bool RegBankLegalizeHelper::applyMappingDst(
case SgprP3:
case SgprP4:
case SgprP5:
+ case SgprP6:
case SgprP8:
case SgprV2S16:
case SgprV2S32:
@@ -2042,6 +2049,7 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case SgprP3:
case SgprP4:
case SgprP5:
+ case SgprP6:
case SgprP8:
case SgprV2S16:
case SgprV2S32:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 60eb33b64fc0d..53099c17784ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -122,6 +122,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniformAtDef(Reg);
case UniP5:
return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniformAtDef(Reg);
+ case UniP6:
+ return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isUniformAtDef(Reg);
case UniP8:
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniformAtDef(Reg);
case UniPtr32:
@@ -1523,6 +1525,31 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForGOpcs({G_AMDGPU_S_BUFFER_PREFETCH})
.Any({{}, {{}, {SgprV4S32_ReadFirstLane, Imm, SgprB32_ReadFirstLane}}});
+ Predicate IsDataPF([](const MachineInstr &MI) -> bool {
+ // prefetch cache type: 0 == instruction (I$) prefetch, 1 == data prefetch.
+ return MI.getOperand(3).getImm() != 0;
+ });
+
+ bool HasSMemPF = ST->hasSafeSmemPrefetch();
+ bool HasVMemPF = ST->hasVmemPrefInsts();
+ addRulesForGOpcs({G_PREFETCH})
+ // Safe smem prefetch keeps both data and instruction prefetch.
+ .Any({{UniPtr64}, {{}, {SgprPtr64}}}, HasSMemPF)
+ // Vmem prefetch keeps data prefetch only.
+ .Any({{{UniPtr64}, IsDataPF}, {{}, {SgprPtr64}}}, !HasSMemPF && HasVMemPF)
+ .Any({{{UniPtr64}, IsDataPF}, {{}, {}, DeletePrefetch}},
+ !HasSMemPF && !HasVMemPF)
+ .Any({{{UniPtr64}, !IsDataPF}, {{}, {}, DeletePrefetch}}, !HasSMemPF)
+
+ .Any({{{DivPtr64}, IsDataPF}, {{}, {VgprPtr64}}}, HasVMemPF)
+ .Any({{{DivPtr64}, IsDataPF}, {{}, {}, DeletePrefetch}}, !HasVMemPF)
+ .Any({{{DivPtr64}, !IsDataPF}, {{}, {}, DeletePrefetch}})
+
+ .Any({{P3}, {{}, {}, DeletePrefetch}})
+ .Any({{P5}, {{}, {}, DeletePrefetch}})
+ .Any({{UniP6}, {{}, {SgprP6}}}, HasSMemPF)
+ .Any({{UniP6}, {{}, {}, DeletePrefetch}}, !HasSMemPF);
+
addRulesForGOpcs({G_FPEXT})
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}})
.Any({{UniS64, S32}, {{UniInVgprS64}, {Vgpr32}}})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index 147e80877ec6e..829018cdb3159 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -79,6 +79,7 @@ enum UniformityLLTOpPredicateID {
UniP3,
UniP4,
UniP5,
+ UniP6,
UniP8,
UniPtr32,
UniPtr64,
@@ -183,6 +184,7 @@ enum RegBankLLTMappingApplyID {
SgprP3,
SgprP4,
SgprP5,
+ SgprP6,
SgprP8,
SgprPtr32,
SgprPtr64,
@@ -341,7 +343,8 @@ enum LoweringMethodID {
InsVecEltTo32,
AbsToNegMax,
AbsToS32,
- DynStackAlloc
+ DynStackAlloc,
+ DeletePrefetch
};
enum FastRulesTypes {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll b/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
index f042474df4fa7..a0776a2e3d88d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
@@ -5,12 +5,12 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,NOSPREFETCH %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+safe-smem-prefetch < %s | FileCheck --check-prefixes=GCN,SPREFETCH,GFX12-SPREFETCH,SPREFETCH-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GCN,NOSPREFETCH %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GFX1250,GL2-ONLY %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+safe-smem-prefetch < %s | FileCheck --check-prefixes=GCN,SPREFETCH,GFX1250-SPREFETCH,GFX1250-SPREFETCH-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+safe-cu-prefetch < %s | FileCheck --check-prefixes=GCN,GFX1250,SAFE-CU %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,NOSPREFETCH %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+safe-smem-prefetch < %s | FileCheck --check-prefixes=GCN,SPREFETCH,GFX12-SPREFETCH,SPREFETCH-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GCN,NOSPREFETCH %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GFX1250,GL2-ONLY %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+safe-smem-prefetch < %s | FileCheck --check-prefixes=GCN,SPREFETCH,GFX1250-SPREFETCH,GFX1250-SPREFETCH-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+safe-cu-prefetch < %s | FileCheck --check-prefixes=GCN,GFX1250,SAFE-CU %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,NOSPREFETCH %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+safe-smem-prefetch < %s | FileCheck --check-prefixes=GCN,SPREFETCH,GFX12-SPREFETCH,SPREFETCH-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GCN,NOSPREFETCH %s
; Scalar data prefetch
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