[llvm] [AVR] Add intrinsics for builtin functions (PR #203212)

[via llvm-commits]

https://github.com/beakthoven created https://github.com/llvm/llvm-project/pull/203212

None

>From c968136ba874c7ca98cf859b07b6bac8729733dd Mon Sep 17 00:00:00 2001
From: Dakkshesh <beakthoven at gmail.com>
Date: Thu, 11 Jun 2026 11:50:35 +0530
Subject: [PATCH 1/2] [AVR] Add intrinsics for nop, sei, cli, sleep, wdr, and
 swap

Introduce IntrinsicsAVR.td with target-specific intrinsics and add
the corresponding isel patterns in AVRInstrInfo.td. sei/cli lower
to BSETs/BCLRs on the I flag, swap lowers to SWAPRd.

Signed-off-by: Dakkshesh <beakthoven at gmail.com>
---
 llvm/include/llvm/IR/Intrinsics.td      |  1 +
 llvm/include/llvm/IR/IntrinsicsAVR.td   | 24 +++++++++++
 llvm/lib/Target/AVR/AVRInstrInfo.td     | 11 +++++
 llvm/test/CodeGen/AVR/avr-intrinsics.ll | 56 +++++++++++++++++++++++++
 4 files changed, 92 insertions(+)
 create mode 100644 llvm/include/llvm/IR/IntrinsicsAVR.td
 create mode 100644 llvm/test/CodeGen/AVR/avr-intrinsics.ll

diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 393dcb751a4a0..595938e8ba52b 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -3123,6 +3123,7 @@ include "llvm/IR/IntrinsicsXCore.td"
 include "llvm/IR/IntrinsicsHexagon.td"
 include "llvm/IR/IntrinsicsNVVM.td"
 include "llvm/IR/IntrinsicsMips.td"
+include "llvm/IR/IntrinsicsAVR.td"
 include "llvm/IR/IntrinsicsAMDGPU.td"
 include "llvm/IR/IntrinsicsBPF.td"
 include "llvm/IR/IntrinsicsSystemZ.td"
diff --git a/llvm/include/llvm/IR/IntrinsicsAVR.td b/llvm/include/llvm/IR/IntrinsicsAVR.td
new file mode 100644
index 0000000000000..8f946ebcdee9d
--- /dev/null
+++ b/llvm/include/llvm/IR/IntrinsicsAVR.td
@@ -0,0 +1,24 @@
+//==- IntrinsicsAVR.td - AVR intrinsics                 -*- tablegen -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the AVR-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "avr" in { // All intrinsics start with "llvm.avr.".
+
+  // Simple void instruction intrinsics.
+  def int_avr_nop : Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+  def int_avr_sei : Intrinsic<[], [], [IntrHasSideEffects]>;
+  def int_avr_cli : Intrinsic<[], [], [IntrHasSideEffects]>;
+  def int_avr_sleep : Intrinsic<[], [], [IntrHasSideEffects]>;
+  def int_avr_wdr : Intrinsic<[], [], [IntrHasSideEffects]>;
+
+  // Swap nibbles: returns i8 with high and low nibbles exchanged.
+  def int_avr_swap : Intrinsic<[llvm_i8_ty], [llvm_i8_ty], [IntrNoMem]>;
+}
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 493e9aa781182..1ad4776d749f4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1736,3 +1736,14 @@ def : Pat<(AVRtst i8 : $rd), (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
 // Lowering of 'lsl' node to 'LSL' instruction.
 // LSL is an alias of 'ADD Rd, Rd'
 def : Pat<(AVRlsl i8 : $rd), (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;
+
+//===----------------------------------------------------------------------===//
+// Builtin lowering
+//===----------------------------------------------------------------------===//
+
+def : Pat<(int_avr_nop), (NOP)>;
+def : Pat<(int_avr_sleep), (SLEEP)>;
+def : Pat<(int_avr_wdr), (WDR)>;
+def : Pat<(int_avr_sei), (BSETs 7)>;
+def : Pat<(int_avr_cli), (BCLRs 7)>;
+def : Pat<(int_avr_swap i8:$src), (SWAPRd GPR8:$src)>;
diff --git a/llvm/test/CodeGen/AVR/avr-intrinsics.ll b/llvm/test/CodeGen/AVR/avr-intrinsics.ll
new file mode 100644
index 0000000000000..740d03eb7d7ae
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/avr-intrinsics.ll
@@ -0,0 +1,56 @@
+; RUN: llc -mtriple=avr -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK-LABEL: test_nop:
+; CHECK: nop
+; CHECK: ret
+define void @test_nop() {
+  call void @llvm.avr.nop()
+  ret void
+}
+
+; CHECK-LABEL: test_sei:
+; CHECK: sei
+; CHECK: ret
+define void @test_sei() {
+  call void @llvm.avr.sei()
+  ret void
+}
+
+; CHECK-LABEL: test_cli:
+; CHECK: cli
+; CHECK: ret
+define void @test_cli() {
+  call void @llvm.avr.cli()
+  ret void
+}
+
+; CHECK-LABEL: test_sleep:
+; CHECK: sleep
+; CHECK: ret
+define void @test_sleep() {
+  call void @llvm.avr.sleep()
+  ret void
+}
+
+; CHECK-LABEL: test_wdr:
+; CHECK: wdr
+; CHECK: ret
+define void @test_wdr() {
+  call void @llvm.avr.wdr()
+  ret void
+}
+
+; CHECK-LABEL: test_swap:
+; CHECK: swap r24
+; CHECK: ret
+define i8 @test_swap(i8 %a) {
+  %1 = call i8 @llvm.avr.swap(i8 %a)
+  ret i8 %1
+}
+
+declare void @llvm.avr.nop()
+declare void @llvm.avr.sei()
+declare void @llvm.avr.cli()
+declare void @llvm.avr.sleep()
+declare void @llvm.avr.wdr()
+declare i8 @llvm.avr.swap(i8)

>From 7838bb0030f5fdb36204709a16b0b1376db0fc68 Mon Sep 17 00:00:00 2001
From: Dakkshesh <beakthoven at gmail.com>
Date: Thu, 11 Jun 2026 14:19:17 +0530
Subject: [PATCH 2/2] [IR] Generate IntrinsicsAVR.h

Signed-off-by: Dakkshesh <beakthoven at gmail.com>
---
 llvm/include/llvm/IR/CMakeLists.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/include/llvm/IR/CMakeLists.txt b/llvm/include/llvm/IR/CMakeLists.txt
index c5c4cc4d21b84..5a7676b968589 100644
--- a/llvm/include/llvm/IR/CMakeLists.txt
+++ b/llvm/include/llvm/IR/CMakeLists.txt
@@ -10,6 +10,7 @@ tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
 tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
 tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
 tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
+tablegen(LLVM IntrinsicsAVR.h -gen-intrinsic-enums -intrinsic-prefix=avr)
 tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
 tablegen(LLVM IntrinsicsDirectX.h -gen-intrinsic-enums -intrinsic-prefix=dx)
 tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)