[llvm] [LoongArch][NFC] Add demanded bits tests for CRC[C].W.{B, H}.W (PR #203200)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-loongarch

Author: hev (heiher)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/203200.diff


1 Files Affected:

- (added) llvm/test/CodeGen/LoongArch/crc.ll (+50) 


``````````diff
diff --git a/llvm/test/CodeGen/LoongArch/crc.ll b/llvm/test/CodeGen/LoongArch/crc.ll
new file mode 100644
index 0000000000000..59fcf41aa057e
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/crc.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+define i32 @crc_w_b_w(i8 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi $a0, $a0, 255
+; CHECK-NEXT:    crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = zext i8 %a to i32
+  %1 = call i32 @llvm.loongarch.crc.w.b.w(i32 %0, i32 %b)
+  ret i32 %1
+}
+
+define i32 @crc_w_h_w(i16 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bstrpick.d $a0, $a0, 15, 0
+; CHECK-NEXT:    crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = zext i16 %a to i32
+  %1 = call i32 @llvm.loongarch.crc.w.h.w(i32 %0, i32 %b)
+  ret i32 %1
+}
+
+define i32 @crcc_w_b_w(i8 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi $a0, $a0, 255
+; CHECK-NEXT:    crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = zext i8 %a to i32
+  %1 = call i32 @llvm.loongarch.crcc.w.b.w(i32 %0, i32 %b)
+  ret i32 %1
+}
+
+define i32 @crcc_w_h_w(i16 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bstrpick.d $a0, $a0, 15, 0
+; CHECK-NEXT:    crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = zext i16 %a to i32
+  %1 = call i32 @llvm.loongarch.crcc.w.h.w(i32 %0, i32 %b)
+  ret i32 %1
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/203200