[llvm] [AMDGPU] DAG Mutation to solve load bunching in outer product matrix multiplications (PR #203095)

[Zeng Wu via llvm-commits]

zwu-2025 wrote:

> MaxOccupancy

@axelcool1234 , do you run llc like `llc -amdgpu-sched-strategy=max-ilp` and there is no input MIR here, so I cannot check the attribute in the MIR either.
But as far as I know, we don't choose the strategy like `max-ilp`, `max-memory-clause`,  `iterative-*`, etc, so the GCNTargetMachine::createMachineScheduler() would fall back to this max-occupancy scheduler ` GCNTargetMachine::createMachineScheduler`

The purpose of the project is as @guacamoleo mentioned, 
we are going to add a new DAG mutation even though it ONLY influences the candidate set and critical path and it cannot directly change the ranking policy  unless it uses strong ordering edges to force the schedule.

The latency adjustment with weak/artificial edges in the DAG mutation are only applied when the pattern is clear and @axelcool1234 will give the pattern in the update of patch, then it will be much more clear . 

The code might include 
- finding SUNnit of ds_load consumed by wmma
- tuning/adding latency for the real data edge
- respecting edges across barriers, waits, stores, side-effecting memory, or ambiguous aliasing.
etc.


Once the basic work is done and to make the work more practical, we might encode the followoing order
  1. RegExcess
  2. PhysReg
  3. Stall / Resource / Latency
  4. Cluster / Weak
  5. RegCritical
  6. RegMax
  7. NodeOrder

in `tryCandidate()` and currently, if both candiates are in the same zone, then the order is
  1. FirstValid
  2. PhysReg
  3. RegExcess
  4. RegCritical


https://github.com/llvm/llvm-project/pull/203095