[llvm] [AMDGPU] using divergent/uniform information in ISel of zext (PR #174539)

[Zeng Wu via llvm-commits]

zwu-2025 wrote:

> > There are still many test failures.
> 
> there are 16 failures, some of them looks normal but others seems needs investigation. Except the pattern pointed by @arsenm 's comment, which is fixed in [patch](https://github.com/llvm/llvm-project/pull/201038), the other one is `func_non_entry_block_static_alloca_align4 at non-entry-alloca.ll`.
> 
> In simple words, the RegClass selection is changed in the patch, for the `bb.2`, there are multiple `COPY %22:vgpr_32` to a `sgpr_32` and the coming `si-fix-sgpr-copies` make the MIR very different.
> 
> Details

Now the regression about extra copy between SGPR and VGPR, e.g. `non-entry-alloca.ll` are fixed by using VS_32RegClassID if possible. The details is in the comment above.  Previously there were 55 in lit-tests AMDGPU changed, now there are 48 lit-tests are changed.


https://github.com/llvm/llvm-project/pull/174539