[llvm] [AMDGPU] Enable WMMA256bInsts + Wave32 for gfx1200/gfx1201 + SISchedule fix + TargetParser gfx1200 propagation (PR #202093)

[Alexandra Munkes via llvm-commits]

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@@ -9,9 +9,8 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_SWMMAC_cluster(ptr
 ; GCN-LABEL: test_sched_group_barrier_pipeline_SWMMAC_cluster:
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GCN-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
-; GCN-NEXT:    v_mov_b32_e32 v48, 0
-; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GCN-NEXT:    v_dual_mov_b32 v33, 0 :: v_dual_lshlrev_b32 v0, 4, v0
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Malexandra-de wrote:

This breaks the functionality tested by the test. `v_mov_b32_e32 v48, 0` writes the literal `0` to vector register `v48`, which is later used as the sparse index data `src2` for `v_swmmac_f16_16x16x32_f16 v[28:31], v[8:11], v[0:7], v48`. v48 is now uninitialized, leading to undefined behaviour.

https://github.com/llvm/llvm-project/pull/202093