[llvm] [AMDGPU] using divergent/uniform information in ISel of zext (PR #174539)

[Zeng Wu via llvm-commits]

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@@ -150,6 +145,22 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
       break;
   }
 
+  // FIXME: The Untyped check is a workaround for SystemZ i128 inline assembly
+  // using i128, when it should probably be using v2i64.
+  const TargetRegisterClass *RegClassForVT =
+      VT == MVT::Untyped ? nullptr : TLI->getRegClassFor(VT, Op->isDivergent());
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zwu-2025 wrote:

Here we use  `TII->getRegClass` to replace `TRI->getAllocatableClass` since getRegClass and use `getAllocatableClass` after intersecting selection for all usages. Which means we choose the register class based on the actual operand constraint from the table-gen and we don't add extra constraint.

Now the logic is:
- Collect the real operand classes from all users with TII->getRegClass.
- Intersect those real constraints with TRI->getCommonSubClass.
- Intersect/fallback with the VT class.
- Only then call TRI->getAllocatableClass(UseRC) before creating the virtual register on line 162.

Please correct me I am wrong. My understanding is useful when we need to create a virtual register class and it returns a maximal subclass of the given register class.  For us, if the operand is used with different SGPR and VGPR and the user has definition like `AMDGPU::VS_32RegClassID` 
` /* 2815 */ { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }
`
then the newly generated copies between VGPR and SGPR will be cleared.



https://github.com/llvm/llvm-project/pull/174539