[llvm] [AMDGPU] Adjust amdgpu fmax/fmin legalization (PR #202917)

[via llvm-commits]

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@@ -1560,6 +1562,33 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
       .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
 
+  auto ScalarNumIsSafe = [=](const MachineInstr &MI) {
+    const SIMachineFunctionInfo *MFI =
+        MI.getMF()->getInfo<SIMachineFunctionInfo>();
+    return hasSALUFloat && (!MFI->getMode().IEEE || hasSALUMinimumMaximumInsts);
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Shoreshen wrote:

Hi @arsenm the key in here which is function dependency is IEEE bit in MODE. This only lies in MFI, so it is really hard to make it independent of MF.

I tried another method which is:
1. In regbank select, for fmaxnum/fminnum related node, even if is uniform, will select SGPR only when !IEEE or !hasSALUMinimumMaximumInsts.
2. Change UniInVgprS* and let it accept VGPR, if in VGPR add a readfirstlane to SGPR (for the uniform user)
3. Let Combiner to optimize out redundant readfirstlane

But I don't think this is better then using lambda, which only need one place adjustment and is clear in code.

https://github.com/llvm/llvm-project/pull/202917