[llvm] [Uniformity] Implement per-output machine uniformity analysis (PR #179275)

[Sameer Sahasrabuddhe via llvm-commits]

================
@@ -11003,30 +11003,50 @@ const MIRFormatter *SIInstrInfo::getMIRFormatter() const {
   return Formatter.get();
 }
 
-ValueUniformity SIInstrInfo::getValueUniformity(const MachineInstr &MI) const {
+bool SIInstrInfo::isTerminatorDivergent(const MachineInstr &MI) const {
+  assert(MI.isTerminator());
+  return isNeverUniform(MI);
+}
+
+ValueUniformity SIInstrInfo::getValueUniformity(const MachineInstr &MI,
+                                                const MachineRegisterInfo &MRI,
+                                                unsigned DefIdx) const {
+  assert(!MI.isTerminator() &&
+         "use isTerminatorDivergent() to query terminator divergence");
+  assert(DefIdx < (unsigned)std::distance(MI.all_defs().begin(),
+                                          MI.all_defs().end()) &&
+         "DefIdx is out of range for this instruction's defs");
+  Register DefReg = std::next(MI.all_defs().begin(), DefIdx)->getReg();
+  assert(DefReg.isVirtual() &&
+         "DefIdx must name a virtual register def, not a physical register");
+
+  // A def whose register bank/class forces uniformity (e.g. an SGPR, but not a
+  // lane-mask class) cannot hold a divergent value regardless of the
+  // instruction's semantics. Resolve that here so the generic
+  // MachineUniformityAnalysis seeding stays target-agnostic and does not need
+  // to consult the register bank itself.
+  if (RI.isUniformReg(MRI, *ST.getRegBankInfo(), DefReg))
+    return ValueUniformity::Default;
 
   if (isNeverUniform(MI))
     return ValueUniformity::NeverUniform;
 
+  // Inline asm can define several registers with different reg classes, so the
+  // uniformity of each output is answered individually from its def reg class.
+  if (MI.isInlineAsm()) {
+    const MachineOperand &MO = *std::next(MI.all_defs().begin(), DefIdx);
----------------
ssahasra wrote:

What is the difference between this `MO` and the `DefReg` that we already have? If `DefReg` was a uniform reg, we had already returned it. Then why bother checking for SGPR here? Also, how do we know that reg is NeverUniform just because it is not in an SGPR? Even a VGPR can hold uniform value.

https://github.com/llvm/llvm-project/pull/179275