[llvm] [AMDGPU] Enable WMMA256bInsts + Wave32 for gfx1200/gfx1201 + SISchedule fix + TargetParser gfx1200 propagation (PR #202093)

[via llvm-commits]

clearnature wrote:

## CI failures analysis / CI 失败分析

The 3 Linux test failures break down as follows:

3 个 Linux 测试失败分析如下：

### 1. llvm.amdgcn.sched.group.barrier.gfx12.ll — caused by this PR / 本 PR 引起

Our SISchedule entries cause the scheduler to produce V_DUAL fused
instructions (\`v_dual_mov_b32 ... :: v_dual_lshlrev_b32\`) where the
CHECK lines expect two separate instructions. This is expected behavior
from correct latency tables — the scheduler now knows it can dual-issue
while WMMA occupies HWXDL.

This will be fixed by re-running \`update_llc_test_checks.py\`.

我们的 SISchedule 延迟表使调度器产生 V_DUAL 融合指令，CHECK 行还期望两个独立指令。
这是正确的延迟表带来的预期行为——调度器知道在 WMMA 占用 HWXDL 时可以双发射。
将用 \`update_llc_test_checks.py\` 修复。

### 2. llvm-mca/AMDGPU/gfx12-pseudo-scalar-trans.s — caused by this PR / 本 PR 引起

Our new HWXDL resource entries add an 8th column to the mca resource
pressure table. CHECK lines expect 7 columns.

Will be fixed by updating the CHECK lines.

新增的 HWXDL 资源给 mca 资源压力表加了第 8 列。CHECK 行期望 7 列。
将更新 CHECK 行修复。

### 3. Flang/Driver/omp-driver-offload.f90 — pre-existing, unrelated / 预存 flaky test

This is a Flang OpenMP offload formatting issue on AArch64. Not related
to AMDGPU. Reported as flaky infrastructure: llvm/llvm-project#203115
with infrastructure label.

这是 Flang OpenMP offload 在 AArch64 上的格式化问题。与 AMDGPU 无关。
已报 flaky infrastructure: llvm/llvm-project#203115，打 infrastructure 标签。

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### Next steps / 后续步骤

- Fix barriers + llvm-mca CHECK lines via update scripts
- Add llvm-mca test showing SWMMAC latency table coverage
- Update PR description to reflect single-file scope
- Provide benchmark justification for latency table values

https://github.com/llvm/llvm-project/pull/202093