[llvm] [AMDGPU] Tweak sched model latencies for VALU fast-forward cases (PR #198475)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 09:02:31 PDT 2026
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/198475
>From 46b92d7811d3363a76b504796e42dafbe5d29bda Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Mon, 18 May 2026 17:59:07 +0100
Subject: [PATCH 1/2] [AMDGPU] Tweak sched model latencies for VALU
fast-forward cases
Model VALU fast-forward cases by setting the latency of the dependency
edge to zero. This allows scheduling pairs like V_CMP/V_CNDMASK
adjacently without the usual VALU->VALU latency, which should give the
scheduler more freedom.
Note that the implementation is similar to shouldScheduleAdjacent but
the purpose is different:
- adjustSchedDependency is trying to increase the accuracy of the
scheduling model. This is useful both pre- and post-RA.
- shouldScheduleAdjacent is trying to encourage allocation of VCC so
that instructions can be shrunk to 32-bit encoding. This is only
useful pre-RA.
---
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 16 +
.../CodeGen/AMDGPU/GlobalISel/andn2.i1.ll | 4 +-
.../GlobalISel/artifact-combiner-asserts.ll | 6 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 23 +-
.../AMDGPU/GlobalISel/bitcast_38_i16.ll | 6 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll | 87 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll | 10 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 88 +-
.../test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll | 54 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll | 6 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 602 +++--
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 557 ++---
llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll | 71 +-
.../AMDGPU/GlobalISel/insertelement.i16.ll | 164 +-
.../AMDGPU/GlobalISel/insertelement.i8.ll | 70 +-
.../AMDGPU/GlobalISel/insertelement.ll | 739 +++---
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 4 +-
.../CodeGen/AMDGPU/GlobalISel/mubuf-global.ll | 3 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 40 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 151 +-
.../CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 56 +-
.../AMDGPU/GlobalISel/select-to-fmin-fmax.ll | 28 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll | 16 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 58 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 81 +-
.../test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll | 18 +-
.../CodeGen/AMDGPU/GlobalISel/udiv.i64.ll | 88 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 26 +-
.../test/CodeGen/AMDGPU/GlobalISel/usubsat.ll | 22 +-
.../CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll | 32 +-
.../test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll | 168 +-
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 88 +-
llvm/test/CodeGen/AMDGPU/addsub64_carry.ll | 2 +-
.../amdgpu-simplify-libcall-rootn-codegen.ll | 16 +-
.../CodeGen/AMDGPU/asyncmark-gfx12plus.ll | 4 +-
.../atomic_optimizations_global_pointer.ll | 224 +-
.../atomic_optimizations_local_pointer.ll | 494 ++--
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 82 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 235 +-
.../buffer-fat-pointer-atomicrmw-fadd.ll | 28 +-
.../buffer-fat-pointer-atomicrmw-fmax.ll | 8 +-
.../buffer-fat-pointer-atomicrmw-fmin.ll | 8 +-
llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll | 2 +-
llvm/test/CodeGen/AMDGPU/bypass-div.ll | 56 +-
.../test/CodeGen/AMDGPU/carryout-selection.ll | 12 +-
llvm/test/CodeGen/AMDGPU/ctlz.ll | 2 +-
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 220 +-
llvm/test/CodeGen/AMDGPU/div_i128.ll | 30 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 283 +--
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 495 ++--
llvm/test/CodeGen/AMDGPU/fdiv.ll | 4 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fadd.ll | 72 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 76 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 76 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fsub.ll | 76 +-
llvm/test/CodeGen/AMDGPU/fma.f16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 126 +-
llvm/test/CodeGen/AMDGPU/fminimum.ll | 126 +-
llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll | 275 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll | 120 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 87 +-
.../CodeGen/AMDGPU/fneg-modifier-casting.ll | 35 +-
llvm/test/CodeGen/AMDGPU/fp_to_sint.ll | 20 +-
.../AMDGPU/fp_trunc_store_fp64_to_bf16.ll | 68 +-
llvm/test/CodeGen/AMDGPU/fptoi.i128.ll | 12 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll | 205 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 313 +--
llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll | 112 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 242 +-
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 128 +-
.../AMDGPU/fptrunc.v2f16.no.fast.math.ll | 14 +-
llvm/test/CodeGen/AMDGPU/fract-match.ll | 181 +-
llvm/test/CodeGen/AMDGPU/freeze.ll | 102 +-
llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll | 68 +-
llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll | 616 ++---
.../AMDGPU/gfx11-sgpr-hazard-latency.mir | 64 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 84 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmax.ll | 76 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmin.ll | 76 +-
.../CodeGen/AMDGPU/global-atomicrmw-fsub.ll | 76 +-
llvm/test/CodeGen/AMDGPU/global-saddr-load.ll | 20 +-
llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll | 328 ++-
.../CodeGen/AMDGPU/indirect-addressing-si.ll | 24 +-
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 4 +-
.../AMDGPU/integer-select-src-modifiers.ll | 28 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll | 4 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 32 +-
llvm/test/CodeGen/AMDGPU/literal64.ll | 10 +-
.../AMDGPU/llvm.amdgcn.av.store.b128.ll | 3 +-
.../AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll | 12 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll | 62 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll | 62 +-
llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll | 1322 +++++-----
llvm/test/CodeGen/AMDGPU/llvm.exp.ll | 8 +-
llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll | 1882 +++++++-------
llvm/test/CodeGen/AMDGPU/llvm.exp10.ll | 8 +-
llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll | 266 +-
llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll | 1578 ++++++------
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll | 18 +-
llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll | 62 +-
llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 10 +-
.../CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll | 16 +-
.../CodeGen/AMDGPU/llvm.is.fpclass.f16.ll | 52 +-
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 109 +-
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 109 +-
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 141 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll | 20 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll | 12 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll | 1434 +++++------
llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll | 20 +-
llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll | 12 +-
llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll | 1434 +++++------
llvm/test/CodeGen/AMDGPU/llvm.modf.ll | 100 +-
llvm/test/CodeGen/AMDGPU/llvm.mulo.ll | 93 +-
llvm/test/CodeGen/AMDGPU/llvm.round.ll | 96 +-
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 16 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 16 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 16 +-
.../CodeGen/AMDGPU/local-atomicrmw-fsub.ll | 16 +-
.../test/CodeGen/AMDGPU/loop-prefetch-data.ll | 30 +-
llvm/test/CodeGen/AMDGPU/lrint.ll | 12 +-
llvm/test/CodeGen/AMDGPU/lround.ll | 84 +-
...ne-sink-temporal-divergence-swdev407790.ll | 6 +-
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll | 2207 ++++++++--------
.../CodeGen/AMDGPU/memintrinsic-unroll.ll | 60 +-
llvm/test/CodeGen/AMDGPU/memmove-var-size.ll | 88 +-
llvm/test/CodeGen/AMDGPU/min.ll | 12 +-
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll | 2217 +++++++++--------
.../CodeGen/AMDGPU/private-memory-atomics.ll | 16 +-
.../AMDGPU/promote-constOffset-to-imm.ll | 20 +-
llvm/test/CodeGen/AMDGPU/rem_i128.ll | 10 +-
llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll | 8 +-
llvm/test/CodeGen/AMDGPU/rsq.f64.ll | 586 ++---
llvm/test/CodeGen/AMDGPU/saddo.ll | 4 +-
llvm/test/CodeGen/AMDGPU/sdiv.ll | 20 +-
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 18 +-
.../AMDGPU/select-fabs-fneg-extract.f16.ll | 8 +-
.../AMDGPU/select-fabs-fneg-extract.v2f16.ll | 4 +-
.../select-nsz-known-values-to-fmin-fmax.ll | 52 +-
llvm/test/CodeGen/AMDGPU/select.f16.ll | 197 +-
llvm/test/CodeGen/AMDGPU/shift-i128.ll | 28 +-
llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll | 6 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 54 +-
llvm/test/CodeGen/AMDGPU/srem.ll | 124 +-
llvm/test/CodeGen/AMDGPU/srem64.ll | 18 +-
llvm/test/CodeGen/AMDGPU/ssubo.ll | 4 +-
llvm/test/CodeGen/AMDGPU/uaddo.ll | 29 +-
llvm/test/CodeGen/AMDGPU/udiv.ll | 62 +-
llvm/test/CodeGen/AMDGPU/udiv64.ll | 14 +-
llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | 6 +-
llvm/test/CodeGen/AMDGPU/urem64.ll | 16 +-
llvm/test/CodeGen/AMDGPU/usubo.ll | 17 +-
.../CodeGen/AMDGPU/vector-reduce-fmaximum.ll | 100 +-
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 100 +-
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 743 +++---
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 743 +++---
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 743 +++---
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 743 +++---
158 files changed, 13800 insertions(+), 13981 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 4b3754741f764..c41791618a623 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -810,6 +810,22 @@ void GCNSubtarget::adjustSchedDependency(
Dep.setLatency(InstrInfo.getSchedModel().computeOperandLatency(
DefI, DefOpIdx, UseI, UseOpIdx));
}
+
+ // Handle "fast-forward" cases for VALU dependencies via a lanemask-like SGPR:
+ // V_CMP* -> V_CNDMASK_B32
+ // V_ADD/SUB with carryout -> V_ADD/SUB with carryin (on GFX10+)
+ switch (UseI->getOpcode()) {
+ case AMDGPU::V_ADDC_U32_e64:
+ case AMDGPU::V_SUBB_U32_e64:
+ case AMDGPU::V_SUBBREV_U32_e64:
+ if (getGeneration() < GFX10)
+ break;
+ [[fallthrough]];
+ case AMDGPU::V_CNDMASK_B32_e64:
+ if (SIInstrInfo::isVALU(*DefI) &&
+ UseOpIdx == AMDGPU::getNamedOperandIdx(UseI->getOpcode(), AMDGPU::OpName::src2))
+ Dep.setLatency(0);
+ }
}
unsigned GCNSubtarget::getNSAThreshold(const MachineFunction &MF) const {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
index 25d70002a7a8e..81ab3ebdce068 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
@@ -58,8 +58,8 @@ define i32 @s_andn2_i1_vcc_multi_use(i32 %arg0, i32 %arg1) {
; WAVE64-LABEL: s_andn2_i1_vcc_multi_use:
; WAVE64: ; %bb.0:
; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1
; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; WAVE64-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1
; WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; WAVE64-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; WAVE64-NEXT: v_cndmask_b32_e64 v0, v0, 1, s[4:5]
@@ -68,8 +68,8 @@ define i32 @s_andn2_i1_vcc_multi_use(i32 %arg0, i32 %arg1) {
; WAVE32-LABEL: s_andn2_i1_vcc_multi_use:
; WAVE32: ; %bb.0:
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v1
; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; WAVE32-NEXT: v_cmp_ne_u32_e64 s4, 0, v1
; WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; WAVE32-NEXT: s_and_b32 s4, vcc_lo, s4
; WAVE32-NEXT: v_cndmask_b32_e64 v0, v0, 1, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
index fae3a75101ee5..6ed32aebce429 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
@@ -8,8 +8,8 @@ define hidden <2 x i64> @icmp_v2i32_sext_to_v2i64(<2 x i32> %arg) {
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 1
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 1
; CHECK-NEXT: v_bfe_i32 v2, v1, 0, 1
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v2
@@ -24,11 +24,11 @@ define hidden <2 x i64> @icmp_v2i32_zext_to_v2i64(<2 x i32> %arg) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq <2 x i32> %arg, zeroinitializer
%sext = zext <2 x i1> %cmp to <2 x i64>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 6fe6b526a7afe..25ad3dc053bbd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -1751,12 +1751,12 @@ define i65 @v_ashr_i65(i65 %value, i65 %amount) {
; GFX10-NEXT: v_or_b32_e32 v2, v6, v8
; GFX10-NEXT: v_or_b32_e32 v8, v7, v9
; GFX10-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5]
-; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v5
+; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v5
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v1, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v4, v1, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_ashr_i65:
@@ -1764,21 +1764,22 @@ define i65 @v_ashr_i65(i65 %value, i65 %amount) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_bfe_i32 v4, v2, 0, 1
; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v3
; GFX11-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX11-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5]
+; GFX11-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5]
; GFX11-NEXT: v_or_b32_e32 v2, v6, v8
; GFX11-NEXT: v_or_b32_e32 v8, v7, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v3
; GFX11-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5]
-; GFX11-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5]
-; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v5
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v8
+; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v1, s0
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v4, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = ashr i65 %value, %amount
ret i65 %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
index 0e32d307bfa71..814e6613d095d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
@@ -10,7 +10,6 @@ define void @main(<19 x i32> %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, 0
; GCN-NEXT: s_mov_b32 s12, s4
-; GCN-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s13, s4
; GCN-NEXT: v_mov_b32_e32 v4, s12
@@ -21,6 +20,7 @@ define void @main(<19 x i32> %arg) {
; GCN-NEXT: s_mov_b32 s9, s4
; GCN-NEXT: s_mov_b32 s10, s4
; GCN-NEXT: s_mov_b32 s11, s4
+; GCN-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_mov_b32_e32 v3, v1
@@ -34,10 +34,10 @@ define void @main(<19 x i32> %arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, s4
; GFX10-NEXT: v_mov_b32_e32 v2, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s7, s4
@@ -53,10 +53,10 @@ define void @main(<19 x i32> %arg) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_mov_b32 s1, s0
; GFX11-NEXT: v_mov_b32_e32 v2, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: v_mov_b32_e32 v3, v1
; GFX11-NEXT: s_mov_b32 s2, s0
; GFX11-NEXT: s_mov_b32 s3, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
index 547261f7d51b4..71b81097da556 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
@@ -243,35 +243,35 @@ define void @fcmp_f16_divergent(half %a, half %b, ptr %p) {
; GFX10-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX10-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX10-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX10-NEXT: flat_store_dword v[2:3], v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -291,52 +291,47 @@ define void @fcmp_f16_divergent(half %a, half %b, ptr %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX12-NEXT: flat_store_b32 v[2:3], v0
@@ -628,35 +623,35 @@ define void @fcmp_f32_divergent(float %a, float %b, ptr %p) {
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX10-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlg_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cmp_nle_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX10-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX10-NEXT: v_cmp_neq_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX10-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX10-NEXT: flat_store_dword v[2:3], v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -676,52 +671,47 @@ define void @fcmp_f32_divergent(float %a, float %b, ptr %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lg_f32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_nlg_f32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: v_cmp_nle_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: v_cmp_neq_f32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX12-NEXT: flat_store_b32 v[2:3], v0
@@ -1027,35 +1017,35 @@ define void @fcmp_f64_divergent(double %a, double %b, ptr %p) {
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ge_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX10-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX10-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_nlt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX10-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX10-NEXT: v_cmp_neq_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX10-NEXT: v_add3_u32 v0, v1, v7, v0
; GFX10-NEXT: flat_store_dword v[4:5], v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -1075,52 +1065,47 @@ define void @fcmp_f64_divergent(double %a, double %b, ptr %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lg_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX12-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX12-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_nlt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX12-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX12-NEXT: v_cmp_neq_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v7, v0
; GFX12-NEXT: flat_store_b32 v[4:5], v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
index 152bb9c91c618..4cbe23de18a2e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -1599,14 +1599,14 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) #1 {
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
-; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
-; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
+; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
+; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v5, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
@@ -3380,8 +3380,8 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e64 v4, -v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
@@ -3398,8 +3398,8 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e64 v4, -v0
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index b19216ae7bbc5..aa19d368e4ad1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -133,27 +133,27 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-NEXT: v_mov_b32_e32 v4, 0x800000
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v4
-; GFX6-NEXT: v_log_f32_e32 v1, v1
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT: v_log_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v6
-; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX6-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX6-NEXT: v_sub_f32_e32 v1, v1, v5
; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
; GFX6-NEXT: v_add_f32_e32 v0, v0, v7
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
; GFX6-NEXT: v_exp_f32_e32 v0, v0
; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
@@ -171,27 +171,27 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX8-NEXT: v_mov_b32_e32 v4, 0x800000
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GFX8-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX8-NEXT: v_ldexp_f32 v1, v1, v4
-; GFX8-NEXT: v_log_f32_e32 v1, v1
; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT: v_log_f32_e32 v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX8-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v5
; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
; GFX8-NEXT: v_add_f32_e32 v0, v0, v7
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
; GFX8-NEXT: v_exp_f32_e32 v0, v0
; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
@@ -209,27 +209,27 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX9-NEXT: v_mov_b32_e32 v4, 0x800000
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GFX9-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX9-NEXT: v_ldexp_f32 v1, v1, v4
-; GFX9-NEXT: v_log_f32_e32 v1, v1
; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT: v_log_f32_e32 v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
-; GFX9-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
-; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v5
; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
; GFX9-NEXT: v_add_f32_e32 v0, v0, v7
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
@@ -245,14 +245,14 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5
; GFX10-NEXT: v_ldexp_f32 v0, v0, v4
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_log_f32_e32 v1, v1
@@ -261,12 +261,12 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v1
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s4
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s4
; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: v_exp_f32_e32 v1, v1
@@ -278,9 +278,9 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, v1
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -296,21 +296,21 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
@@ -419,10 +419,10 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v4
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42800000
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v5, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v3
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[4:5]
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
@@ -559,10 +559,10 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v4
; GFX6-NEXT: v_mov_b32_e32 v5, 0x42800000
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v5, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v3
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_add_f32_e32 v2, v2, v4
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v3
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[4:5]
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
@@ -707,10 +707,10 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v4
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v4
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
@@ -855,10 +855,10 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v4
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v4
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
; GFX6-NEXT: v_exp_f32_e32 v2, v2
; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
index 63d04a535109a..f31ef85b2a7ca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
@@ -278,15 +278,15 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX11-LABEL: fptrunc_f64_to_f16_div:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-NEXT: v_bfe_u32 v2, v1, 20, 11
+; GFX11-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_sub_nc_u32_e32 v4, 1, v2
; GFX11-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -295,10 +295,10 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v5, v3, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v3, v3, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX11-NEXT: v_lshl_or_b32 v4, v2, 12, v0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-NEXT: v_lshl_or_b32 v4, v2, 12, v0
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX11-NEXT: v_or_b32_e32 v3, v5, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -312,11 +312,11 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX11-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
@@ -326,15 +326,15 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
;
; GFX12-LABEL: fptrunc_f64_to_f16_div:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX12-NEXT: v_bfe_u32 v2, v1, 20, 11
+; GFX12-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX12-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX12-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_sub_nc_u32_e32 v4, 1, v2
; GFX12-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -343,11 +343,11 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshrrev_b32_e32 v5, v3, v4
; GFX12-NEXT: v_lshlrev_b32_e32 v3, v3, v5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: v_lshl_or_b32 v4, v2, 12, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-NEXT: v_lshl_or_b32 v4, v2, 12, v0
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX12-NEXT: v_or_b32_e32 v3, v5, v3
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -363,12 +363,12 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX12-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX12-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX12-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -380,15 +380,15 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX1250-LABEL: fptrunc_f64_to_f16_div:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX1250-NEXT: v_bfe_u32 v2, v1, 20, 11
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
-; GFX1250-NEXT: v_dual_lshrrev_b32 v3, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_sub_nc_u32_e32 v4, 1, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_dual_lshrrev_b32 v1, 16, v1 :: v_dual_sub_nc_u32 v4, 1, v2
; GFX1250-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_med3_i32 v3, v4, 0, 13
@@ -396,10 +396,10 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_lshrrev_b32_e32 v5, v3, v4
; GFX1250-NEXT: v_lshlrev_b32_e32 v3, v3, v5
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX1250-NEXT: v_lshl_or_b32 v4, v2, 12, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX1250-NEXT: v_lshl_or_b32 v4, v2, 12, v0
; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX1250-NEXT: v_or_b32_e32 v3, v5, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -413,11 +413,11 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX1250-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
index 5f18c0cd2aca5..adf44b4ac1775 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
@@ -777,8 +777,8 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[4:5], 0
; CI-NEXT: v_mov_b32_e32 v2, 0x7ff80000
; CI-NEXT: v_cndmask_b32_e64 v3, v0, 0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; CI-NEXT: v_mov_b32_e32 v0, 0
+; CI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; CI-NEXT: v_mov_b32_e32 v1, 0x7ff00000
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[0:1]
; CI-NEXT: s_mov_b32 s2, -1
@@ -886,8 +886,8 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[4:5], 0
; VI-NEXT: v_mov_b32_e32 v2, 0x7ff80000
; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; VI-NEXT: v_mov_b32_e32 v0, 0
+; VI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; VI-NEXT: v_mov_b32_e32 v1, 0x7ff00000
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[0:1]
; VI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
@@ -3323,9 +3323,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; CI-NEXT: v_mov_b32_e32 v4, 0
; CI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
+; CI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
-; CI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; CI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5]
; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 8dafa36282c97..fd118548c6d20 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -6121,45 +6121,45 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX10-LABEL: v_fshl_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v17, 0x7f, v8
+; GFX10-NEXT: v_and_b32_e32 v16, 0x7f, v8
; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
-; GFX10-NEXT: v_bfi_b32 v18, v8, 0, 0x7f
-; GFX10-NEXT: v_lshrrev_b64 v[9:10], 1, v[6:7]
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, 64, v17
-; GFX10-NEXT: v_lshlrev_b64 v[7:8], v17, v[2:3]
-; GFX10-NEXT: v_add_nc_u32_e32 v15, 0xffffffc0, v17
+; GFX10-NEXT: v_bfi_b32 v17, v8, 0, 0x7f
+; GFX10-NEXT: v_lshrrev_b64 v[12:13], 1, v[6:7]
+; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v16
+; GFX10-NEXT: v_lshlrev_b64 v[8:9], v16, v[2:3]
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v16
+; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v17
; GFX10-NEXT: v_lshl_or_b32 v5, v6, 31, v5
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v18
-; GFX10-NEXT: v_lshrrev_b64 v[11:12], v11, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[13:14], v17, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
+; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[14:15], v16, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v16
+; GFX10-NEXT: v_lshrrev_b64 v[6:7], v17, v[4:5]
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v16
+; GFX10-NEXT: v_or_b32_e32 v10, v10, v8
+; GFX10-NEXT: v_or_b32_e32 v19, v11, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v11, 0xffffffc0, v17
+; GFX10-NEXT: v_lshlrev_b64 v[8:9], v18, v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v0, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[10:11], v11, v[12:13]
+; GFX10-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX10-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v1, v19, vcc_lo
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v17
-; GFX10-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v18
-; GFX10-NEXT: v_lshlrev_b64 v[15:16], v16, v[9:10]
-; GFX10-NEXT: v_or_b32_e32 v11, v11, v7
-; GFX10-NEXT: v_lshrrev_b64 v[6:7], v18, v[4:5]
-; GFX10-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v18
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v17, v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v8, v3, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v17
-; GFX10-NEXT: v_cndmask_b32_e32 v20, v0, v11, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[11:12], v19, v[9:10]
-; GFX10-NEXT: v_or_b32_e32 v0, v6, v15
-; GFX10-NEXT: v_or_b32_e32 v6, v7, v16
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18
-; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v11, v0, s5
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], v18, v[9:10]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v6, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v14, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v20, v2, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v1, s5
-; GFX10-NEXT: v_or_b32_e32 v0, v13, v4
-; GFX10-NEXT: v_or_b32_e32 v1, v9, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v7, v5, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v0, v14, v4
+; GFX10-NEXT: v_or_b32_e32 v1, v15, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -6167,48 +6167,51 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX11-LABEL: v_fshl_i128:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v17, 0x7f, v8
+; GFX11-NEXT: v_and_b32_e32 v16, 0x7f, v8
; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
-; GFX11-NEXT: v_bfi_b32 v18, v8, 0, 0x7f
-; GFX11-NEXT: v_lshrrev_b64 v[9:10], 1, v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v11, 64, v17
-; GFX11-NEXT: v_lshlrev_b64 v[7:8], v17, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v15, 0xffffffc0, v17
+; GFX11-NEXT: v_bfi_b32 v17, v8, 0, 0x7f
+; GFX11-NEXT: v_lshrrev_b64 v[12:13], 1, v[6:7]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b64 v[14:15], v16, v[0:1]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v16
+; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v17
; GFX11-NEXT: v_lshl_or_b32 v5, v6, 31, v5
-; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v18
-; GFX11-NEXT: v_lshrrev_b64 v[11:12], v11, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[13:14], v17, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v16
+; GFX11-NEXT: v_lshlrev_b64 v[8:9], v16, v[2:3]
+; GFX11-NEXT: v_dual_cndmask_b32 v14, 0, v14 :: v_dual_add_nc_u32 v7, 0xffffffc0, v16
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v16
+; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX11-NEXT: v_lshrrev_b64 v[6:7], v17, v[4:5]
+; GFX11-NEXT: v_or_b32_e32 v10, v10, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v19, v11, v9
+; GFX11-NEXT: v_add_nc_u32_e32 v11, 0xffffffc0, v17
+; GFX11-NEXT: v_lshlrev_b64 v[8:9], v18, v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v0, v10, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshrrev_b64 v[10:11], v11, v[12:13]
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v1, v19, vcc_lo
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v17
-; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v18
-; GFX11-NEXT: v_lshlrev_b64 v[15:16], v16, v[9:10]
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v7
-; GFX11-NEXT: v_lshrrev_b64 v[6:7], v18, v[4:5]
-; GFX11-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v18
-; GFX11-NEXT: v_cndmask_b32_e32 v20, v0, v11, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[11:12], v19, v[9:10]
-; GFX11-NEXT: v_or_b32_e32 v0, v6, v15
-; GFX11-NEXT: v_or_b32_e32 v6, v7, v16
-; GFX11-NEXT: v_cndmask_b32_e32 v7, v1, v8, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v17, v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v8, v3, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_cndmask_b32 v7, v11, v7
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v17
-; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v11, v0, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v18, v[9:10]
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, v6, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v9, 0, v14, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v20, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v4, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v13, v4
-; GFX11-NEXT: v_or_b32_e32 v1, v9, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v6, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v7, v5, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v0 :: v_dual_cndmask_b32 v7, 0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v14, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v15, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6377,104 +6380,104 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
;
; GFX10-LABEL: v_fshl_i128_ssv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_and_b32_e32 v11, 0x7f, v0
-; GFX10-NEXT: v_bfi_b32 v12, v0, 0, 0x7f
+; GFX10-NEXT: v_and_b32_e32 v9, 0x7f, v0
+; GFX10-NEXT: v_bfi_b32 v10, v0, 0, 0x7f
; GFX10-NEXT: s_mov_b32 s8, 0
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX10-NEXT: s_lshl_b32 s9, s6, 31
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 64, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v11
-; GFX10-NEXT: v_lshlrev_b64 v[1:2], v11, s[2:3]
-; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v12
-; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 64, v9
+; GFX10-NEXT: v_lshlrev_b64 v[1:2], v9, s[2:3]
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v9
+; GFX10-NEXT: v_lshlrev_b64 v[5:6], v9, s[0:1]
+; GFX10-NEXT: v_add_nc_u32_e32 v12, 0xffffffc0, v10
; GFX10-NEXT: v_lshrrev_b64 v[3:4], v3, s[0:1]
-; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v9
; GFX10-NEXT: v_lshlrev_b64 v[7:8], v7, s[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[5:6], v11, s[0:1]
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v13, 0xffffffc0, v12
-; GFX10-NEXT: v_or_b32_e32 v3, v3, v1
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], v12, s[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
+; GFX10-NEXT: s_or_b64 s[0:1], s[4:5], s[8:9]
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
+; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v4, v4, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
-; GFX10-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
-; GFX10-NEXT: v_or_b32_e32 v5, v0, v9
-; GFX10-NEXT: v_or_b32_e32 v9, v1, v10
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s1
-; GFX10-NEXT: v_lshrrev_b64 v[4:5], v12, s[6:7]
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
+; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v10
+; GFX10-NEXT: v_or_b32_e32 v11, v3, v1
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v10, s[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc_lo
+; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, s[4:5]
+; GFX10-NEXT: v_lshrrev_b64 v[4:5], v12, s[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v10
+; GFX10-NEXT: v_or_b32_e32 v11, v0, v2
+; GFX10-NEXT: v_or_b32_e32 v12, v1, v3
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v10, s[4:5]
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v9
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s3, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v4, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v5, s1
-; GFX10-NEXT: v_or_b32_e32 v0, v14, v0
-; GFX10-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX10-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX10-NEXT: v_or_b32_e32 v3, v8, v3
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v0, v13, v2
+; GFX10-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX10-NEXT: v_or_b32_e32 v2, v7, v4
+; GFX10-NEXT: v_or_b32_e32 v3, v8, v5
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_fshl_i128_ssv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e32 v11, 0x7f, v0
-; GFX11-NEXT: v_bfi_b32 v12, v0, 0, 0x7f
+; GFX11-NEXT: v_and_b32_e32 v9, 0x7f, v0
+; GFX11-NEXT: v_bfi_b32 v10, v0, 0, 0x7f
; GFX11-NEXT: s_mov_b32 s8, 0
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX11-NEXT: s_lshl_b32 s9, s6, 31
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], v11, s[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
-; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v12
-; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v14, 0, v5 :: v_dual_add_nc_u32 v13, 0xffffffc0, v12
-; GFX11-NEXT: v_sub_nc_u32_e32 v3, 64, v11
-; GFX11-NEXT: v_lshlrev_b64 v[1:2], v11, s[2:3]
-; GFX11-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
+; GFX11-NEXT: v_lshlrev_b64 v[5:6], v9, s[0:1]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v13, 0, v5 :: v_dual_add_nc_u32 v12, 0xffffffc0, v10
; GFX11-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 64, v9
+; GFX11-NEXT: v_lshlrev_b64 v[1:2], v9, s[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b64 v[3:4], v3, s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v4, v4, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v12, s[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v9
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v11, v3, v1
; GFX11-NEXT: v_lshlrev_b64 v[7:8], v7, s[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
-; GFX11-NEXT: v_or_b32_e32 v5, v0, v9
-; GFX11-NEXT: v_or_b32_e32 v9, v1, v10
-; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_cndmask_b32 v7, v7, v3
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
-; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 0, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_or_b64 s[0:1], s[4:5], s[8:9]
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v10, s[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, s[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], v12, s[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v10
+; GFX11-NEXT: v_or_b32_e32 v11, v0, v2
+; GFX11-NEXT: v_or_b32_e32 v12, v1, v3
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v10, s[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v11 :: v_dual_cndmask_b32 v5, v5, v12
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v9
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v5, s1
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], v12, s[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s3, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v1, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v5, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v14, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v3
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v3, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v4, 0, v0 :: v_dual_cndmask_b32 v5, 0, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v13, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX11-NEXT: v_or_b32_e32 v2, v7, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v3, v8, v5
; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
@@ -7914,179 +7917,174 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX10-LABEL: v_fshl_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v19, 0x7f, v16
+; GFX10-NEXT: v_and_b32_e32 v25, 0x7f, v16
; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
-; GFX10-NEXT: v_bfi_b32 v29, v16, 0, 0x7f
-; GFX10-NEXT: v_sub_nc_u32_e32 v21, 64, v19
-; GFX10-NEXT: v_add_nc_u32_e32 v25, 0xffffffc0, v19
-; GFX10-NEXT: v_lshlrev_b64 v[23:24], v19, v[2:3]
+; GFX10-NEXT: v_bfi_b32 v26, v16, 0, 0x7f
+; GFX10-NEXT: v_lshrrev_b64 v[12:13], 1, v[12:13]
+; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v25
+; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
+; GFX10-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v25
; GFX10-NEXT: v_lshl_or_b32 v9, v10, 31, v9
; GFX10-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
-; GFX10-NEXT: v_lshrrev_b64 v[21:22], v21, v[0:1]
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v29
-; GFX10-NEXT: v_lshlrev_b64 v[17:18], v19, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v25, v[0:1]
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19
-; GFX10-NEXT: v_lshrrev_b64 v[25:26], v29, v[8:9]
-; GFX10-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX10-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v29
-; GFX10-NEXT: v_lshlrev_b64 v[27:28], v16, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v30, 0, v17, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v19
+; GFX10-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
+; GFX10-NEXT: v_sub_nc_u32_e32 v19, 64, v26
+; GFX10-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
+; GFX10-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
+; GFX10-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX10-NEXT: v_or_b32_e32 v22, v18, v22
+; GFX10-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
+; GFX10-NEXT: v_lshlrev_b64 v[18:19], v19, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
-; GFX10-NEXT: v_or_b32_e32 v0, v22, v24
-; GFX10-NEXT: v_lshrrev_b64 v[16:17], v23, v[10:11]
-; GFX10-NEXT: v_or_b32_e32 v19, v25, v27
-; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v29
-; GFX10-NEXT: v_or_b32_e32 v22, v26, v28
-; GFX10-NEXT: v_cndmask_b32_e32 v23, v1, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v29
-; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v19, s5
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], v29, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v17, v22, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v23, v3, s4
-; GFX10-NEXT: v_and_b32_e32 v23, 0x7f, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v21, v2, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v10, v9, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v23
+; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX10-NEXT: v_or_b32_e32 v17, v17, v19
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
+; GFX10-NEXT: v_and_b32_e32 v18, 0x7f, v20
+; GFX10-NEXT: v_lshrrev_b64 v[10:11], v26, v[10:11]
+; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v16, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v21, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v17, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v19, v22, v3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 64, v18
+; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, v10, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v21, 0, v11, s4
+; GFX10-NEXT: v_lshlrev_b64 v[10:11], v18, v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v3, v[4:5]
; GFX10-NEXT: v_bfi_b32 v20, v20, 0, 0x7f
-; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, v0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, v1, s5
-; GFX10-NEXT: v_or_b32_e32 v0, v30, v2
-; GFX10-NEXT: v_or_b32_e32 v1, v18, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v23
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], v10, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[10:11], v23, v[6:7]
-; GFX10-NEXT: v_lshl_or_b32 v9, v14, 31, v9
+; GFX10-NEXT: v_lshl_or_b32 v13, v14, 31, v13
; GFX10-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX10-NEXT: v_lshlrev_b64 v[12:13], v23, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
-; GFX10-NEXT: v_or_b32_e32 v10, v2, v10
-; GFX10-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v20
-; GFX10-NEXT: v_lshrrev_b64 v[16:17], v20, v[8:9]
-; GFX10-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX10-NEXT: v_or_b32_e32 v2, v21, v24
-; GFX10-NEXT: v_or_b32_e32 v11, v3, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v4, v10, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[3:4], v26, v[14:15]
-; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v20
-; GFX10-NEXT: v_or_b32_e32 v10, v16, v18
-; GFX10-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v23
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v10, s5
-; GFX10-NEXT: v_lshrrev_b64 v[10:11], v20, v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v21, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v3, v8, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v4, v9, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v10, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v11, s5
-; GFX10-NEXT: v_or_b32_e32 v3, v22, v25
-; GFX10-NEXT: v_or_b32_e32 v4, v12, v5
-; GFX10-NEXT: v_or_b32_e32 v5, v13, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffc0, v18
+; GFX10-NEXT: v_or_b32_e32 v2, v2, v16
+; GFX10-NEXT: v_or_b32_e32 v22, v8, v10
+; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v20
+; GFX10-NEXT: v_lshlrev_b64 v[16:17], v18, v[4:5]
+; GFX10-NEXT: v_or_b32_e32 v0, v23, v0
+; GFX10-NEXT: v_or_b32_e32 v23, v9, v11
+; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
+; GFX10-NEXT: v_add_nc_u32_e32 v5, 0xffffffc0, v20
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v20, v[12:13]
+; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, v[14:15]
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
+; GFX10-NEXT: v_or_b32_e32 v1, v24, v1
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v25, 0, v17, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[16:17], v5, v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v22, v3, v22, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v5, v8, v10
+; GFX10-NEXT: v_or_b32_e32 v8, v9, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v4, v23, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v20
+; GFX10-NEXT: v_lshrrev_b64 v[3:4], v20, v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v22, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v20
+; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v13, s4
+; GFX10-NEXT: v_or_b32_e32 v3, v19, v21
; GFX10-NEXT: v_or_b32_e32 v6, v6, v9
; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX10-NEXT: v_or_b32_e32 v4, v24, v5
+; GFX10-NEXT: v_or_b32_e32 v5, v25, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_v2i128:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v16
+; GFX11-NEXT: v_and_b32_e32 v25, 0x7f, v16
; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
-; GFX11-NEXT: v_bfi_b32 v29, v16, 0, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[17:18], v19, v[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19
+; GFX11-NEXT: v_bfi_b32 v26, v16, 0, 0x7f
+; GFX11-NEXT: v_lshrrev_b64 v[12:13], 1, v[12:13]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_sub_nc_u32_e32 v17, 64, v25
+; GFX11-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
; GFX11-NEXT: v_lshl_or_b32 v9, v10, 31, v9
; GFX11-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
-; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v29
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v29
-; GFX11-NEXT: v_cndmask_b32_e32 v30, 0, v17, vcc_lo
-; GFX11-NEXT: v_sub_nc_u32_e32 v21, 64, v19
-; GFX11-NEXT: v_dual_cndmask_b32 v18, 0, v18 :: v_dual_add_nc_u32 v25, 0xffffffc0, v19
-; GFX11-NEXT: v_lshlrev_b64 v[23:24], v19, v[2:3]
-; GFX11-NEXT: v_lshlrev_b64 v[27:28], v16, v[10:11]
+; GFX11-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
+; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v25
+; GFX11-NEXT: v_sub_nc_u32_e32 v19, 64, v26
+; GFX11-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
+; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v26
+; GFX11-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
+; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX11-NEXT: v_or_b32_e32 v22, v18, v22
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
+; GFX11-NEXT: v_lshlrev_b64 v[18:19], v19, v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshrrev_b64 v[21:22], v21, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v25, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], v29, v[8:9]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v19
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v29
-; GFX11-NEXT: v_or_b32_e32 v19, v25, v27
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v0, v22, v24
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v23, v[10:11]
-; GFX11-NEXT: v_or_b32_e32 v22, v26, v28
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e32 v23, v1, v0, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v29
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v19, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v29, v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v17, v22, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v23, v3, s0
-; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v8, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v24, 0, v24 :: v_dual_cndmask_b32 v21, v0, v21
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
+; GFX11-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX11-NEXT: v_or_b32_e32 v17, v17, v19
+; GFX11-NEXT: v_and_b32_e32 v18, 0x7f, v20
+; GFX11-NEXT: v_lshrrev_b64 v[10:11], v26, v[10:11]
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v21, v2 :: v_dual_cndmask_b32 v19, v22, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v16, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v17, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 64, v18
+; GFX11-NEXT: v_cndmask_b32_e64 v16, 0, v10, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v21, 0, v11, s0
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v18, v[6:7]
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_cndmask_b32 v1, v1, v9
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v3, v[4:5]
; GFX11-NEXT: v_bfi_b32 v20, v20, 0, 0x7f
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v10, v9, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v23
-; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v25, 0, v1, s1
-; GFX11-NEXT: v_or_b32_e32 v0, v30, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v23
-; GFX11-NEXT: v_lshl_or_b32 v9, v14, 31, v9
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v16
+; GFX11-NEXT: v_lshlrev_b64 v[16:17], v18, v[4:5]
+; GFX11-NEXT: v_lshl_or_b32 v13, v14, 31, v13
; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
-; GFX11-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v20
-; GFX11-NEXT: v_or_b32_e32 v1, v18, v3
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v10, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[10:11], v23, v[6:7]
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX11-NEXT: v_lshlrev_b64 v[12:13], v23, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[8:9]
-; GFX11-NEXT: v_or_b32_e32 v10, v2, v10
-; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX11-NEXT: v_or_b32_e32 v2, v21, v24
-; GFX11-NEXT: v_or_b32_e32 v11, v3, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v21, v4, v10
-; GFX11-NEXT: v_lshrrev_b64 v[3:4], v26, v[14:15]
-; GFX11-NEXT: v_or_b32_e32 v10, v16, v18
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
-; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
-; GFX11-NEXT: v_lshrrev_b64 v[10:11], v20, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v8, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v4, v9, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v10, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v11, s1
-; GFX11-NEXT: v_or_b32_e32 v3, v22, v25
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v13, v8
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffc0, v18
+; GFX11-NEXT: v_or_b32_e32 v22, v8, v10
+; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v20
+; GFX11-NEXT: v_or_b32_e32 v1, v24, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v24, 0, v16, vcc_lo
+; GFX11-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
+; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
+; GFX11-NEXT: v_or_b32_e32 v23, v9, v11
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffc0, v20
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[12:13]
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v10, v[14:15]
+; GFX11-NEXT: v_dual_cndmask_b32 v25, 0, v17 :: v_dual_cndmask_b32 v22, v3, v22
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v5, v[14:15]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v18
+; GFX11-NEXT: v_or_b32_e32 v5, v8, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v9, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v4, v23, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v20
+; GFX11-NEXT: v_lshrrev_b64 v[3:4], v20, v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v22, v6, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v16, v5 :: v_dual_cndmask_b32 v8, v17, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, v7, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v20
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v12, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v13, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v9, 0, v3, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v3, v19, v21
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_or_b32_e32 v4, v24, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v25, v8
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 7623c8b8aad57..02139b918ec19 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -5881,102 +5881,100 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX10-NEXT: v_bfi_b32 v18, v8, 0, 0x7f
+; GFX10-NEXT: v_bfi_b32 v15, v8, 0, 0x7f
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 31, v1
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX10-NEXT: v_and_b32_e32 v19, 0x7f, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v18
+; GFX10-NEXT: v_and_b32_e32 v16, 0x7f, v8
+; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v15
; GFX10-NEXT: v_or_b32_e32 v2, v2, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v14, 0xffffffc0, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19
-; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1]
-; GFX10-NEXT: v_lshrrev_b64 v[8:9], v10, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
-; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7]
-; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v19
+; GFX10-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v15
+; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v16
+; GFX10-NEXT: v_lshlrev_b64 v[13:14], v15, v[0:1]
+; GFX10-NEXT: v_lshrrev_b64 v[9:10], v10, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[11:12], v15, v[2:3]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v15
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v15
+; GFX10-NEXT: v_or_b32_e32 v18, v9, v11
+; GFX10-NEXT: v_or_b32_e32 v19, v10, v12
+; GFX10-NEXT: v_add_nc_u32_e32 v12, 0xffffffc0, v16
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v16, v[4:5]
+; GFX10-NEXT: v_lshlrev_b64 v[10:11], v17, v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v17, 0, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[12:13], v12, v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v0, v18, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v8, v8, v10
-; GFX10-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v19
-; GFX10-NEXT: v_or_b32_e32 v11, v9, v11
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v18
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v19
-; GFX10-NEXT: v_cndmask_b32_e32 v20, v0, v8, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[8:9], v10, v[6:7]
-; GFX10-NEXT: v_or_b32_e32 v0, v14, v16
-; GFX10-NEXT: v_or_b32_e32 v10, v15, v17
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v20, v2, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s5
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v10, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s5
-; GFX10-NEXT: v_or_b32_e32 v0, v12, v4
-; GFX10-NEXT: v_or_b32_e32 v1, v7, v5
+; GFX10-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v1, v19, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v16
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v16, v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v10, v3, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v13, v9, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v7, v5, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v0, v17, v4
+; GFX10-NEXT: v_or_b32_e32 v1, v14, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_i128:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: v_bfi_b32 v18, v8, 0, 0x7f
+; GFX11-NEXT: v_bfi_b32 v15, v8, 0, 0x7f
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 31, v1
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v15
; GFX11-NEXT: v_or_b32_e32 v2, v2, v9
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v19
-; GFX11-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], v10, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3]
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v19
-; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v11, v9, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v14, 0xffffffc0, v18
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b64 v[13:14], v15, v[0:1]
+; GFX11-NEXT: v_and_b32_e32 v16, 0x7f, v8
+; GFX11-NEXT: v_lshrrev_b64 v[9:10], v10, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[11:12], v15, v[2:3]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v15
+; GFX11-NEXT: v_sub_nc_u32_e32 v17, 64, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v18, v9, v11
+; GFX11-NEXT: v_or_b32_e32 v19, v10, v12
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v17, v[6:7]
+; GFX11-NEXT: v_dual_cndmask_b32 v17, 0, v13 :: v_dual_add_nc_u32 v12, 0xffffffc0, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b64 v[12:13], v12, v[6:7]
+; GFX11-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v15
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v16, v[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v0, v18, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v8, v8, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v19
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e32 v20, v0, v8, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], v10, v[6:7]
-; GFX11-NEXT: v_or_b32_e32 v0, v14, v16
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v10, v15, v17
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v20, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v0, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v10, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v4, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v1, s1
-; GFX11-NEXT: v_or_b32_e32 v0, v12, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v1, v7, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v1, v19, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v16
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v16, v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v10, v3, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v12, v8 :: v_dual_cndmask_b32 v7, v13, v9
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v6, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v7, v5, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v0 :: v_dual_cndmask_b32 v7, 0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v17, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v14, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result
@@ -6140,98 +6138,98 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
;
; GFX10-LABEL: v_fshr_i128_ssv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_bfi_b32 v11, v0, 0, 0x7f
-; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], 1
-; GFX10-NEXT: s_lshr_b32 s2, s1, 31
-; GFX10-NEXT: v_and_b32_e32 v12, 0x7f, v0
+; GFX10-NEXT: v_bfi_b32 v9, v0, 0, 0x7f
+; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX10-NEXT: s_lshr_b32 s8, s1, 31
+; GFX10-NEXT: v_and_b32_e32 v10, 0x7f, v0
+; GFX10-NEXT: s_or_b32 s2, s2, s8
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 64, v9
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, 64, v11
-; GFX10-NEXT: s_or_b32 s8, s8, s2
-; GFX10-NEXT: v_add_nc_u32_e32 v0, 0xffffffc0, v11
-; GFX10-NEXT: v_lshlrev_b64 v[3:4], v11, s[8:9]
-; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v12
-; GFX10-NEXT: v_lshrrev_b64 v[1:2], v1, s[0:1]
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v13, 0xffffffc0, v12
-; GFX10-NEXT: v_lshrrev_b64 v[7:8], v12, s[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
-; GFX10-NEXT: v_lshlrev_b64 v[5:6], v11, s[0:1]
-; GFX10-NEXT: v_or_b32_e32 v3, v1, v3
+; GFX10-NEXT: v_lshlrev_b64 v[1:2], v9, s[2:3]
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 0xffffffc0, v9
+; GFX10-NEXT: v_sub_nc_u32_e32 v7, 64, v10
+; GFX10-NEXT: v_lshrrev_b64 v[3:4], v3, s[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[5:6], v9, s[0:1]
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v9
+; GFX10-NEXT: v_lshlrev_b64 v[7:8], v7, s[6:7]
+; GFX10-NEXT: v_or_b32_e32 v11, v3, v1
+; GFX10-NEXT: v_or_b32_e32 v12, v4, v2
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]
-; GFX10-NEXT: v_or_b32_e32 v4, v2, v4
-; GFX10-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v12
-; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v14, v0, v3, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
-; GFX10-NEXT: v_or_b32_e32 v0, v7, v9
-; GFX10-NEXT: v_or_b32_e32 v7, v8, v10
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v4, 0xffffffc0, v10
+; GFX10-NEXT: v_lshrrev_b64 v[2:3], v10, s[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s1
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], v12, s[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v14, s8, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s9, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s5, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v0, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v1, s1
-; GFX10-NEXT: v_or_b32_e32 v0, v5, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v9
+; GFX10-NEXT: v_lshrrev_b64 v[4:5], v4, s[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v0, v11, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v2, v2, v7
+; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v12, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v10
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v10, s[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v11, s2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v7, s3, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s5, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v0, v13, v2
; GFX10-NEXT: v_or_b32_e32 v1, v6, v3
-; GFX10-NEXT: v_or_b32_e32 v2, v7, v8
-; GFX10-NEXT: v_or_b32_e32 v3, v4, v9
+; GFX10-NEXT: v_or_b32_e32 v2, v4, v7
+; GFX10-NEXT: v_or_b32_e32 v3, v5, v8
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_fshr_i128_ssv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_bfi_b32 v11, v0, 0, 0x7f
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], 1
-; GFX11-NEXT: s_lshr_b32 s2, s1, 31
+; GFX11-NEXT: v_bfi_b32 v9, v0, 0, 0x7f
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshr_b32 s8, s1, 31
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_or_b32 s8, s8, s2
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, 64, v11
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], v11, s[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0x7f, v0
-; GFX11-NEXT: v_lshlrev_b64 v[3:4], v11, s[8:9]
-; GFX11-NEXT: v_lshrrev_b64 v[1:2], v1, s[0:1]
-; GFX11-NEXT: v_dual_cndmask_b32 v5, 0, v5 :: v_dual_add_nc_u32 v0, 0xffffffc0, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v12
-; GFX11-NEXT: v_lshrrev_b64 v[7:8], v12, s[4:5]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v12
-; GFX11-NEXT: v_or_b32_e32 v3, v1, v3
+; GFX11-NEXT: s_or_b32 s2, s2, s8
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 64, v9
+; GFX11-NEXT: v_lshlrev_b64 v[1:2], v9, s[2:3]
+; GFX11-NEXT: v_lshlrev_b64 v[5:6], v9, s[0:1]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v9
+; GFX11-NEXT: v_and_b32_e32 v10, 0x7f, v0
+; GFX11-NEXT: v_lshrrev_b64 v[3:4], v3, s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 64, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v12, v4, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 0xffffffc0, v9
+; GFX11-NEXT: v_or_b32_e32 v11, v3, v1
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v10, s[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[7:8], v7, s[6:7]
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 0xffffffc0, v12
-; GFX11-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
-; GFX11-NEXT: v_or_b32_e32 v4, v2, v4
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v14, v0, v3, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
-; GFX11-NEXT: v_or_b32_e32 v0, v7, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v8, v10
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffc0, v10
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v0, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v12, s[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v14, s8, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s9, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s5, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v1, s1
-; GFX11-NEXT: v_or_b32_e32 v0, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v7
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v0, v11, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], v4, s[6:7]
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v6 :: v_dual_cndmask_b32 v7, v1, v12
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v10
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v10, s[6:7]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v11, s2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v7, s3, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s5, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v13, v2
; GFX11-NEXT: v_or_b32_e32 v1, v6, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v7, v8
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v9
+; GFX11-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
@@ -7618,8 +7616,8 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-NEXT: v_lshlrev_b64 v[16:17], v23, v[17:18]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[4:5]
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, v[10:11]
-; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v26
; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc
+; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v26
; GFX9-NEXT: v_cndmask_b32_e64 v18, v0, v21, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v21, v1, v22, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc
@@ -7694,76 +7692,76 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX10-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1]
-; GFX10-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
-; GFX10-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v25
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v26
; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
-; GFX10-NEXT: v_or_b32_e32 v22, v18, v22
+; GFX10-NEXT: v_or_b32_e32 v16, v17, v21
+; GFX10-NEXT: v_or_b32_e32 v21, v18, v22
; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v26
-; GFX10-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX10-NEXT: v_cndmask_b32_e32 v22, 0, v23, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v26
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
-; GFX10-NEXT: v_bfi_b32 v25, v20, 0, 0x7f
-; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v26
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v3, s4
-; GFX10-NEXT: v_and_b32_e32 v20, 0x7f, v20
+; GFX10-NEXT: v_cndmask_b32_e32 v21, v1, v21, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
; GFX10-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v21, v2, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v25, v0, v2, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v23, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v21, v3, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v26
; GFX10-NEXT: v_or_b32_e32 v17, v17, v19
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v26
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_lshrrev_b32_e32 v10, 31, v5
+; GFX10-NEXT: v_bfi_b32 v19, v20, 0, 0x7f
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
-; GFX10-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v25
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s4
-; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v25
; GFX10-NEXT: v_or_b32_e32 v6, v6, v10
+; GFX10-NEXT: v_and_b32_e32 v20, 0x7f, v20
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s4
+; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v19
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v26, 0, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v27, 0, v3, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], v8, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[8:9], v25, v[6:7]
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX10-NEXT: v_lshlrev_b64 v[10:11], v25, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX10-NEXT: v_or_b32_e32 v0, v23, v0
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
-; GFX10-NEXT: v_or_b32_e32 v8, v2, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v20
-; GFX10-NEXT: v_lshrrev_b64 v[16:17], v20, v[12:13]
-; GFX10-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX10-NEXT: v_or_b32_e32 v2, v21, v26
-; GFX10-NEXT: v_or_b32_e32 v9, v3, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v4, v8, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15]
-; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v20
-; GFX10-NEXT: v_or_b32_e32 v8, v16, v18
-; GFX10-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v25
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s5
-; GFX10-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v21, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v3, v12, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v4, v13, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v8, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v9, s5
+; GFX10-NEXT: v_lshlrev_b64 v[10:11], v19, v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v21, 0, v3, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v0, v22, v0
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffc0, v19
+; GFX10-NEXT: v_lshlrev_b64 v[16:17], v19, v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19
; GFX10-NEXT: v_or_b32_e32 v1, v24, v1
-; GFX10-NEXT: v_or_b32_e32 v3, v22, v27
-; GFX10-NEXT: v_or_b32_e32 v4, v10, v5
-; GFX10-NEXT: v_or_b32_e32 v5, v11, v12
-; GFX10-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX10-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX10-NEXT: v_or_b32_e32 v22, v8, v10
+; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v20
+; GFX10-NEXT: v_or_b32_e32 v23, v9, v11
+; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
+; GFX10-NEXT: v_add_nc_u32_e32 v5, 0xffffffc0, v20
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v20, v[12:13]
+; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, v[14:15]
+; GFX10-NEXT: v_or_b32_e32 v2, v25, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v25, 0, v17, vcc_lo
+; GFX10-NEXT: v_lshrrev_b64 v[16:17], v5, v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v22, v3, v22, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v5, v8, v10
+; GFX10-NEXT: v_or_b32_e32 v8, v9, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v4, v23, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v20
+; GFX10-NEXT: v_lshrrev_b64 v[3:4], v20, v[14:15]
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v19
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v22, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v20
+; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v13, s4
+; GFX10-NEXT: v_or_b32_e32 v3, v18, v21
+; GFX10-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX10-NEXT: v_or_b32_e32 v4, v24, v5
+; GFX10-NEXT: v_or_b32_e32 v5, v25, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_v2i128:
@@ -7779,86 +7777,83 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
; GFX11-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1]
-; GFX11-NEXT: v_and_b32_e32 v26, 0x7f, v16
+; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v25
; GFX11-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v25
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
-; GFX11-NEXT: v_dual_cndmask_b32 v23, 0, v23 :: v_dual_cndmask_b32 v24, 0, v24
-; GFX11-NEXT: v_bfi_b32 v25, v20, 0, 0x7f
-; GFX11-NEXT: v_or_b32_e32 v22, v18, v22
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v26
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX11-NEXT: v_and_b32_e32 v26, 0x7f, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v16, v17, v21
+; GFX11-NEXT: v_or_b32_e32 v21, v18, v22
+; GFX11-NEXT: v_cndmask_b32_e32 v22, 0, v23, vcc_lo
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v1, v21, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v26
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_add_nc_u32 v23, 0xffffffc0, v26
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
-; GFX11-NEXT: v_and_b32_e32 v20, 0x7f, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_cndmask_b32 v21, v0, v21 :: v_dual_cndmask_b32 v22, v1, v22
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v26
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v26
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v0, v2, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v23, v[10:11]
; GFX11-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
; GFX11-NEXT: v_or_b32_e32 v17, v17, v19
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v22, v3, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v26
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
+; GFX11-NEXT: v_bfi_b32 v19, v20, 0, 0x7f
+; GFX11-NEXT: v_and_b32_e32 v20, 0x7f, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v21, v3, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v26
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 31, v5
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17
-; GFX11-NEXT: v_cndmask_b32_e32 v26, 0, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v6, v6, v10
-; GFX11-NEXT: v_cndmask_b32_e32 v27, 0, v3, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v21, 0, v3
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v8, s0
-; GFX11-NEXT: v_sub_nc_u32_e32 v8, 64, v25
+; GFX11-NEXT: v_sub_nc_u32_e32 v8, 64, v19
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
-; GFX11-NEXT: v_lshlrev_b64 v[10:11], v25, v[4:5]
-; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v8, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[8:9], v25, v[6:7]
-; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v20
-; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
-; GFX11-NEXT: v_or_b32_e32 v8, v2, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v25
-; GFX11-NEXT: v_or_b32_e32 v2, v21, v26
-; GFX11-NEXT: v_or_b32_e32 v9, v3, v9
-; GFX11-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v19, v[6:7]
+; GFX11-NEXT: v_lshlrev_b64 v[16:17], v19, v[4:5]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
+; GFX11-NEXT: v_or_b32_e32 v0, v22, v0
+; GFX11-NEXT: v_or_b32_e32 v2, v25, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffc0, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v25, 0, v17, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v1, v24, v1
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[12:13]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v8, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15]
-; GFX11-NEXT: v_or_b32_e32 v8, v16, v18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
+; GFX11-NEXT: v_or_b32_e32 v22, v8, v10
+; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v20
+; GFX11-NEXT: v_or_b32_e32 v23, v9, v11
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e32 v24, 0, v16, vcc_lo
+; GFX11-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffc0, v20
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v10, v[14:15]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v19
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v5, v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v3, v22, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v5, v8, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v9, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v4, v23, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v20
+; GFX11-NEXT: v_lshrrev_b64 v[3:4], v20, v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v22, v6, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, v7, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v16, v5 :: v_dual_cndmask_b32 v8, v17, v8
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v20
+; GFX11-NEXT: v_dual_cndmask_b32 v9, 0, v3 :: v_dual_cndmask_b32 v10, 0, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v12, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v12, s2
-; GFX11-NEXT: v_or_b32_e32 v3, v22, v27
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v4, v13, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v8, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v9, s1
-; GFX11-NEXT: v_or_b32_e32 v4, v10, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v5, v11, v12
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v13, s0
+; GFX11-NEXT: v_or_b32_e32 v3, v18, v21
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_or_b32_e32 v4, v24, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v25, v8
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
index 4cc8d6536efe0..af51c272c0398 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
@@ -233,36 +233,33 @@ define void @icmp_i16_divergent(i16 %a, i16 %b, ptr addrspace(1) %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_i16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: v_cmp_le_i16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: v_cmp_lt_u16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: v_cmp_le_u16_e32 vcc_lo, v0.l, v1.l
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.l, v1.l
-; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX12-NEXT: global_store_b32 v[2:3], v0, off
@@ -518,36 +515,33 @@ define void @icmp_i32_divergent(i32 %a, i32 %b, ptr addrspace(1) %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v6, v7
; GFX12-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v4, v4, v5, v8
; GFX12-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX12-NEXT: global_store_b32 v[2:3], v0, off
@@ -590,13 +584,10 @@ define void @icmp_i64_divergent(i64 %a, i64 %b, ptr addrspace(1) %p) {
; HAWAII: ; %bb.0:
; HAWAII-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; HAWAII-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b32 s6, 0
; HAWAII-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; HAWAII-NEXT: v_cmp_ne_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b32 s7, 0xf000
; HAWAII-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; HAWAII-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b64 s[4:5], 0
; HAWAII-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; HAWAII-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; HAWAII-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
@@ -621,6 +612,9 @@ define void @icmp_i64_divergent(i64 %a, i64 %b, ptr addrspace(1) %p) {
; HAWAII-NEXT: v_add_i32_e32 v1, vcc, v1, v13
; HAWAII-NEXT: v_add_i32_e32 v1, vcc, v1, v14
; HAWAII-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; HAWAII-NEXT: s_mov_b32 s6, 0
+; HAWAII-NEXT: s_mov_b32 s7, 0xf000
+; HAWAII-NEXT: s_mov_b64 s[4:5], 0
; HAWAII-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64
; HAWAII-NEXT: s_waitcnt vmcnt(0)
; HAWAII-NEXT: s_setpc_b64 s[30:31]
@@ -639,36 +633,33 @@ define void @icmp_i64_divergent(i64 %a, i64 %b, ptr addrspace(1) %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: v_cmp_le_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v6, v6, v8, v9
; GFX12-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v6, v6, v7, v10
; GFX12-NEXT: v_cmp_le_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v7, v0
; GFX12-NEXT: global_store_b32 v[4:5], v0, off
@@ -857,20 +848,19 @@ define void @icmp_p3_divergent(ptr addrspace(3) %a, ptr addrspace(3) %b, ptr add
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX12-NEXT: global_store_b32 v[2:3], v0, off
@@ -1046,20 +1036,19 @@ define void @icmp_p5_divergent(ptr addrspace(5) %a, ptr addrspace(5) %b, ptr add
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX12-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v4, v6, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v5, v0
; GFX12-NEXT: global_store_b32 v[2:3], v0, off
@@ -1212,13 +1201,10 @@ define void @icmp_p0_divergent(ptr %a, ptr %b, ptr addrspace(1) %p) {
; HAWAII: ; %bb.0:
; HAWAII-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; HAWAII-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b32 s6, 0
; HAWAII-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; HAWAII-NEXT: v_cmp_ne_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b32 s7, 0xf000
; HAWAII-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; HAWAII-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b64 s[4:5], 0
; HAWAII-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; HAWAII-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; HAWAII-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
@@ -1231,6 +1217,9 @@ define void @icmp_p0_divergent(ptr %a, ptr %b, ptr addrspace(1) %p) {
; HAWAII-NEXT: v_add_i32_e32 v1, vcc, v1, v9
; HAWAII-NEXT: v_add_i32_e32 v1, vcc, v1, v10
; HAWAII-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; HAWAII-NEXT: s_mov_b32 s6, 0
+; HAWAII-NEXT: s_mov_b32 s7, 0xf000
+; HAWAII-NEXT: s_mov_b64 s[4:5], 0
; HAWAII-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64
; HAWAII-NEXT: s_waitcnt vmcnt(0)
; HAWAII-NEXT: s_setpc_b64 s[30:31]
@@ -1249,20 +1238,19 @@ define void @icmp_p0_divergent(ptr %a, ptr %b, ptr addrspace(1) %p) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: v_cmp_le_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v7, v0
; GFX12-NEXT: global_store_b32 v[4:5], v0, off
@@ -1413,13 +1401,10 @@ define void @icmp_p1_divergent(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr add
; HAWAII: ; %bb.0:
; HAWAII-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; HAWAII-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b32 s6, 0
; HAWAII-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; HAWAII-NEXT: v_cmp_ne_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b32 s7, 0xf000
; HAWAII-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; HAWAII-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
-; HAWAII-NEXT: s_mov_b64 s[4:5], 0
; HAWAII-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; HAWAII-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; HAWAII-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
@@ -1432,6 +1417,9 @@ define void @icmp_p1_divergent(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr add
; HAWAII-NEXT: v_add_i32_e32 v1, vcc, v1, v9
; HAWAII-NEXT: v_add_i32_e32 v1, vcc, v1, v10
; HAWAII-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; HAWAII-NEXT: s_mov_b32 s6, 0
+; HAWAII-NEXT: s_mov_b32 s7, 0xf000
+; HAWAII-NEXT: s_mov_b64 s[4:5], 0
; HAWAII-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64
; HAWAII-NEXT: s_waitcnt vmcnt(0)
; HAWAII-NEXT: s_setpc_b64 s[30:31]
@@ -1450,20 +1438,19 @@ define void @icmp_p1_divergent(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr add
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX12-NEXT: v_cmp_le_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: v_add3_u32 v1, v6, v8, v9
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add3_u32 v0, v1, v7, v0
; GFX12-NEXT: global_store_b32 v[4:5], v0, off
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
index 9528752b76a8e..42e7efed84749 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
@@ -1272,9 +1272,9 @@ define amdgpu_ps void @insertelement_v_v4i16_s_v(ptr addrspace(1) %ptr, i16 inre
; GFX9-NEXT: v_lshlrev_b32_e32 v2, v2, v5
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX9-NEXT: v_not_b32_e32 v2, v2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
; GFX9-NEXT: v_and_or_b32 v2, v5, v2, v7
@@ -1294,9 +1294,9 @@ define amdgpu_ps void @insertelement_v_v4i16_s_v(ptr addrspace(1) %ptr, i16 inre
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX8-NEXT: v_lshlrev_b32_e64 v7, v2, s0
; GFX8-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
; GFX8-NEXT: v_bfi_b32 v2, v2, 0, v5
@@ -1319,8 +1319,8 @@ define amdgpu_ps void @insertelement_v_v4i16_s_v(ptr addrspace(1) %ptr, i16 inre
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_lshl_b32_e32 v4, s0, v2
; GFX7-NEXT: v_lshl_b32_e32 v2, 0xffff, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
@@ -1502,9 +1502,9 @@ define amdgpu_ps void @insertelement_v_v4i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX9-NEXT: v_lshlrev_b32_e32 v3, v3, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX9-NEXT: v_not_b32_e32 v3, v3
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
; GFX9-NEXT: v_and_or_b32 v2, v6, v3, v2
@@ -1523,9 +1523,9 @@ define amdgpu_ps void @insertelement_v_v4i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_lshlrev_b32_e32 v3, v3, v6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
; GFX8-NEXT: v_bfi_b32 v3, v3, 0, v6
@@ -1548,8 +1548,8 @@ define amdgpu_ps void @insertelement_v_v4i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v3, v2
; GFX7-NEXT: v_lshl_b32_e32 v3, 0xffff, v3
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
@@ -1978,13 +1978,13 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX9-NEXT: s_and_b32 s4, s4, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX9-NEXT: v_lshlrev_b32_e64 v7, v0, s4
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v0, v0
; GFX9-NEXT: v_and_or_b32 v7, v6, v0, v7
@@ -2013,9 +2013,9 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX8-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
; GFX8-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX8-NEXT: v_lshlrev_b32_e64 v7, v0, s4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v8
@@ -2046,8 +2046,8 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX7-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX7-NEXT: v_lshl_b32_e32 v7, s4, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xffff, v0
@@ -2147,12 +2147,12 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_mov_b32_e32 v4, s2
; GFX9-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v1, v1
; GFX9-NEXT: v_and_or_b32 v8, v7, v1, v0
@@ -2181,8 +2181,8 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX8-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v8
@@ -2213,8 +2213,8 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX7-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
@@ -2313,11 +2313,11 @@ define amdgpu_ps void @insertelement_v_v8i16_s_v(ptr addrspace(1) %ptr, i16 inre
; GFX9-NEXT: v_lshlrev_b32_e64 v9, v2, s0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
@@ -2343,9 +2343,9 @@ define amdgpu_ps void @insertelement_v_v8i16_s_v(ptr addrspace(1) %ptr, i16 inre
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v7, 0
; GFX8-NEXT: v_mov_b32_e32 v8, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
@@ -2367,15 +2367,15 @@ define amdgpu_ps void @insertelement_v_v8i16_s_v(ptr addrspace(1) %ptr, i16 inre
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 1, v2
; GFX7-NEXT: v_and_b32_e32 v1, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: s_and_b32 s0, s2, 0xffff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshl_b32_e32 v2, s0, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v7, v3, v4, vcc
@@ -2575,11 +2575,11 @@ define amdgpu_ps void @insertelement_v_v8i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
@@ -2604,9 +2604,9 @@ define amdgpu_ps void @insertelement_v_v8i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v8, 0
; GFX8-NEXT: v_mov_b32_e32 v9, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
@@ -2629,14 +2629,14 @@ define amdgpu_ps void @insertelement_v_v8i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 1, v3
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -2686,8 +2686,8 @@ define amdgpu_ps void @insertelement_v_v8i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 1, v3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3170,23 +3170,23 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX9-NEXT: v_mov_b32_e32 v4, s11
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v3, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v5, s12
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
; GFX9-NEXT: v_mov_b32_e32 v6, s13
; GFX9-NEXT: v_mov_b32_e32 v7, s14
; GFX9-NEXT: v_mov_b32_e32 v8, s15
-; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v9
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v5, s[14:15]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[6:7]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX9-NEXT: s_and_b32 s4, s4, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[8:9]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX9-NEXT: v_lshlrev_b32_e64 v11, v0, s4
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v12
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v8, s[10:11]
; GFX9-NEXT: v_not_b32_e32 v0, v0
; GFX9-NEXT: v_and_or_b32 v10, v10, v0, v11
@@ -3222,21 +3222,21 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX8-NEXT: v_mov_b32_e32 v4, s11
; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v3, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v5, s12
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
; GFX8-NEXT: v_mov_b32_e32 v6, s13
; GFX8-NEXT: v_mov_b32_e32 v7, s14
; GFX8-NEXT: v_mov_b32_e32 v8, s15
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v9
; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v5, s[14:15]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[6:7]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[8:9]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v8, s[10:11]
; GFX8-NEXT: v_lshlrev_b32_e64 v11, v0, s4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v12
@@ -3274,20 +3274,20 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX7-NEXT: v_mov_b32_e32 v4, s11
; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v3, s[0:1]
; GFX7-NEXT: v_mov_b32_e32 v5, s12
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
; GFX7-NEXT: v_mov_b32_e32 v6, s13
; GFX7-NEXT: v_mov_b32_e32 v7, s14
; GFX7-NEXT: v_mov_b32_e32 v8, s15
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v9
; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v5, s[14:15]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[6:7]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[8:9]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v8, s[10:11]
; GFX7-NEXT: v_lshl_b32_e32 v11, s4, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xffff, v0
@@ -3322,13 +3322,14 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v13
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v13
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v13
-; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v13
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v13
; GFX10-NEXT: v_lshlrev_b32_e64 v10, v0, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s5
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v13
+; GFX10-NEXT: v_not_b32_e32 v10, v10
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s8
; GFX10-NEXT: v_mov_b32_e32 v2, s9
@@ -3339,7 +3340,6 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v7, s14
; GFX10-NEXT: v_mov_b32_e32 v8, s15
-; GFX10-NEXT: v_not_b32_e32 v10, v10
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v4, s1
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v5, s2
@@ -3372,11 +3372,11 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v13
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v13
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v13
-; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v13
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_lshlrev_b32_e64 v10, v0, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, s5
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v13
@@ -3426,17 +3426,17 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 1, v1
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, s7
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v8, s6
; GFX9-NEXT: v_mov_b32_e32 v7, s5
; GFX9-NEXT: v_mov_b32_e32 v6, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s3
-; GFX9-NEXT: v_mov_b32_e32 v4, s2
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v10
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v4, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v10
@@ -3445,12 +3445,12 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v6, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v10
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[6:7]
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX9-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[8:9]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v12
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[10:11]
; GFX9-NEXT: v_not_b32_e32 v1, v1
; GFX9-NEXT: v_and_or_b32 v11, v11, v1, v0
@@ -3476,18 +3476,18 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX8-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 1, v1
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, s7
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
; GFX8-NEXT: v_mov_b32_e32 v8, s6
; GFX8-NEXT: v_mov_b32_e32 v7, s5
; GFX8-NEXT: v_mov_b32_e32 v6, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v10
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v4, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v10
@@ -3497,9 +3497,9 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v10
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[8:9]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[10:11]
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v12
@@ -3527,18 +3527,18 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX7-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
; GFX7-NEXT: v_lshrrev_b32_e32 v10, 1, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, s7
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
; GFX7-NEXT: v_mov_b32_e32 v8, s6
; GFX7-NEXT: v_mov_b32_e32 v7, s5
; GFX7-NEXT: v_mov_b32_e32 v6, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v10
; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v4, s[0:1]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v10
@@ -3548,9 +3548,9 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v10
; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[8:9]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[10:11]
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
@@ -3590,18 +3590,18 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: v_mov_b32_e32 v8, s6
; GFX10-NEXT: v_mov_b32_e32 v7, s5
; GFX10-NEXT: v_mov_b32_e32 v6, s4
-; GFX10-NEXT: v_mov_b32_e32 v5, s3
-; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v3, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v14
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v14
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v14
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v4, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v14
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v14
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v4, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v14
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v14
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v5, s1
@@ -3641,19 +3641,19 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v14
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v14
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v14
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v14
-; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v14
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v4, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v14
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v14
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v5, s1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v6, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3700,11 +3700,11 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v1
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v1
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
; GFX9-NEXT: v_mov_b32_e32 v13, 16
; GFX9-NEXT: v_mov_b32_e32 v14, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -3749,9 +3749,9 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v11, 0
; GFX8-NEXT: v_mov_b32_e32 v12, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v13, 16
; GFX8-NEXT: v_mov_b32_e32 v14, 0
; GFX8-NEXT: s_waitcnt vmcnt(1)
@@ -3786,20 +3786,20 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr
; GFX7-NEXT: buffer_load_dwordx4 v[7:10], v[0:1], s[16:19], 0 addr64 offset:16
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 1, v2
; GFX7-NEXT: v_and_b32_e32 v1, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: s_and_b32 s0, s2, 0xffff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshl_b32_e32 v2, s0, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX7-NEXT: s_mov_b64 s[16:17], 0
; GFX7-NEXT: s_mov_b32 s18, -1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_cndmask_b32_e32 v11, v3, v4, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v5, s[0:1]
@@ -3838,8 +3838,8 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 6, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v14, 0
@@ -4073,11 +4073,11 @@ define amdgpu_ps void @insertelement_v_v16i16_v_v(ptr addrspace(1) %ptr, i16 %va
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v1
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v1
; GFX9-NEXT: v_mov_b32_e32 v12, 0
; GFX9-NEXT: v_mov_b32_e32 v13, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
; GFX9-NEXT: v_mov_b32_e32 v14, 16
; GFX9-NEXT: v_mov_b32_e32 v15, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -4121,9 +4121,9 @@ define amdgpu_ps void @insertelement_v_v16i16_v_v(ptr addrspace(1) %ptr, i16 %va
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v12, 0
; GFX8-NEXT: v_mov_b32_e32 v13, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v14, 16
; GFX8-NEXT: v_mov_b32_e32 v15, 0
; GFX8-NEXT: s_waitcnt vmcnt(1)
@@ -4163,15 +4163,15 @@ define amdgpu_ps void @insertelement_v_v16i16_v_v(ptr addrspace(1) %ptr, i16 %va
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX7-NEXT: s_mov_b64 s[16:17], 0
; GFX7-NEXT: s_mov_b32 s18, -1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
@@ -4210,8 +4210,8 @@ define amdgpu_ps void @insertelement_v_v16i16_v_v(ptr addrspace(1) %ptr, i16 %va
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 4, v3
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
@@ -4255,29 +4255,29 @@ define amdgpu_ps void @insertelement_v_v16i16_v_v(ptr addrspace(1) %ptr, i16 %va
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 4, v3
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v13, 0 :: v_dual_lshlrev_b32 v2, v3, v2
; GFX11-NEXT: v_lshlrev_b32_e64 v12, v3, 0xffff
+; GFX11-NEXT: v_dual_mov_b32 v13, 0 :: v_dual_lshlrev_b32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_not_b32_e32 v3, v12
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_cndmask_b32 v1, v4, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v7, s1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v8, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s3
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v10, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v11, s5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v11, s5
; GFX11-NEXT: v_and_or_b32 v16, v1, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v16, s6
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v16, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v16, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
index 6d76b31091963..e0e8f9e94ffa3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
@@ -434,9 +434,9 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_and_b32_sdwa v3, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: global_store_short v[0:1], v2, off
@@ -454,10 +454,10 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, s4, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
@@ -655,9 +655,9 @@ define amdgpu_ps void @insertelement_v_v2i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_and_b32_sdwa v3, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, s2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_and_b32_sdwa v3, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: global_store_short v[0:1], v2, off
@@ -669,12 +669,12 @@ define amdgpu_ps void @insertelement_v_v2i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
@@ -2163,9 +2163,9 @@ define amdgpu_ps void @insertelement_v_v8i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX9-NEXT: v_lshlrev_b32_e32 v2, v2, v5
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX9-NEXT: v_not_b32_e32 v2, v2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
; GFX9-NEXT: v_and_or_b32 v2, v5, v2, v7
@@ -2185,9 +2185,9 @@ define amdgpu_ps void @insertelement_v_v8i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX8-NEXT: v_lshlrev_b32_e64 v7, v2, s0
; GFX8-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
; GFX8-NEXT: v_bfi_b32 v2, v2, 0, v5
@@ -2210,8 +2210,8 @@ define amdgpu_ps void @insertelement_v_v8i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_lshl_b32_e32 v4, s0, v2
; GFX7-NEXT: v_lshl_b32_e32 v2, 0xff, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
@@ -2393,9 +2393,9 @@ define amdgpu_ps void @insertelement_v_v8i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX9-NEXT: v_lshlrev_b32_e32 v3, v3, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX9-NEXT: v_not_b32_e32 v3, v3
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
; GFX9-NEXT: v_and_or_b32 v2, v6, v3, v2
@@ -2414,9 +2414,9 @@ define amdgpu_ps void @insertelement_v_v8i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_lshlrev_b32_e32 v3, v3, v6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v7
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
; GFX8-NEXT: v_bfi_b32 v3, v3, 0, v6
@@ -2439,8 +2439,8 @@ define amdgpu_ps void @insertelement_v_v8i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v3, v2
; GFX7-NEXT: v_lshl_b32_e32 v3, 0xff, v3
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
@@ -2869,13 +2869,13 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX9-NEXT: v_lshlrev_b32_e64 v7, v0, s4
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v0, v0
; GFX9-NEXT: v_and_or_b32 v7, v6, v0, v7
@@ -2904,9 +2904,9 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX8-NEXT: v_lshlrev_b32_e64 v7, v0, s4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v8
@@ -2937,8 +2937,8 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX7-NEXT: s_and_b32 s4, s4, 0xff
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX7-NEXT: v_lshl_b32_e32 v7, s4, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xff, v0
@@ -3038,12 +3038,12 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_mov_b32_e32 v4, s2
; GFX9-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX9-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v1, v1
; GFX9-NEXT: v_and_or_b32 v8, v7, v1, v0
@@ -3072,8 +3072,8 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v8
@@ -3104,8 +3104,8 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
@@ -3204,11 +3204,11 @@ define amdgpu_ps void @insertelement_v_v16i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX9-NEXT: v_lshlrev_b32_e64 v9, v2, s0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
@@ -3234,9 +3234,9 @@ define amdgpu_ps void @insertelement_v_v16i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v7, 0
; GFX8-NEXT: v_mov_b32_e32 v8, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
@@ -3258,15 +3258,15 @@ define amdgpu_ps void @insertelement_v_v16i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 2, v2
; GFX7-NEXT: v_and_b32_e32 v1, 3, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: s_and_b32 s0, s2, 0xff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshl_b32_e32 v2, s0, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v7, v3, v4, vcc
@@ -3466,11 +3466,11 @@ define amdgpu_ps void @insertelement_v_v16i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
@@ -3495,9 +3495,9 @@ define amdgpu_ps void @insertelement_v_v16i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: v_mov_b32_e32 v8, 0
; GFX8-NEXT: v_mov_b32_e32 v9, 0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
@@ -3520,14 +3520,14 @@ define amdgpu_ps void @insertelement_v_v16i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 2, v3
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_and_b32_e32 v1, 3, v3
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -3577,8 +3577,8 @@ define amdgpu_ps void @insertelement_v_v16i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 3, v3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
; GFX11-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
index d0873872a684d..3ce1e3d443a98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
@@ -240,14 +240,14 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %v
; GFX10-LABEL: dyn_insertelement_v8f32_s_s_v:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_mov_b32_e32 v1, s2
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: v_mov_b32_e32 v5, s6
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_mov_b32_e32 v6, s7
; GFX10-NEXT: v_cndmask_b32_e64 v8, v1, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_mov_b32_e32 v6, s7
; GFX10-NEXT: v_mov_b32_e32 v7, s8
; GFX10-NEXT: v_mov_b32_e32 v9, s9
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s10, vcc_lo
@@ -262,16 +262,16 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %v
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, v8
; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, s10, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v0, v8
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v8f32_s_s_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
; GFX11-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: v_mov_b32_e32 v7, s8
@@ -288,8 +288,8 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %v
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, v8
; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, s10, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v0, v8
; GFX11-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: dyn_insertelement_v8f32_s_s_v:
@@ -887,6 +887,7 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
; GPRIDX-NEXT: v_mov_b32_e32 v6, s7
+; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GPRIDX-NEXT: v_mov_b32_e32 v7, s8
; GPRIDX-NEXT: v_mov_b32_e32 v8, s9
; GPRIDX-NEXT: v_mov_b32_e32 v9, s10
@@ -899,18 +900,17 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GPRIDX-NEXT: v_mov_b32_e32 v16, s17
; GPRIDX-NEXT: v_mov_b32_e32 v17, s18
; GPRIDX-NEXT: v_mov_b32_e32 v18, s19
-; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v2
+; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17]
+; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17]
+; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 2, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 3, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 4, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 5, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[14:15], 7, v2
-; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17]
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17]
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[8:9]
@@ -956,39 +956,39 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX10-NEXT: v_mov_b32_e32 v6, s7
; GFX10-NEXT: v_mov_b32_e32 v7, s8
; GFX10-NEXT: v_mov_b32_e32 v8, s9
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_mov_b32_e32 v9, s10
; GFX10-NEXT: v_mov_b32_e32 v10, s11
; GFX10-NEXT: v_mov_b32_e32 v11, s12
; GFX10-NEXT: v_mov_b32_e32 v12, s13
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_mov_b32_e32 v13, s14
; GFX10-NEXT: v_mov_b32_e32 v14, s15
; GFX10-NEXT: v_mov_b32_e32 v15, s16
; GFX10-NEXT: v_mov_b32_e32 v16, s17
-; GFX10-NEXT: v_mov_b32_e32 v17, s18
-; GFX10-NEXT: v_mov_b32_e32 v18, s19
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s4
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v2
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX10-NEXT: v_mov_b32_e32 v17, s18
+; GFX10-NEXT: v_mov_b32_e32 v18, s19
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s4
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v2
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
@@ -1018,31 +1018,27 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
-; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
-; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
-; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
-; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v0 :: v_dual_cndmask_b32 v6, v6, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v9, v9, v0 :: v_dual_cndmask_b32 v10, v10, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v12, v12, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v0 :: v_dual_cndmask_b32 v14, v14, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s0
; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v0 :: v_dual_cndmask_b32 v16, v16, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v17, v17, v0 :: v_dual_cndmask_b32 v18, v18, v1
; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc
@@ -1073,6 +1069,7 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_mov_b32_e32 v7, s8
; GFX8-NEXT: v_mov_b32_e32 v8, s9
; GFX8-NEXT: v_mov_b32_e32 v9, s10
@@ -1085,18 +1082,17 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX8-NEXT: v_mov_b32_e32 v16, s17
; GFX8-NEXT: v_mov_b32_e32 v17, s18
; GFX8-NEXT: v_mov_b32_e32 v18, s19
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 2, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 3, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 4, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 5, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 7, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[8:9]
@@ -1223,43 +1219,43 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
; GFX10-NEXT: v_mov_b32_e32 v16, s15
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
+; GFX10-NEXT: v_mov_b32_e32 v6, s5
+; GFX10-NEXT: v_mov_b32_e32 v5, s4
+; GFX10-NEXT: v_mov_b32_e32 v8, s7
+; GFX10-NEXT: v_mov_b32_e32 v7, s6
+; GFX10-NEXT: v_mov_b32_e32 v10, s9
+; GFX10-NEXT: v_mov_b32_e32 v9, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_mov_b32_e32 v15, s14
-; GFX10-NEXT: v_mov_b32_e32 v14, s13
-; GFX10-NEXT: v_mov_b32_e32 v13, s12
; GFX10-NEXT: v_mov_b32_e32 v12, s11
; GFX10-NEXT: v_mov_b32_e32 v11, s10
-; GFX10-NEXT: v_mov_b32_e32 v10, s9
-; GFX10-NEXT: v_mov_b32_e32 v9, s8
-; GFX10-NEXT: v_mov_b32_e32 v8, s7
-; GFX10-NEXT: v_mov_b32_e32 v7, s6
-; GFX10-NEXT: v_mov_b32_e32 v6, s5
-; GFX10-NEXT: v_mov_b32_e32 v5, s4
-; GFX10-NEXT: v_mov_b32_e32 v4, s3
-; GFX10-NEXT: v_mov_b32_e32 v3, s2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_mov_b32_e32 v15, s14
+; GFX10-NEXT: v_mov_b32_e32 v14, s13
+; GFX10-NEXT: v_mov_b32_e32 v13, s12
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s19, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s19, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s18, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s18, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s19, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s19, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, s19, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s18, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s19, s0
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, s19, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[1:4], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[5:8], off
@@ -1290,36 +1286,36 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
+; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6
+; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10
-; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
-; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6
-; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
-; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s18, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s19, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s18, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s18, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s19, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s18, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s18, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s19, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v0
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s18, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s18, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s19, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, s19, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s18, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s19, s0
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s18, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s18, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, s19, vcc_lo
; GFX11-NEXT: global_store_b128 v[0:1], v[1:4], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[5:8], off dlc
@@ -1708,6 +1704,11 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s14, s16
; GPRIDX-NEXT: v_mov_b32_e32 v18, s15
+; GPRIDX-NEXT: v_mov_b32_e32 v6, s3
+; GPRIDX-NEXT: v_mov_b32_e32 v5, s2
+; GPRIDX-NEXT: v_mov_b32_e32 v4, s1
+; GPRIDX-NEXT: v_mov_b32_e32 v3, s0
+; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GPRIDX-NEXT: v_mov_b32_e32 v17, s14
; GPRIDX-NEXT: v_mov_b32_e32 v16, s13
; GPRIDX-NEXT: v_mov_b32_e32 v15, s12
@@ -1719,22 +1720,17 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GPRIDX-NEXT: v_mov_b32_e32 v9, s6
; GPRIDX-NEXT: v_mov_b32_e32 v8, s5
; GPRIDX-NEXT: v_mov_b32_e32 v7, s4
-; GPRIDX-NEXT: v_mov_b32_e32 v6, s3
-; GPRIDX-NEXT: v_mov_b32_e32 v5, s2
-; GPRIDX-NEXT: v_mov_b32_e32 v4, s1
-; GPRIDX-NEXT: v_mov_b32_e32 v3, s0
-; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v2
+; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[12:13]
+; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[12:13]
+; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v2
-; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[12:13]
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[12:13]
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[4:5]
@@ -1779,42 +1775,42 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_mov_b32_e32 v17, s14
-; GFX10-NEXT: v_mov_b32_e32 v16, s13
-; GFX10-NEXT: v_mov_b32_e32 v15, s12
-; GFX10-NEXT: v_mov_b32_e32 v14, s11
-; GFX10-NEXT: v_mov_b32_e32 v13, s10
-; GFX10-NEXT: v_mov_b32_e32 v12, s9
-; GFX10-NEXT: v_mov_b32_e32 v11, s8
-; GFX10-NEXT: v_mov_b32_e32 v10, s7
-; GFX10-NEXT: v_mov_b32_e32 v9, s6
-; GFX10-NEXT: v_mov_b32_e32 v8, s5
-; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX10-NEXT: v_mov_b32_e32 v8, s5
+; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_mov_b32_e32 v10, s7
+; GFX10-NEXT: v_mov_b32_e32 v9, s6
+; GFX10-NEXT: v_mov_b32_e32 v12, s9
+; GFX10-NEXT: v_mov_b32_e32 v11, s8
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX10-NEXT: v_mov_b32_e32 v14, s11
+; GFX10-NEXT: v_mov_b32_e32 v13, s10
+; GFX10-NEXT: v_mov_b32_e32 v16, s13
+; GFX10-NEXT: v_mov_b32_e32 v15, s12
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX10-NEXT: v_mov_b32_e32 v17, s14
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
@@ -1846,31 +1842,27 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
-; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
-; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
-; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
-; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v0 :: v_dual_cndmask_b32 v6, v6, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v9, v9, v0 :: v_dual_cndmask_b32 v10, v10, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v12, v12, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v0 :: v_dual_cndmask_b32 v14, v14, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s0
; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v0 :: v_dual_cndmask_b32 v16, v16, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v17, v17, v0 :: v_dual_cndmask_b32 v18, v18, v1
; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc
@@ -1900,6 +1892,11 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GFX8-NEXT: s_mov_b32 s12, s14
; GFX8-NEXT: s_mov_b32 s14, s16
; GFX8-NEXT: v_mov_b32_e32 v18, s15
+; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s2
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_mov_b32_e32 v17, s14
; GFX8-NEXT: v_mov_b32_e32 v16, s13
; GFX8-NEXT: v_mov_b32_e32 v15, s12
@@ -1911,22 +1908,17 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GFX8-NEXT: v_mov_b32_e32 v9, s6
; GFX8-NEXT: v_mov_b32_e32 v8, s5
; GFX8-NEXT: v_mov_b32_e32 v7, s4
-; GFX8-NEXT: v_mov_b32_e32 v6, s3
-; GFX8-NEXT: v_mov_b32_e32 v5, s2
-; GFX8-NEXT: v_mov_b32_e32 v4, s1
-; GFX8-NEXT: v_mov_b32_e32 v3, s0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[4:5]
@@ -2003,29 +1995,29 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i
; GFX10-LABEL: dyn_insertelement_v8f64_v_s_v:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v16
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
@@ -2039,29 +2031,29 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i
; GFX11-LABEL: dyn_insertelement_v8f64_v_s_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v16
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s3, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s2, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s3, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s3, s1
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s3, s0
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
@@ -2237,29 +2229,29 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %
; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
@@ -2273,25 +2265,21 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %
; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v16 :: v_dual_cndmask_b32 v3, v3, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v16 :: v_dual_cndmask_b32 v5, v5, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v16 :: v_dual_cndmask_b32 v7, v7, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v16 :: v_dual_cndmask_b32 v9, v9, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v11, v11, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX11-NEXT: v_dual_cndmask_b32 v12, v12, v16 :: v_dual_cndmask_b32 v13, v13, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v14, v14, v16 :: v_dual_cndmask_b32 v15, v15, v17
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
@@ -3158,29 +3146,29 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_add_nc_u32_e32 v18, 1, v18
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
@@ -3195,26 +3183,21 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_add_nc_u32_e32 v18, 1, v18
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v16 :: v_dual_cndmask_b32 v3, v3, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v16 :: v_dual_cndmask_b32 v5, v5, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v16 :: v_dual_cndmask_b32 v7, v7, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v16 :: v_dual_cndmask_b32 v9, v9, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v11, v11, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX11-NEXT: v_dual_cndmask_b32 v12, v12, v16 :: v_dual_cndmask_b32 v13, v13, v17
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v14, v14, v16 :: v_dual_cndmask_b32 v15, v15, v17
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
@@ -7488,7 +7471,6 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: v_mov_b32_e32 v18, s15
-; GPRIDX-NEXT: v_mov_b32_e32 v17, s14
; GPRIDX-NEXT: v_mov_b32_e32 v16, s13
; GPRIDX-NEXT: v_mov_b32_e32 v15, s12
; GPRIDX-NEXT: v_mov_b32_e32 v14, s11
@@ -7504,13 +7486,14 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GPRIDX-NEXT: v_mov_b32_e32 v4, s1
; GPRIDX-NEXT: v_mov_b32_e32 v3, s0
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GPRIDX-NEXT: v_mov_b32_e32 v17, s14
+; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v5, v0, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v7, v0, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v9, v0, s[2:3]
@@ -7557,54 +7540,54 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: v_mov_b32_e32 v18, s15
-; GFX10-NEXT: v_mov_b32_e32 v17, s14
-; GFX10-NEXT: v_mov_b32_e32 v16, s13
-; GFX10-NEXT: v_mov_b32_e32 v15, s12
-; GFX10-NEXT: v_mov_b32_e32 v14, s11
-; GFX10-NEXT: v_mov_b32_e32 v13, s10
-; GFX10-NEXT: v_mov_b32_e32 v12, s9
-; GFX10-NEXT: v_mov_b32_e32 v11, s8
-; GFX10-NEXT: v_mov_b32_e32 v10, s7
-; GFX10-NEXT: v_mov_b32_e32 v9, s6
-; GFX10-NEXT: v_mov_b32_e32 v8, s5
-; GFX10-NEXT: v_mov_b32_e32 v7, s4
-; GFX10-NEXT: v_mov_b32_e32 v6, s3
-; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
+; GFX10-NEXT: v_mov_b32_e32 v6, s3
+; GFX10-NEXT: v_mov_b32_e32 v5, s2
+; GFX10-NEXT: v_mov_b32_e32 v8, s5
+; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_mov_b32_e32 v10, s7
+; GFX10-NEXT: v_mov_b32_e32 v9, s6
+; GFX10-NEXT: v_mov_b32_e32 v12, s9
+; GFX10-NEXT: v_mov_b32_e32 v11, s8
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX10-NEXT: v_mov_b32_e32 v14, s11
+; GFX10-NEXT: v_mov_b32_e32 v13, s10
+; GFX10-NEXT: v_mov_b32_e32 v16, s13
+; GFX10-NEXT: v_mov_b32_e32 v15, s12
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
-; GFX10-NEXT: v_readfirstlane_b32 s2, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v12, v1, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s3, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX10-NEXT: v_mov_b32_e32 v17, s14
; GFX10-NEXT: v_readfirstlane_b32 s0, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v4
+; GFX10-NEXT: v_readfirstlane_b32 s2, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v6
; GFX10-NEXT: v_readfirstlane_b32 s4, v7
; GFX10-NEXT: v_readfirstlane_b32 s5, v8
; GFX10-NEXT: v_readfirstlane_b32 s6, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
; GFX10-NEXT: v_readfirstlane_b32 s7, v10
; GFX10-NEXT: v_readfirstlane_b32 s8, v11
-; GFX10-NEXT: v_readfirstlane_b32 s9, v2
-; GFX10-NEXT: v_readfirstlane_b32 s10, v12
-; GFX10-NEXT: v_readfirstlane_b32 s11, v13
+; GFX10-NEXT: v_readfirstlane_b32 s9, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
+; GFX10-NEXT: v_readfirstlane_b32 s10, v13
+; GFX10-NEXT: v_readfirstlane_b32 s11, v14
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10-NEXT: ; return to shader part epilog
@@ -7626,43 +7609,39 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
-; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
-; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
-; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
-; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
-; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
-; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v0 :: v_dual_cndmask_b32 v6, v6, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
-; GFX11-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v2, v12, v1
-; GFX11-NEXT: v_readfirstlane_b32 s3, v6
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-NEXT: v_readfirstlane_b32 s3, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v9, v9, v0 :: v_dual_cndmask_b32 v10, v10, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX11-NEXT: v_readfirstlane_b32 s4, v7
; GFX11-NEXT: v_readfirstlane_b32 s5, v8
; GFX11-NEXT: v_readfirstlane_b32 s6, v9
; GFX11-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v12, v12, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v11
-; GFX11-NEXT: v_readfirstlane_b32 s9, v2
-; GFX11-NEXT: v_readfirstlane_b32 s10, v12
-; GFX11-NEXT: v_readfirstlane_b32 s11, v13
+; GFX11-NEXT: v_readfirstlane_b32 s9, v12
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v0 :: v_dual_cndmask_b32 v14, v14, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
+; GFX11-NEXT: v_readfirstlane_b32 s10, v13
+; GFX11-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v15, v0 :: v_dual_cndmask_b32 v1, v16, v1
; GFX11-NEXT: v_readfirstlane_b32 s12, v0
; GFX11-NEXT: v_readfirstlane_b32 s13, v1
; GFX11-NEXT: ; return to shader part epilog
@@ -7684,7 +7663,6 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX8-NEXT: s_mov_b32 s12, s14
; GFX8-NEXT: s_mov_b32 s13, s15
; GFX8-NEXT: v_mov_b32_e32 v18, s15
-; GFX8-NEXT: v_mov_b32_e32 v17, s14
; GFX8-NEXT: v_mov_b32_e32 v16, s13
; GFX8-NEXT: v_mov_b32_e32 v15, s12
; GFX8-NEXT: v_mov_b32_e32 v14, s11
@@ -7700,13 +7678,14 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX8-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX8-NEXT: v_mov_b32_e32 v17, s14
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v0, s[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v0, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v0, s[2:3]
@@ -7856,38 +7835,38 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_v(<7 x double> %vec,
; GFX10-LABEL: dyn_insertelement_v7f64_v_v_v:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 6, v16
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v14, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v15, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v14, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v15, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v15, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v14, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v15, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v15, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v15, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; GFX10-NEXT: v_readfirstlane_b32 s10, v10
; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s12, v12
; GFX10-NEXT: v_readfirstlane_b32 s13, v13
; GFX10-NEXT: ; return to shader part epilog
@@ -7895,35 +7874,31 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_v(<7 x double> %vec,
; GFX11-LABEL: dyn_insertelement_v7f64_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v16
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v14 :: v_dual_cndmask_b32 v1, v1, v15
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v14, s1
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v14 :: v_dual_cndmask_b32 v5, v5, v15
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v14, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v15, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v15, s1
-; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v9, v9, v15
-; GFX11-NEXT: v_readfirstlane_b32 s1, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v14, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v15, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v14 :: v_dual_cndmask_b32 v3, v3, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v14 :: v_dual_cndmask_b32 v5, v5, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_cndmask_b32 v7, v7, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v9, v9, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v10, v14 :: v_dual_cndmask_b32 v11, v11, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v12, v14 :: v_dual_cndmask_b32 v13, v13, v15
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: ; return to shader part epilog
@@ -8201,8 +8176,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 4, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 4, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v10, v1, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v0, v11, v0, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[0:1]
@@ -8231,38 +8206,38 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: v_mov_b32_e32 v12, s9
-; GFX10-NEXT: v_mov_b32_e32 v11, s8
-; GFX10-NEXT: v_mov_b32_e32 v10, s7
-; GFX10-NEXT: v_mov_b32_e32 v9, s6
-; GFX10-NEXT: v_mov_b32_e32 v8, s5
-; GFX10-NEXT: v_mov_b32_e32 v7, s4
-; GFX10-NEXT: v_mov_b32_e32 v6, s3
-; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 4, v2
+; GFX10-NEXT: v_mov_b32_e32 v6, s3
+; GFX10-NEXT: v_mov_b32_e32 v5, s2
+; GFX10-NEXT: v_mov_b32_e32 v8, s5
+; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
-; GFX10-NEXT: v_readfirstlane_b32 s2, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v10, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s1
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_mov_b32_e32 v10, s7
+; GFX10-NEXT: v_mov_b32_e32 v9, s6
+; GFX10-NEXT: v_mov_b32_e32 v11, s8
; GFX10-NEXT: v_readfirstlane_b32 s0, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v4
+; GFX10-NEXT: v_readfirstlane_b32 s2, v5
; GFX10-NEXT: v_readfirstlane_b32 s3, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; GFX10-NEXT: v_readfirstlane_b32 s4, v7
-; GFX10-NEXT: v_readfirstlane_b32 s5, v2
-; GFX10-NEXT: v_readfirstlane_b32 s6, v8
-; GFX10-NEXT: v_readfirstlane_b32 s7, v9
+; GFX10-NEXT: v_readfirstlane_b32 s5, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
+; GFX10-NEXT: v_readfirstlane_b32 s6, v9
+; GFX10-NEXT: v_readfirstlane_b32 s7, v10
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10-NEXT: ; return to shader part epilog
@@ -8280,31 +8255,28 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
-; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
-; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
-; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 4, v2
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
-; GFX11-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v2, v8, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v9, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v10, v1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v11, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v12, v1, s1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v0 :: v_dual_cndmask_b32 v6, v6, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
+; GFX11-NEXT: v_readfirstlane_b32 s2, v5
; GFX11-NEXT: v_readfirstlane_b32 s3, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; GFX11-NEXT: v_readfirstlane_b32 s4, v7
-; GFX11-NEXT: v_readfirstlane_b32 s5, v2
-; GFX11-NEXT: v_readfirstlane_b32 s6, v8
-; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s5, v8
+; GFX11-NEXT: v_dual_cndmask_b32 v9, v9, v0 :: v_dual_cndmask_b32 v10, v10, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
+; GFX11-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v11, v0 :: v_dual_cndmask_b32 v1, v12, v1
; GFX11-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-NEXT: v_readfirstlane_b32 s9, v1
; GFX11-NEXT: ; return to shader part epilog
@@ -8341,8 +8313,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 4, v2
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 4, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v11, v0, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[0:1]
@@ -8453,28 +8425,28 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec,
; GFX10-LABEL: dyn_insertelement_v5f64_v_v_v:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 4, v12
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12
; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: ; return to shader part epilog
@@ -8482,26 +8454,23 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec,
; GFX11-LABEL: dyn_insertelement_v5f64_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 4, v12
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v12
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12
; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v10 :: v_dual_cndmask_b32 v9, v9, v11
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index 5fb07622c580f..0787935b31cce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -129,9 +129,9 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
index 7d8ac66128424..1794f87c4cf39 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
@@ -1587,8 +1587,9 @@ define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4294967296(ptr addrspace(1)
;
; GFX12-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4294967296:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
; GFX12-NEXT: v_mov_b32_e32 v4, v2
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 4, v1, vcc_lo
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
index ecd21f9d02095..b09c1058e6907 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -2847,9 +2847,9 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX10-NEXT: v_mad_u64_u32 v[5:6], s9, v16, v9, v[1:2]
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s6, 0, v12, s6
; GFX10-NEXT: v_mad_u64_u32 v[12:13], s6, v19, v8, v[3:4]
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
; GFX10-NEXT: v_mul_lo_u32 v20, v16, v15
; GFX10-NEXT: v_mul_lo_u32 v9, v17, v14
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
; GFX10-NEXT: v_mad_u64_u32 v[14:15], s9, v21, v8, v[10:11]
; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s6, 0, v1, s6
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s6, v17, v8, v[5:6]
@@ -3007,9 +3007,9 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v12, s2
; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], s2, v19, v8, v[3:4]
-; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, 1, s5
; GFX12-NEXT: v_mul_lo_u32 v20, v16, v15
; GFX12-NEXT: v_mul_lo_u32 v9, v17, v14
+; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, 1, s5
; GFX12-NEXT: v_mad_co_u64_u32 v[14:15], s5, v21, v8, v[10:11]
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v1, s2
@@ -3072,36 +3072,36 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_mad_nc_u64_u32 v[24:25], v6, v8, v[20:21]
; GFX1250-NEXT: v_mad_co_u64_u32 v[0:1], s0, v17, v9, v[18:19]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_dual_mov_b32 v18, v23 :: v_dual_mov_b32 v19, v24
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_mov_b32_e32 v18, v23
+; GFX1250-NEXT: v_cndmask_b32_e64 v23, 0, 1, s0
+; GFX1250-NEXT: v_mov_b32_e32 v19, v24
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_mad_co_u64_u32 v[20:21], vcc_lo, v2, v8, v[0:1]
; GFX1250-NEXT: v_mul_lo_u32 v24, v6, v9
-; GFX1250-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v23, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_mad_co_u64_u32 v[0:1], s0, v16, v13, v[18:19]
-; GFX1250-NEXT: v_mov_b32_e32 v19, v22
-; GFX1250-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
-; GFX1250-NEXT: v_mov_b32_e32 v18, v21
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_mad_co_u64_u32 v[26:27], vcc_lo, v17, v12, v[0:1]
+; GFX1250-NEXT: v_dual_mov_b32 v19, v22 :: v_dual_mov_b32 v18, v21
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], vcc_lo, v17, v12, v[0:1]
+; GFX1250-NEXT: v_mad_co_u64_u32 v[26:27], s2, v16, v11, v[18:19]
; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v16, v8, 0
-; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], s2, v16, v11, v[18:19]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_cndmask_b32_e64 v21, 0, 1, s2
-; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s1, v2, v11, v[26:27]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s1, v2, v11, v[22:23]
+; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], s2, v17, v10, v[26:27]
; GFX1250-NEXT: v_mov_b32_e32 v11, v20
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_mad_co_u64_u32 v[26:27], s2, v17, v10, v[22:23]
-; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], s3, v3, v10, v[18:19]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_mad_co_u64_u32 v[26:27], s3, v3, v10, v[18:19]
; GFX1250-NEXT: v_mov_b32_e32 v10, v1
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v21, s2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s2, v2, v9, v[26:27]
+; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s2, v2, v9, v[22:23]
; GFX1250-NEXT: v_mul_lo_u32 v2, v2, v13
; GFX1250-NEXT: v_mad_co_u64_u32 v[20:21], s5, v16, v9, v[10:11]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, s2
-; GFX1250-NEXT: v_mad_co_u64_u32 v[12:13], s4, v4, v9, v[22:23]
+; GFX1250-NEXT: v_mad_co_u64_u32 v[12:13], s4, v4, v9, v[26:27]
; GFX1250-NEXT: v_mul_lo_u32 v22, v16, v15
; GFX1250-NEXT: v_mul_lo_u32 v9, v17, v14
; GFX1250-NEXT: v_mad_co_u64_u32 v[10:11], s2, v3, v8, v[18:19]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index 6b0fa2f947e33..8eda4ea8e8b08 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -4532,8 +4532,8 @@ define amdgpu_ps <2 x float> @saddsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
+; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
@@ -4840,8 +4840,8 @@ define amdgpu_ps <2 x float> @saddsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
+; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-NEXT: ; return to shader part epilog
@@ -5262,9 +5262,9 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc
; GFX6-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v3
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
@@ -5292,8 +5292,8 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX8-NEXT: v_xor_b32_e32 v2, v2, v6
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000000, v3
; GFX8-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
@@ -5321,9 +5321,9 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX9-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX9-NEXT: v_add_u32_e32 v6, 0x80000000, v3
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
@@ -5347,8 +5347,8 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX10-NEXT: v_xor_b32_e32 v2, v2, v6
; GFX10-NEXT: v_add_nc_u32_e32 v6, 0x80000000, v3
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2
@@ -5373,8 +5373,8 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX11-NEXT: v_xor_b32_e32 v2, v2, v6
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x80000000, v3
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2
@@ -5396,12 +5396,12 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v6, s2
; GFX6-NEXT: v_mov_b32_e32 v7, s3
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v3, v7, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
+; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
@@ -5433,9 +5433,9 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
-; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -5463,9 +5463,9 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -5490,14 +5490,14 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[2:3], 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: s_cselect_b32 s0, 0, s0
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10-NEXT: s_cselect_b32 s0, 0, s0
; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX10-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
@@ -5517,14 +5517,14 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[2:3], 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, 1, 0
-; GFX11-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v7
-; GFX11-NEXT: s_cselect_b32 s0, 0, s0
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v2
+; GFX11-NEXT: s_cselect_b32 s0, 0, s0
; GFX11-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v2 :: v_dual_cndmask_b32 v3, v7, v3
@@ -5654,11 +5654,11 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v17
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11]
-; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc
@@ -5676,11 +5676,11 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
-; GFX9-NEXT: v_add_u32_e32 v7, 0x80000000, v6
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_add_u32_e32 v7, 0x80000000, v6
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
@@ -5699,42 +5699,42 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[16:17], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v4, v12
-; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v5, v13, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, v6, v14, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v19, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v18, 0, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v4, v12
+; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v6, v14, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v7, v15, vcc_lo
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[4:5]
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[6:7]
-; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v19
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[6:7]
+; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v17
+; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v13
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v17
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v4
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v3
-; GFX10-NEXT: v_xor_b32_e32 v2, v2, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u16_e64 s4, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v18, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v19, v7, s4
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
+; GFX10-NEXT: v_xor_b32_e32 v5, v2, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v13, v7, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_saddsat_v2i128:
@@ -5748,41 +5748,40 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[16:17], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v4, v12
-; GFX11-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v5, v13, vcc_lo
-; GFX11-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, v6, v14, vcc_lo
-; GFX11-NEXT: v_add_co_ci_u32_e64 v19, null, v7, v15, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v18, 0, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v4, v12
+; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, v7, v15, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[4:5]
; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[6:7]
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[6:7]
-; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[6:7]
+; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v17
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v13
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v17
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v4
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v3
-; GFX11-NEXT: v_xor_b32_e32 v2, v2, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v8, v3, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc_lo
-; GFX11-NEXT: v_cmp_ne_u16_e64 s0, 0, v2
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v16, v3 :: v_dual_cndmask_b32 v3, v17, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v12, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v13, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v18, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v19, v7, s0
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
+; GFX11-NEXT: v_xor_b32_e32 v5, v2, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v8, v4 :: v_dual_cndmask_b32 v3, v17, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v4, vcc_lo
+; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v12, v6 :: v_dual_cndmask_b32 v7, v13, v7
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
index b0d486396bfb1..eabe19663a2c2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -131,8 +131,8 @@ define i64 @v_sdiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v2
; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v3, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1
; CHECK-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1
; CHECK-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v11
; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v12, vcc
@@ -238,8 +238,8 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
@@ -309,8 +309,8 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v6
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s11, v1
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v5, s[0:1]
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s10, v0
@@ -513,9 +513,9 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v14, v4
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[8:9]
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v14, v4
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, 1, v17
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v14, v4
; GISEL-NEXT: v_cndmask_b32_e64 v4, v13, v15, s[4:5]
; GISEL-NEXT: v_addc_u32_e32 v13, vcc, 0, v18, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v10
@@ -611,8 +611,8 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v7
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v6
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v6
; GISEL-NEXT: v_cndmask_b32_e64 v4, v8, v9, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v12
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v14, vcc
@@ -717,8 +717,8 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_mul_hi_u32 v4, v14, v4
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v11, v5
@@ -759,8 +759,8 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v3, v2
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1
; CGP-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1
; CGP-NEXT: v_cndmask_b32_e64 v5, v10, v11, s[4:5]
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v14
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v15, vcc
@@ -890,8 +890,8 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_mul_hi_u32 v6, v12, v6
+; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7
@@ -932,8 +932,8 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v4
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v5, v4
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v3
; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v3
; CGP-NEXT: v_cndmask_b32_e64 v6, v8, v9, s[4:5]
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v13
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v15, vcc
@@ -1068,8 +1068,8 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v11
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_mul_hi_u32 v5, v10, v6
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
@@ -1138,8 +1138,8 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v6
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; CHECK-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, v3, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v7
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
@@ -1232,8 +1232,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v9, vcc
; GISEL-NEXT: v_xor_b32_e32 v18, v0, v9
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v14
; GISEL-NEXT: v_xor_b32_e32 v19, v1, v9
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v16, v1
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
@@ -1255,8 +1255,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v1, v19, v1
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v14, v0
@@ -1336,8 +1336,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_mul_hi_u32 v5, v11, v5
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v6, v2
@@ -1379,8 +1379,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GISEL-NEXT: v_cndmask_b32_e64 v3, -1, v6, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v11
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v15, vcc
@@ -1466,8 +1466,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v17
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v17, vcc
; CGP-NEXT: v_xor_b32_e32 v18, v0, v17
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v13
; CGP-NEXT: v_xor_b32_e32 v19, v1, v17
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v13
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v1, vcc, v15, v1
; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
@@ -1489,8 +1489,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_mul_hi_u32 v1, v19, v1
+; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e32 v14, vcc, v0, v12
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v0, vcc, v13, v0
@@ -1569,8 +1569,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_mul_hi_u32 v5, v12, v5
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6
@@ -1608,8 +1608,8 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; CGP-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v3, -1, v6, s[4:5]
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v7
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc
@@ -1764,8 +1764,8 @@ define i64 @v_sdiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v2
; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v3, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1
; CHECK-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1
; CHECK-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v11
; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v12, vcc
@@ -1862,8 +1862,8 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v18, v14
; GISEL-NEXT: v_mul_hi_u32 v9, v16, v9
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v18, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
@@ -1968,9 +1968,9 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v16, v5
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[8:9]
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v16, v5
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v17
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v16, v5
; GISEL-NEXT: v_cndmask_b32_e64 v5, v14, v15, s[4:5]
; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v18, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, 1, v11
@@ -2066,8 +2066,8 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v10
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v9
; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v9
; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v13
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v17, vcc
@@ -2217,8 +2217,8 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v4
; CGP-NEXT: v_sub_i32_e32 v8, vcc, v8, v4
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v1
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v10, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v1
; CGP-NEXT: v_cndmask_b32_e64 v9, v11, v12, s[4:5]
; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v16
; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v17, vcc
@@ -2392,8 +2392,8 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v4
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v5, v4
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v3
; CGP-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v3
; CGP-NEXT: v_cndmask_b32_e64 v6, v8, v9, s[4:5]
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v13
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v14, vcc
@@ -2631,8 +2631,8 @@ define <2 x i64> @v_sdiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v11, v8
; GISEL-NEXT: v_mul_hi_u32 v7, v14, v7
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v11, v8
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
@@ -2667,8 +2667,8 @@ define <2 x i64> @v_sdiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v16, v7
; GISEL-NEXT: v_mul_hi_u32 v1, v14, v1
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v16, v7
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v7, v6
@@ -2702,8 +2702,8 @@ define <2 x i64> @v_sdiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; GISEL-NEXT: v_cndmask_b32_e64 v4, -1, v6, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v11
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v14, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
index 70934d0d901f6..d157a876cca71 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
@@ -45,14 +45,14 @@ define <4 x half> @test_v4s16(<4 x half> %a) #0 {
; GCN-LABEL: test_v4s16:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GCN-NEXT: v_cndmask_b32_e64 v5, v0, 0, vcc
; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v0, v4 src0_sel:WORD_1 src1_sel:DWORD
-; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[4:5]
+; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v2, v1, 0, vcc
; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v4 src0_sel:WORD_1 src1_sel:DWORD
; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[4:5]
@@ -71,29 +71,29 @@ define <8 x half> @test_v8s16(<8 x half> %a) #0 {
; GCN-LABEL: test_v8s16:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GCN-NEXT: v_cndmask_b32_e64 v9, v0, 0, vcc
; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v0, v8 src0_sel:WORD_1 src1_sel:DWORD
-; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GCN-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v4, v1, 0, vcc
-; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v8 src0_sel:WORD_1 src1_sel:DWORD
-; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v8 src0_sel:WORD_1 src1_sel:DWORD
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, 0, s[4:5]
+; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v5, v2, 0, vcc
-; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v2, v8 src0_sel:WORD_1 src1_sel:DWORD
-; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v2, v8 src0_sel:WORD_1 src1_sel:DWORD
; GCN-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
+; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e64 v6, v3, 0, vcc
-; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v3, v8 src0_sel:WORD_1 src1_sel:DWORD
; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v4
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v5
+; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v3, v8 src0_sel:WORD_1 src1_sel:DWORD
; GCN-NEXT: v_cndmask_b32_e64 v3, v7, 0, s[4:5]
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v9
; GCN-NEXT: v_lshl_or_b32 v2, v2, 16, v4
@@ -146,11 +146,11 @@ define <2 x double> @test_v2s64(<2 x double> %a) #0 {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cmp_gt_f64_e64 s[4:5], 0, v[2:3]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5]
+; GCN-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
+; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%fcmp = fcmp olt <2 x double> %a, zeroinitializer
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
index f589919992335..8c6a99fdddd06 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
@@ -1651,14 +1651,14 @@ define i65 @v_shl_i65(i65 %value, i65 %amount) {
; GFX10-LABEL: v_shl_i65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 64, v3
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 64, v3
; GFX10-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v3
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
-; GFX10-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]
+; GFX10-NEXT: v_lshrrev_b64 v[4:5], v4, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[5:6], v3, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
-; GFX10-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX10-NEXT: v_or_b32_e32 v1, v4, v5
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc_lo
@@ -1669,14 +1669,14 @@ define i65 @v_shl_i65(i65 %value, i65 %amount) {
; GFX11-LABEL: v_shl_i65:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 64, v3
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 64, v3
; GFX11-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v3
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
-; GFX11-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], v4, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[5:6], v3, v[2:3]
; GFX11-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v1 :: v_dual_cndmask_b32 v1, 0, v7
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index 3cd02dd65fd95..dec410d36df82 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -129,8 +129,8 @@ define i64 @v_srem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
; CHECK-NEXT: v_subb_u32_e32 v4, vcc, v4, v1, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[4:5]
; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v2, v0
; CHECK-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v4, vcc
@@ -234,8 +234,8 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v8
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_mul_hi_u32 v3, v7, v4
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
@@ -298,14 +298,14 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_sub_i32_e64 v3, s[0:1], s11, v4
; CHECK-NEXT: v_subb_u32_e64 v2, s[0:1], v7, v4, vcc
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2
; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
+; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2
+; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v0
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v5, s[0:1]
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
@@ -522,8 +522,8 @@ define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v14, v9
; GISEL-NEXT: v_mul_hi_u32 v0, v20, v0
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v14, v9
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v8, v1
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
@@ -599,18 +599,18 @@ define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v7
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v2, v6
; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v7
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v6
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v7
; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v8, v6
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v7
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
@@ -745,8 +745,8 @@ define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
; CGP-NEXT: v_subb_u32_e32 v4, vcc, v4, v1, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v10, vcc, v2, v0
; CGP-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v4, vcc
@@ -914,8 +914,8 @@ define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v2
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v3
; CGP-NEXT: v_subb_u32_e32 v6, vcc, v6, v3, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v3
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v8, vcc, v4, v2
; CGP-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v6, vcc
@@ -1053,8 +1053,8 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v11
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_mul_hi_u32 v5, v10, v6
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
@@ -1129,8 +1129,8 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v4, v6
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v2, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[4:5]
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
@@ -1215,8 +1215,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v9, vcc
; GISEL-NEXT: v_xor_b32_e32 v18, v0, v9
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v14
; GISEL-NEXT: v_xor_b32_e32 v19, v1, v9
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v16, v1
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
@@ -1238,8 +1238,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v1, v19, v1
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v14, v0
@@ -1317,8 +1317,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_mul_hi_u32 v5, v11, v5
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v6, v2
@@ -1366,8 +1366,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cndmask_b32_e32 v8, -1, v8, vcc
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v7, v4
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GISEL-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GISEL-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
@@ -1445,8 +1445,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v17
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v17, vcc
; CGP-NEXT: v_xor_b32_e32 v18, v0, v17
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v13
; CGP-NEXT: v_xor_b32_e32 v19, v1, v17
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v13
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v1, vcc, v15, v1
; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
@@ -1546,8 +1546,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_mul_hi_u32 v5, v12, v5
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6
@@ -1591,8 +1591,8 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_cndmask_b32_e32 v9, -1, v9, vcc
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v7, v4
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v5, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[4:5]
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CGP-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
@@ -1737,8 +1737,8 @@ define i64 @v_srem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
; CHECK-NEXT: v_subb_u32_e32 v4, vcc, v4, v1, vcc
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[4:5]
; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v2, v0
; CHECK-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v4, vcc
@@ -1956,8 +1956,8 @@ define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v0, v20, v0
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v9, v1
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
@@ -2033,18 +2033,18 @@ define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v8
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v9, vcc, v2, v6
; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v3, vcc
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v8
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v6
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v8
; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v9, v6
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v8
; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5]
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
@@ -2182,8 +2182,8 @@ define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v0
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v1
; CGP-NEXT: v_subb_u32_e32 v9, vcc, v9, v1, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v1
; CGP-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v11, vcc, v4, v0
; CGP-NEXT: v_subbrev_u32_e64 v12, s[4:5], 0, v9, vcc
@@ -2353,8 +2353,8 @@ define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v2
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v3
; CGP-NEXT: v_subb_u32_e32 v6, vcc, v6, v3, vcc
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v3
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v8, vcc, v4, v2
; CGP-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v6, vcc
@@ -2620,8 +2620,8 @@ define <2 x i64> @v_srem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v16, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v11, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v16, v7
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5
@@ -2661,8 +2661,8 @@ define <2 x i64> @v_srem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cndmask_b32_e32 v8, -1, v8, vcc
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v7, v3
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; GISEL-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 38eebd4ae1c25..97e502e5ecdfe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -5304,11 +5304,11 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
@@ -5330,9 +5330,9 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v5
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
-; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
@@ -5447,11 +5447,11 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
@@ -5473,9 +5473,9 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v5
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
-; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
@@ -5631,11 +5631,11 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v17
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[16:17]
-; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v18, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v19, v2, vcc
@@ -5653,11 +5653,11 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[8:9]
-; GFX9-NEXT: v_add_u32_e32 v7, 0x80000000, v6
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX9-NEXT: v_xor_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u32_e32 v7, 0x80000000, v6
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc
@@ -5688,30 +5688,30 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v17
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v17
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v4
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v3
-; GFX10-NEXT: v_xor_b32_e32 v2, v1, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v3, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u16_e64 s4, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v7, s4
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
+; GFX10-NEXT: v_xor_b32_e32 v5, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_ssubsat_v2i128:
@@ -5737,29 +5737,28 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX11-NEXT: v_sub_co_ci_u32_e64 v9, null, v7, v15, vcc_lo
; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
; GFX11-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v17
; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v9
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v17
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v4
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v3
-; GFX11-NEXT: v_xor_b32_e32 v2, v1, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v18, v3, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v3, vcc_lo
-; GFX11-NEXT: v_cmp_ne_u16_e64 s0, 0, v2
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v16, v3 :: v_dual_cndmask_b32 v3, v17, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v8, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, v7, s0
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
+; GFX11-NEXT: v_xor_b32_e32 v5, v1, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v18, v4 :: v_dual_cndmask_b32 v3, v17, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v4, vcc_lo
+; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 567656635b726..ad6cbe90501dd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -2991,9 +2991,9 @@ define i48 @v_uaddsat_i48(i48 %lhs, i48 %rhs) {
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
@@ -3100,12 +3100,12 @@ define amdgpu_ps <2 x float> @uaddsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -3159,12 +3159,12 @@ define amdgpu_ps <2 x float> @uaddsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -3711,10 +3711,10 @@ define <2 x i128> @v_uaddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
-; GFX10-NEXT: v_add_co_u32 v4, s4, v4, v12
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s4, v5, v13, s4
+; GFX10-NEXT: v_add_co_u32 v4, s4, v4, v12
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s4, v5, v13, s4
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, v6, v14, s4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v7, v15, s4
@@ -3732,10 +3732,10 @@ define <2 x i128> @v_uaddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
-; GFX11-NEXT: v_add_co_u32 v4, s0, v4, v12
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
-; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s0, v5, v13, s0
+; GFX11-NEXT: v_add_co_u32 v4, s0, v4, v12
; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s0, v5, v13, s0
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, v6, v14, s0
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, s0, v7, v15, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
index b6fa328393b86..589904ac19951 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
@@ -2051,81 +2051,81 @@ define <2 x i64> @v_udiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_mul_lo_u32 v10, v6, v2
; GISEL-NEXT: v_mul_hi_u32 v11, v6, v2
; GISEL-NEXT: v_mul_lo_u32 v12, 0, v2
-; GISEL-NEXT: v_mul_hi_u32 v13, 0, v2
-; GISEL-NEXT: v_mul_lo_u32 v2, v0, v5
+; GISEL-NEXT: v_mul_hi_u32 v2, 0, v2
+; GISEL-NEXT: v_mul_lo_u32 v13, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v14, v0, v5
; GISEL-NEXT: v_mul_lo_u32 v15, 0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_mul_lo_u32 v10, v3, v13
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v9, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v2
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v14
-; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v11, v1, v5
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v15
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v8, v4
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GISEL-NEXT: v_mul_lo_u32 v7, v3, v4
-; GISEL-NEXT: v_mul_hi_u32 v8, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, 0, v4
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, 1, v4
-; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v13, vcc
-; GISEL-NEXT: v_mul_lo_u32 v15, v1, v2
-; GISEL-NEXT: v_mul_hi_u32 v16, v1, v2
-; GISEL-NEXT: v_mul_lo_u32 v17, 0, v2
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v2
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
+; GISEL-NEXT: v_mul_hi_u32 v9, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v12, 0, v4
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v4
+; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v2, vcc
+; GISEL-NEXT: v_mul_lo_u32 v15, v1, v7
+; GISEL-NEXT: v_mul_hi_u32 v16, v1, v7
+; GISEL-NEXT: v_mul_lo_u32 v17, 0, v7
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v7
; GISEL-NEXT: v_addc_u32_e32 v19, vcc, 0, v5, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v16, v9
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, 1, v12
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v16, v11
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v13
; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v14, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v17
-; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v7
-; GISEL-NEXT: v_subb_u32_e64 v7, s[4:5], 0, v8, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
+; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], 0, v9, vcc
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v3
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v15
-; GISEL-NEXT: v_subb_u32_e64 v15, s[6:7], 0, v9, s[4:5]
+; GISEL-NEXT: v_subb_u32_e64 v15, s[6:7], 0, v10, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v0, v1
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, -1, s[6:7]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8
; GISEL-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v15
-; GISEL-NEXT: v_add_i32_e64 v7, s[10:11], 1, v18
+; GISEL-NEXT: v_add_i32_e64 v8, s[10:11], 1, v18
; GISEL-NEXT: v_addc_u32_e64 v15, s[10:11], 0, v19, s[10:11]
-; GISEL-NEXT: v_sub_i32_e64 v8, s[10:11], 0, v8
; GISEL-NEXT: v_sub_i32_e64 v9, s[10:11], 0, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v11, -1, v11, s[6:7]
-; GISEL-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc
+; GISEL-NEXT: v_sub_i32_e64 v10, s[10:11], 0, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v12, -1, v12, s[6:7]
+; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v17, -1, v17, s[8:9]
-; GISEL-NEXT: v_subbrev_u32_e64 v9, vcc, 0, v9, s[4:5]
+; GISEL-NEXT: v_subbrev_u32_e64 v10, vcc, 0, v10, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v9, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v10, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GISEL-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v12, v10, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v18, v7, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v16, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v13, v11, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v14, v16, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT: v_cndmask_b32_e32 v6, v18, v8, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v8, v19, v15, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v4, v19, v15, s[4:5]
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v7, v6, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_udiv_v2i64_24bit:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
index 9d7cb130c44ea..046981b88361f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
@@ -2164,29 +2164,29 @@ define <2 x i64> @v_urem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v10, v3
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v8, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v0, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v12, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v11, -1, v11, vcc
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v10, v3
; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v2, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GISEL-NEXT: v_cndmask_b32_e32 v13, -1, v13, vcc
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v12, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v13, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v0, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v10, v2, v14, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
+; GISEL-NEXT: v_cndmask_b32_e32 v10, v12, v1, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v11, v0, v15, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v13, v15, s[4:5]
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v10, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_urem_v2i64_24bit:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index e17706ba6dd67..ec621dc18ef72 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -2861,9 +2861,9 @@ define i48 @v_usubsat_i48(i48 %lhs, i48 %rhs) {
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
@@ -2966,14 +2966,14 @@ define amdgpu_ps <2 x float> @usubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX6-LABEL: usubsat_i48_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s1
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
@@ -3024,14 +3024,14 @@ define amdgpu_ps <2 x float> @usubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX6-LABEL: usubsat_i48_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s1
-; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
@@ -3579,10 +3579,10 @@ define <2 x i128> @v_usubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v8
-; GFX10-NEXT: v_sub_co_u32 v4, s4, v4, v12
; GFX10-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s4, v5, v13, s4
+; GFX10-NEXT: v_sub_co_u32 v4, s4, v4, v12
; GFX10-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s4, v5, v13, s4
; GFX10-NEXT: v_sub_co_ci_u32_e64 v6, s4, v6, v14, s4
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e64 v7, s4, v7, v15, s4
@@ -3600,10 +3600,10 @@ define <2 x i128> @v_usubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v8
-; GFX11-NEXT: v_sub_co_u32 v4, s0, v4, v12
; GFX11-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, s0, v5, v13, s0
+; GFX11-NEXT: v_sub_co_u32 v4, s0, v4, v12
; GFX11-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, s0, v5, v13, s0
; GFX11-NEXT: v_sub_co_ci_u32_e64 v6, s0, v6, v14, s0
; GFX11-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
; GFX11-NEXT: v_sub_co_ci_u32_e64 v7, s0, v7, v15, s0
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
index 4f40948cab0a2..712d1f652045a 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
@@ -527,11 +527,11 @@ define void @flat_atomic_cmpxchg_i64_ret_av_av__a(ptr %ptr) #0 {
; CHECK-NEXT: v_accvgpr_write_b32 a0, v4
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[2:3]
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; CHECK-NEXT: v_accvgpr_write_b32 a1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; CHECK-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
+; CHECK-NEXT: v_accvgpr_write_b32 a1, v5
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; CHECK-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; CHECK-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; CHECK-NEXT: .LBB14_4: ; %atomicrmw.phi
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: ;;#ASMSTART
@@ -558,13 +558,13 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__a(ptr %ptr) #0 {
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; def a[2:3]
; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_accvgpr_read_b32 v5, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; def a[4:5]
; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v3, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; CHECK-NEXT: ; implicit-def: $agpr0_agpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -581,8 +581,8 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__a(ptr %ptr) #0 {
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: buffer_invl2
; CHECK-NEXT: buffer_wbinvl1_vol
-; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
+; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
; CHECK-NEXT: v_accvgpr_write_b32 a0, v0
; CHECK-NEXT: v_accvgpr_write_b32 a1, v1
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
@@ -597,12 +597,12 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__a(ptr %ptr) #0 {
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: v_accvgpr_write_b32 a0, v0
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[4:5]
-; CHECK-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
+; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
+; CHECK-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; CHECK-NEXT: v_accvgpr_write_b32 a1, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; CHECK-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; CHECK-NEXT: v_cndmask_b32_e32 v2, v1, v5, vcc
+; CHECK-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen
+; CHECK-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen offset:4
; CHECK-NEXT: .LBB15_4: ; %atomicrmw.phi
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: ;;#ASMSTART
@@ -850,11 +850,11 @@ define void @flat_atomic_cmpxchg_i64_ret_v_v__a(ptr %ptr) #0 {
; CHECK-NEXT: v_accvgpr_write_b32 a0, v4
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[2:3]
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; CHECK-NEXT: v_accvgpr_write_b32 a1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; CHECK-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
+; CHECK-NEXT: v_accvgpr_write_b32 a1, v5
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; CHECK-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; CHECK-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; CHECK-NEXT: .LBB19_4: ; %atomicrmw.phi
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
index 3dac24ed89fa0..2991d0a8c8e06 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
@@ -7412,21 +7412,21 @@ define void @flat_atomic_max_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_max_i64_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
+; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1
+; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX90A-NEXT: ; implicit-def: $agpr0_agpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB99_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
+; GFX90A-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
@@ -7436,19 +7436,19 @@ define void @flat_atomic_max_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB99_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v2, vcc
-; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(1)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB99_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: ;;#ASMSTART
@@ -7602,21 +7602,21 @@ define void @flat_atomic_min_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_min_i64_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
+; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1
+; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX90A-NEXT: ; implicit-def: $agpr0_agpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB101_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
+; GFX90A-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
@@ -7626,19 +7626,19 @@ define void @flat_atomic_min_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB101_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v2, vcc
-; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(1)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB101_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: ;;#ASMSTART
@@ -7792,21 +7792,21 @@ define void @flat_atomic_umax_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_umax_i64_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
+; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1
+; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX90A-NEXT: ; implicit-def: $agpr0_agpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB103_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
+; GFX90A-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
@@ -7816,19 +7816,19 @@ define void @flat_atomic_umax_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB103_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v2, vcc
-; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(1)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB103_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: ;;#ASMSTART
@@ -7982,21 +7982,21 @@ define void @flat_atomic_umin_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_umin_i64_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
+; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1
+; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX90A-NEXT: ; implicit-def: $agpr0_agpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB105_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
+; GFX90A-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
@@ -8006,19 +8006,19 @@ define void @flat_atomic_umin_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB105_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v2, vcc
-; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(1)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
-; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
+; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB105_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: ;;#ASMSTART
@@ -10840,8 +10840,8 @@ define void @flat_atomic_fmaximum_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: v_mov_b32_e32 v7, 0x7ff80000
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
+; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
@@ -11109,8 +11109,8 @@ define void @flat_atomic_fminimum_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: v_mov_b32_e32 v7, 0x7ff80000
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
+; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
@@ -15824,11 +15824,11 @@ define void @flat_atomic_max_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB207_4: ; %atomicrmw.end
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use a[0:1]
@@ -16008,11 +16008,11 @@ define void @flat_atomic_min_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB209_4: ; %atomicrmw.end
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use a[0:1]
@@ -16192,11 +16192,11 @@ define void @flat_atomic_umax_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB211_4: ; %atomicrmw.end
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use a[0:1]
@@ -16376,11 +16376,11 @@ define void @flat_atomic_umin_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
+; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB213_4: ; %atomicrmw.end
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use a[0:1]
@@ -19167,8 +19167,8 @@ define void @flat_atomic_fmaximum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_mov_b32_e32 v7, 0x7ff80000
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
+; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
@@ -19428,8 +19428,8 @@ define void @flat_atomic_fminimum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_mov_b32_e32 v7, 0x7ff80000
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
+; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 4652d0ae60fd0..bd450ea2c73d4 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -740,7 +740,7 @@ define <16 x ptr> @addrspacecast_v16p5_to_v16p0(<16 x ptr addrspace(5)> %ptr) {
; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; CI-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
+; CI-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v31, s4
; CI-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc
@@ -751,28 +751,28 @@ define <16 x ptr> @addrspacecast_v16p5_to_v16p0(<16 x ptr addrspace(5)> %ptr) {
; CI-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
; CI-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; CI-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
+; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
; CI-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
+; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
; CI-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
+; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; CI-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
; CI-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; CI-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; CI-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
+; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
; CI-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
+; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
; CI-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
+; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
; CI-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
+; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
; CI-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
+; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
; CI-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
+; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
; CI-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
+; CI-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; CI-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
; CI-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
; CI-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
@@ -814,30 +814,30 @@ define <16 x ptr> @addrspacecast_v16p5_to_v16p0(<16 x ptr addrspace(5)> %ptr) {
; GFX9-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; GFX9-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
; GFX9-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
; GFX9-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
; GFX9-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; GFX9-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
; GFX9-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; GFX9-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
@@ -1192,7 +1192,7 @@ define <16 x ptr> @addrspacecast_v16p3_to_v16p0(<16 x ptr addrspace(3)> %ptr) {
; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; CI-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
+; CI-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v31, s4
; CI-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc
@@ -1203,28 +1203,28 @@ define <16 x ptr> @addrspacecast_v16p3_to_v16p0(<16 x ptr addrspace(3)> %ptr) {
; CI-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
; CI-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; CI-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
+; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
; CI-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
+; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
; CI-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
+; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; CI-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
; CI-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; CI-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; CI-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
+; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
; CI-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
+; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
; CI-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
+; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
; CI-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
+; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
; CI-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
+; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
; CI-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
+; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
; CI-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
+; CI-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; CI-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
; CI-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
; CI-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
@@ -1266,30 +1266,30 @@ define <16 x ptr> @addrspacecast_v16p3_to_v16p0(<16 x ptr addrspace(3)> %ptr) {
; GFX9-NEXT: v_cndmask_b32_e32 v35, 0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v32, 0, v31, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; GFX9-NEXT: v_cndmask_b32_e32 v36, 0, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v4
; GFX9-NEXT: v_cndmask_b32_e64 v48, 0, v4, s[4:5]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v5
; GFX9-NEXT: v_cndmask_b32_e64 v37, 0, v5, s[6:7]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v6
; GFX9-NEXT: v_cndmask_b32_e64 v33, 0, v6, s[8:9]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v7
; GFX9-NEXT: v_cndmask_b32_e64 v38, 0, v7, s[10:11]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v8
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[12:13]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v9
; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[14:15]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v10
; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[16:17]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v11
; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[18:19]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v12
; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[20:21]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v13
; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[22:23]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v14
; GFX9-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[24:25]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[26:27], -1, v15
; GFX9-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[26:27]
; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v31, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v31, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/addsub64_carry.ll b/llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
index 8088c1b4c8fc7..172310726e6fe 100644
--- a/llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
+++ b/llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
@@ -121,9 +121,9 @@ define i64 @v_uadd_n1(i64 %val0, i64 %val1, ptr %ptrval) {
; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, -1, v0
; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CHECK-NEXT: flat_store_dwordx2 v[4:5], v[2:3]
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, v0
+; CHECK-NEXT: flat_store_dwordx2 v[4:5], v[2:3]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
%pair = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val0, i64 -1)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
index 7af5b0e177b7f..1d4d6bddf15c3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
@@ -11,8 +11,8 @@ define float @test_rootn_afn_f32(float %x, i32 %y) #0 {
; CHECK-LABEL: test_rootn_afn_f32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cvt_f32_i32_e32 v2, v1
+; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
; CHECK-NEXT: v_ldexp_f32 v4, |v0|, v4
@@ -62,15 +62,15 @@ define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: test_rootn_afn_v2f32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cvt_f32_i32_e32 v5, v3
+; CHECK-NEXT: s_mov_b32 s4, 0x800000
+; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v2
; CHECK-NEXT: v_mov_b32_e32 v6, 0x42000000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
-; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 32, vcc
-; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
; CHECK-NEXT: v_ldexp_f32 v8, |v1|, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
; CHECK-NEXT: v_log_f32_e32 v8, v8
; CHECK-NEXT: v_ldexp_f32 v9, |v0|, v9
@@ -86,8 +86,8 @@ define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
; CHECK-NEXT: v_mov_b32_e32 v6, 0x42800000
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v5
; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; CHECK-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v4
; CHECK-NEXT: v_add_f32_e32 v5, v5, v7
+; CHECK-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v4
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
; CHECK-NEXT: v_exp_f32_e32 v5, v5
; CHECK-NEXT: v_add_f32_e32 v4, v4, v6
@@ -99,14 +99,14 @@ define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
; CHECK-NEXT: v_ldexp_f32 v4, v4, v6
; CHECK-NEXT: v_and_b32_e32 v6, 1, v3
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
-; CHECK-NEXT: v_and_b32_e32 v7, 1, v2
; CHECK-NEXT: v_cndmask_b32_e64 v6, v1, 1.0, vcc
; CHECK-NEXT: s_brev_b32 s18, -2
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7
+; CHECK-NEXT: v_and_b32_e32 v7, 1, v2
; CHECK-NEXT: v_bfi_b32 v5, s18, v5, v6
; CHECK-NEXT: v_mov_b32_e32 v6, 0x204
; CHECK-NEXT: v_cmp_eq_f32_e64 s[10:11], 0, v1
; CHECK-NEXT: v_cmp_gt_i32_e64 s[14:15], 0, v3
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, v0, 1.0, s[4:5]
; CHECK-NEXT: v_cmp_class_f32_e64 s[6:7], v1, v6
; CHECK-NEXT: v_cmp_class_f32_e64 s[8:9], v0, v6
diff --git a/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll b/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
index 4e5ad79b72468..c1035e5ad4a75 100644
--- a/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
@@ -51,15 +51,15 @@ define void @interleaved_with_wave_barrier(ptr addrspace(1) %foo, ptr addrspace(
; GISEL-NEXT: s_wait_kmcnt 0x0
; GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GISEL-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
-; GISEL-NEXT: v_add_co_u32 v6, vcc_lo, 0x54, v0
; GISEL-NEXT: v_add_nc_u32_e32 v3, 0x54, v2
+; GISEL-NEXT: v_add_co_u32 v6, vcc_lo, 0x54, v0
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
; GISEL-NEXT: global_load_b32 v10, v[8:9], off offset:44
; GISEL-NEXT: global_load_b32 v11, v[0:1], off offset:4
; GISEL-NEXT: ; wave barrier
; GISEL-NEXT: global_load_async_to_lds_b32 v3, v[6:7], off offset:4 th:TH_LOAD_NT nv
; GISEL-NEXT: v_add_co_u32 v6, vcc_lo, 0x58, v8
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v9, vcc_lo
; GISEL-NEXT: v_add_nc_u32_e32 v3, 0x58, v2
; GISEL-NEXT: ; wave barrier
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 0ee94a1bb7d05..0cbbc53ceb45d 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -2597,11 +2597,11 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_add_co_u32 v0, vcc, s2, v0
-; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc
; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1164_ITERATIVE-NEXT: s_endpgm
;
@@ -3144,54 +3144,55 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP: ; %bb.0: ; %entry
; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 31
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@@ -3242,12 +3243,12 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v4
; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v5
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_u32 v6, vcc, s2, v8
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: s_mov_b32 s2, s6
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v7, null, s3, v9, vcc
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164_DPP-NEXT: s_mov_b32 s2, s6
; GFX1164_DPP-NEXT: buffer_store_b64 v[6:7], off, s[0:3], 0
; GFX1164_DPP-NEXT: s_endpgm
;
@@ -3264,18 +3265,18 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -3347,46 +3348,46 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
-; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
-; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1264_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_readlane_b32 s2, v1, 31
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1264_DPP-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -3462,45 +3463,45 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1232_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1232_DPP-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1232_DPP-NEXT: s_or_saveexec_b32 s6, -1
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX1232_DPP-NEXT: v_readlane_b32 s4, v2, 31
; GFX1232_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: v_readlane_b32 s7, v2, 15
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX1232_DPP-NEXT: v_readlane_b32 s8, v1, 15
; GFX1232_DPP-NEXT: v_readlane_b32 s5, v1, 31
; GFX1232_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: s_mov_b32 exec_lo, s6
-; GFX1232_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1232_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1232_DPP-NEXT: s_or_saveexec_b32 s6, -1
; GFX1232_DPP-NEXT: v_writelane_b32 v6, s7, 16
@@ -5847,9 +5848,9 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1164-NEXT: v_subrev_co_ci_u32_e64 v6, null, 0, v8, vcc
; GFX1164-NEXT: v_mov_b32_e32 v0, v5
; GFX1164-NEXT: v_mov_b32_e32 v2, v7
-; GFX1164-NEXT: v_mov_b32_e32 v3, v8
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1164-NEXT: v_mov_b32_e32 v1, v6
+; GFX1164-NEXT: v_mov_b32_e32 v3, v8
; GFX1164-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1164-NEXT: s_waitcnt vmcnt(0)
; GFX1164-NEXT: buffer_gl1_inv
@@ -5870,11 +5871,11 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1164-NEXT: v_mul_u32_u24_e32 v0, 5, v4
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v4
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-NEXT: v_sub_co_u32 v0, vcc, s2, v0
-; GFX1164-NEXT: s_mov_b32 s2, -1
; GFX1164-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164-NEXT: s_mov_b32 s2, -1
; GFX1164-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1164-NEXT: s_endpgm
;
@@ -6375,9 +6376,9 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1164-NEXT: v_subrev_co_ci_u32_e64 v6, null, s15, v8, vcc
; GFX1164-NEXT: v_mov_b32_e32 v0, v5
; GFX1164-NEXT: v_mov_b32_e32 v2, v7
-; GFX1164-NEXT: v_mov_b32_e32 v3, v8
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1164-NEXT: v_mov_b32_e32 v1, v6
+; GFX1164-NEXT: v_mov_b32_e32 v3, v8
; GFX1164-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1164-NEXT: s_waitcnt vmcnt(0)
; GFX1164-NEXT: buffer_gl1_inv
@@ -6975,9 +6976,9 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_ITERATIVE-NEXT: v_subrev_co_ci_u32_e64 v7, null, s9, v9, vcc
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, v8
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, v9
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, v9
; GFX1164_ITERATIVE-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1164_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1164_ITERATIVE-NEXT: buffer_gl1_inv
@@ -6997,9 +6998,10 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164_ITERATIVE-NEXT: v_sub_co_u32 v0, vcc, s2, v4
-; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v5, vcc
; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1164_ITERATIVE-NEXT: s_endpgm
;
@@ -7655,54 +7657,55 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP: ; %bb.0: ; %entry
; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 31
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@@ -7777,12 +7780,12 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v4
; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v5
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_sub_co_u32 v6, vcc, s2, v8
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: v_sub_co_ci_u32_e64 v7, null, s3, v9, vcc
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: buffer_store_b64 v[6:7], off, s[0:3], 0
; GFX1164_DPP-NEXT: s_endpgm
;
@@ -7799,18 +7802,18 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -7904,46 +7907,46 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
-; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
-; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1264_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_readlane_b32 s2, v1, 31
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1264_DPP-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -8019,45 +8022,45 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1232_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1232_DPP-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1232_DPP-NEXT: s_or_saveexec_b32 s6, -1
-; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX1232_DPP-NEXT: v_readlane_b32 s4, v2, 31
; GFX1232_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: v_readlane_b32 s7, v2, 15
+; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX1232_DPP-NEXT: v_readlane_b32 s8, v1, 15
; GFX1232_DPP-NEXT: v_readlane_b32 s5, v1, 31
; GFX1232_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: s_mov_b32 exec_lo, s6
-; GFX1232_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1232_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1232_DPP-NEXT: s_or_saveexec_b32 s6, -1
; GFX1232_DPP-NEXT: v_writelane_b32 v6, s7, 16
@@ -13526,8 +13529,8 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
@@ -13627,8 +13630,8 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1064-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1064-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1064-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1064-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1]
+; GFX1064-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX1064-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX1064-NEXT: v_mov_b32_e32 v3, v1
; GFX1064-NEXT: v_mov_b32_e32 v2, v0
@@ -13676,8 +13679,8 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1032-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1032-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1032-NEXT: v_cmp_u_f32_e64 s0, v0, v0
-; GFX1032-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v3, v5, s0
+; GFX1032-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX1032-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX1032-NEXT: v_mov_b32_e32 v3, v1
; GFX1032-NEXT: v_mov_b32_e32 v2, v0
@@ -13777,28 +13780,27 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-FAKE16-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX1164-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX1164-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX1164-FAKE16-NEXT: v_add_f32_e32 v0, s12, v0
-; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX1164-FAKE16-NEXT: v_add_f32_e32 v2, s13, v2
-; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
-; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT: v_add_f32_e32 v0, s12, v0
; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1164-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX1164-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX1164-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
+; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
; GFX1164-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1]
-; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
+; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v3, v1
-; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v2, v0
; GFX1164-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1164-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -13909,9 +13911,9 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1132-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1132-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1132-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
-; GFX1132-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX1132-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s0
+; GFX1132-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX1132-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX1132-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
@@ -14021,14 +14023,14 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1264-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1264-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1264-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1]
-; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1264-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX1264-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX1264-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264-FAKE16-NEXT: v_mov_b32_e32 v2, v0
; GFX1264-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1264-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -14134,13 +14136,13 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1232-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1232-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
-; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1232-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s0
-; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1232-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX1232-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
+; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
; GFX1232-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1232-FAKE16-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 6a09b269867c9..a64745a54ff04 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -2223,11 +2223,11 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_add_co_u32 v0, vcc, s2, v0
-; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc
; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1164_ITERATIVE-NEXT: s_endpgm
@@ -2630,29 +2630,30 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP: ; %bb.0: ; %entry
; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0
-; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -2725,10 +2726,10 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v5
; GFX1164_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v8
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_add_co_u32 v7, vcc, s3, v9
-; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v8, null, s4, v10, vcc
+; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
; GFX1164_DPP-NEXT: s_endpgm
@@ -2746,18 +2747,18 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -3284,45 +3285,45 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1164_DPP: ; %bb.0: ; %entry
; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:1 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: v_permlanex16_b32 v3, v2, 0, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_permlanex16_b32 v3, v2, 0, 0
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_u32 v2, vcc, v2, v3
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, 0, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlane64_b32 v3, v2
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_permlane64_b32 v4, v1
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_add_co_u32 v2, vcc, v2, v3
@@ -3356,18 +3357,18 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:2 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -5027,11 +5028,11 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-NEXT: v_sub_co_u32 v0, vcc, s2, v0
-; GFX1164-NEXT: s_mov_b32 s2, -1
; GFX1164-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164-NEXT: s_mov_b32 s2, -1
; GFX1164-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1164-NEXT: s_endpgm
@@ -5635,11 +5636,11 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_sub_co_u32 v0, vcc, s2, v0
-; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc
; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1164_ITERATIVE-NEXT: s_endpgm
@@ -6042,29 +6043,30 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP: ; %bb.0: ; %entry
; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0
-; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -6137,10 +6139,10 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v5
; GFX1164_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v8
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_sub_co_u32 v7, vcc, s3, v9
-; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: v_sub_co_ci_u32_e64 v8, null, s4, v10, vcc
+; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
; GFX1164_DPP-NEXT: s_endpgm
@@ -6158,18 +6160,18 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1132_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1132_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -11053,11 +11055,11 @@ define amdgpu_kernel void @max_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: buffer_gl0_inv
; GFX1164-NEXT: .LBB22_2:
; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
-; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -11417,9 +11419,10 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1164_ITERATIVE-NEXT: .LBB23_4:
; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
@@ -11724,35 +11727,35 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, s3
; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1064_DPP-NEXT: v_bfrev_b32_e32 v5, 1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1064_DPP-NEXT: v_bfrev_b32_e32 v6, 1
; GFX1064_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1064_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1064_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1064_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1064_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
@@ -11772,8 +11775,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1064_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064_DPP-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[7:8]
; GFX1064_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
@@ -11821,23 +11824,23 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_permlanex16_b32 v6, v1, -1, -1
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1032_DPP-NEXT: v_bfrev_b32_e32 v5, 1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1032_DPP-NEXT: v_bfrev_b32_e32 v6, 1
; GFX1032_DPP-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1032_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1032_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1032_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
@@ -11857,8 +11860,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1032_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032_DPP-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[7:8]
; GFX1032_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
@@ -11935,40 +11938,39 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v6, 1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1164_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1164_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1164_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1164_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1164_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -11987,8 +11989,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[7:8]
@@ -12043,24 +12045,25 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1132_DPP-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1132_DPP-NEXT: v_bfrev_b32_e32 v6, 1
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1132_DPP-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1132_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1132_DPP-NEXT: v_readlane_b32 s1, v2, 31
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1132_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
+; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1132_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -12077,7 +12080,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v6
; GFX1132_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[7:8]
@@ -12876,11 +12879,11 @@ define amdgpu_kernel void @min_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: buffer_gl0_inv
; GFX1164-NEXT: .LBB25_2:
; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
-; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -13240,9 +13243,10 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1164_ITERATIVE-NEXT: .LBB26_4:
; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
@@ -13547,35 +13551,35 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, s3
; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1064_DPP-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v5, -1
+; GFX1064_DPP-NEXT: v_bfrev_b32_e32 v6, -2
; GFX1064_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, -1
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1064_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1064_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1064_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1064_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
@@ -13595,8 +13599,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1064_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064_DPP-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[7:8]
; GFX1064_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
@@ -13644,23 +13648,23 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_permlanex16_b32 v6, v1, -1, -1
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1032_DPP-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v5, -1
+; GFX1032_DPP-NEXT: v_bfrev_b32_e32 v6, -2
; GFX1032_DPP-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, -1
-; GFX1032_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1032_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1032_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
@@ -13680,8 +13684,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1032_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032_DPP-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[4:5], v[7:8]
; GFX1032_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
@@ -13758,40 +13762,39 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v5, -2
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, -1
+; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, -1
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1164_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1164_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1164_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1164_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1164_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -13810,8 +13813,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[7:8]
@@ -13866,24 +13869,25 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1132_DPP-NEXT: v_bfrev_b32_e32 v5, -2
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v5, -1
+; GFX1132_DPP-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1132_DPP-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, -1
-; GFX1132_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1132_DPP-NEXT: v_readlane_b32 s1, v2, 31
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1132_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
+; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1132_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -13900,7 +13904,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v6
; GFX1132_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[4:5], v[7:8]
@@ -14695,11 +14699,11 @@ define amdgpu_kernel void @umax_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: buffer_gl0_inv
; GFX1164-NEXT: .LBB28_2:
; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164-NEXT: v_mov_b32_e32 v1, 0
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
-; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -15053,9 +15057,10 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1164_ITERATIVE-NEXT: .LBB29_4:
; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
@@ -15362,34 +15367,34 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1064_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1064_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1064_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1064_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1064_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
@@ -15409,8 +15414,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1064_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[7:8]
; GFX1064_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
@@ -15459,22 +15464,22 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1032_DPP-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1032_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1032_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1032_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
@@ -15494,8 +15499,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1032_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032_DPP-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[7:8]
; GFX1032_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
@@ -15573,39 +15578,38 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1164_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1164_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1164_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1164_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1164_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -15624,8 +15628,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[7:8]
@@ -15675,23 +15679,25 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1132_DPP-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v2, v4, v2
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v1, v3, v1
-; GFX1132_DPP-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1132_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX1132_DPP-NEXT: v_readlane_b32 s1, v2, 31
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1132_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
+; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1132_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -15708,7 +15714,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v6
; GFX1132_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[7:8]
@@ -16504,11 +16510,11 @@ define amdgpu_kernel void @umin_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: buffer_gl0_inv
; GFX1164-NEXT: .LBB31_2:
; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
; GFX1164-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
-; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -16862,9 +16868,10 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1164_ITERATIVE-NEXT: .LBB32_4:
; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3
; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
@@ -17169,34 +17176,34 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_e32 v5, -1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, -1
; GFX1064_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, -1
; GFX1064_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1064_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1064_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1064_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1064_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
@@ -17216,8 +17223,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1064_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064_DPP-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[7:8]
; GFX1064_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
@@ -17266,22 +17273,22 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_e32 v5, -1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v6, -1
; GFX1032_DPP-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1032_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, -1
-; GFX1032_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1032_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1032_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
@@ -17301,8 +17308,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1032_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032_DPP-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[4:5], v[7:8]
; GFX1032_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
@@ -17380,39 +17387,38 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, -1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, -1
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1164_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1164_DPP-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s3, 16
-; GFX1164_DPP-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1164_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1164_DPP-NEXT: v_readlane_b32 s9, v1, 47
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
@@ -17431,8 +17437,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v4
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v6
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[7:8]
@@ -17482,23 +17488,25 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v6, -1
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[3:4]
; GFX1132_DPP-NEXT: v_dual_mov_b32 v5, -1 :: v_dual_cndmask_b32 v2, v4, v2
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v4, -1 :: v_dual_cndmask_b32 v1, v3, v1
-; GFX1132_DPP-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1132_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX1132_DPP-NEXT: v_readlane_b32 s1, v2, 31
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1132_DPP-NEXT: v_readlane_b32 s0, v1, 31
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
+; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1132_DPP-NEXT: v_writelane_b32 v6, s6, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
-; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -17515,7 +17523,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s5, v8
; GFX1132_DPP-NEXT: v_readfirstlane_b32 s4, v7
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v6
; GFX1132_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[4:5], v[7:8]
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 4b917977acd58..2827d3d12416a 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -150,15 +150,15 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX-942-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-942-NEXT: s_movk_i32 s4, 0x7fff
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
-; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX-942-NEXT: s_movk_i32 s4, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s4
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
@@ -167,19 +167,19 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX-942-NEXT: v_cvt_f32_f64_e32 v5, v[2:3]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
; GFX-942-NEXT: v_and_b32_e32 v6, 1, v5
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[0:1]|
; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v6
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[0:1]|
+; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
; GFX-942-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v0, v5, v0
-; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX-942-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX-942-NEXT: v_add3_u32 v1, v1, v0, s4
; GFX-942-NEXT: v_or_b32_e32 v0, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[2:3]
-; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
-; GFX-942-NEXT: s_nop 0
+; GFX-942-NEXT: s_nop 1
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX-942-NEXT: v_perm_b32 v0, v0, v4, s0
; GFX-942-NEXT: ; return to shader part epilog
@@ -190,21 +190,22 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX-950-NEXT: v_and_b32_e32 v4, 1, v6
; GFX-950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], v[2:3], v[4:5]
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[4:5]|
; GFX-950-NEXT: v_cvt_f32_f64_e32 v7, v[0:1]
+; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-950-NEXT: v_cndmask_b32_e64 v2, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v2, v6, v2
-; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-950-NEXT: v_and_b32_e32 v8, 1, v7
; GFX-950-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[2:3], v7
-; GFX-950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
; GFX-950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], v[0:1], v[2:3]
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-950-NEXT: s_nop 0
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v7, v0
-; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, v4
; GFX-950-NEXT: ; return to shader part epilog
@@ -217,17 +218,17 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v8
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[6:7], v9
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[2:3]|, |v[4:5]|
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[2:3], v[4:5]
; GFX1250-NEXT: v_cmp_nlg_f64_e64 s0, v[0:1], v[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[2:3]|, |v[4:5]|
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cndmask_b32_e64 v2, -1, 1, s1
+; GFX1250-NEXT: v_and_b32_e32 v10, 1, v8
; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[6:7]|
-; GFX1250-NEXT: v_dual_add_nc_u32 v1, v8, v2 :: v_dual_bitop2_b32 v10, 1, v8 bitop3:0x40
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_cndmask_b32_e64 v0, -1, 1, s1
-; GFX1250-NEXT: v_and_b32_e32 v11, 1, v9
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_dual_add_nc_u32 v1, v8, v2 :: v_dual_bitop2_b32 v11, 1, v9 bitop3:0x40
; GFX1250-NEXT: v_cmp_ne_u32_e64 s1, 0, v10
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_add_nc_u32_e32 v0, v9, v0
@@ -444,15 +445,15 @@ define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX-942-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
-; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
@@ -466,12 +467,13 @@ define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX-950-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-950-NEXT: s_nop 0
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
-; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
@@ -483,9 +485,9 @@ define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX1250-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
-; GFX1250-NEXT: v_cmp_gt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX1250-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_cmp_gt_f64_e64 s0, |v[0:1]|, |v[4:5]|
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cndmask_b32_e64 v0, -1, 1, s0
; GFX1250-NEXT: v_dual_add_nc_u32 v0, v6, v0 :: v_dual_bitop2_b32 v7, 1, v6 bitop3:0x40
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
@@ -507,15 +509,15 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], -v[0:1], v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
-; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
@@ -529,12 +531,13 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], -v[0:1], v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-950-NEXT: s_nop 0
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
-; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
@@ -546,9 +549,9 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX1250-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
-; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[4:5]|
; GFX1250-NEXT: v_cmp_nlg_f64_e64 s0, -v[0:1], v[4:5]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[4:5]|
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cndmask_b32_e64 v0, -1, 1, s1
; GFX1250-NEXT: v_dual_add_nc_u32 v0, v6, v0 :: v_dual_bitop2_b32 v7, 1, v6 bitop3:0x40
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -572,15 +575,15 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
-; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[0:1]|
@@ -594,12 +597,13 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-950-NEXT: s_nop 0
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
-; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
@@ -611,9 +615,9 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX1250-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
-; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[4:5]|
; GFX1250-NEXT: v_cmp_nlg_f64_e64 s0, |v[0:1]|, v[4:5]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[4:5]|
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cndmask_b32_e64 v0, -1, 1, s1
; GFX1250-NEXT: v_dual_add_nc_u32 v0, v6, v0 :: v_dual_bitop2_b32 v7, 1, v6 bitop3:0x40
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index a066211e56b13..2124d681d66d1 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -1636,8 +1636,8 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX8-NEXT: v_and_b32_e32 v7, 1, v6
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; GFX8-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v4, s[6:7], v6, v4
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -1663,8 +1663,8 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX900-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX900-NEXT: v_and_b32_e32 v7, 1, v6
; GFX900-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
-; GFX900-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; GFX900-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; GFX900-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; GFX900-NEXT: v_add_u32_e32 v4, v6, v4
; GFX900-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -1686,12 +1686,13 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX950-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX950-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
+; GFX950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX950-NEXT: v_add_u32_e32 v0, v6, v0
-; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX950-NEXT: global_store_short v[2:3], v0, off
@@ -1706,8 +1707,8 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX10-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX10-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX10-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX10-NEXT: v_cmp_gt_f64_e64 s4, |v[0:1]|, |v[4:5]|
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_gt_f64_e64 s4, |v[0:1]|, |v[4:5]|
; GFX10-NEXT: v_cndmask_b32_e64 v4, -1, 1, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v7
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
@@ -1730,9 +1731,9 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX11-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX11-NEXT: v_cmp_gt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX11-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_gt_f64_e64 s0, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v4, -1, 1, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -1758,10 +1759,10 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX1250-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
-; GFX1250-NEXT: v_cmp_gt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX1250-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX1250-NEXT: v_cmp_gt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cndmask_b32_e64 v0, -1, 1, s0
; GFX1250-NEXT: v_dual_add_nc_u32 v0, v6, v0 :: v_dual_bitop2_b32 v7, 1, v6 bitop3:0x40
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
@@ -29591,8 +29592,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX7-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX7-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX7-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX7-NEXT: s_mov_b32 s4, 0x7f800000
; GFX7-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX7-NEXT: s_mov_b32 s4, 0x7f800000
; GFX7-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -29648,8 +29649,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -29679,8 +29680,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX950-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX950-NEXT: v_fma_f32 v2, v0, s0, -v1
; GFX950-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
; GFX950-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
; GFX950-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, s0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
@@ -30017,8 +30018,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX7-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX7-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX7-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX7-NEXT: s_mov_b32 s4, 0x7f800000
; GFX7-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX7-NEXT: s_mov_b32 s4, 0x7f800000
; GFX7-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -30074,8 +30075,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -30105,8 +30106,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX950-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX950-NEXT: v_fma_f32 v2, v0, s0, -v1
; GFX950-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
; GFX950-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
; GFX950-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, s0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
@@ -34513,14 +34514,14 @@ define <3 x i64> @v_fptosi_v3bf16_to_v3i64(<3 x bfloat> %x) {
; GFX11-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: v_xor_b32_e32 v3, v3, v5
; GFX11-NEXT: v_xor_b32_e32 v2, v2, v5
; GFX11-NEXT: v_xor_b32_e32 v9, v0, v7
; GFX11-NEXT: v_xor_b32_e32 v4, v4, v7
-; GFX11-NEXT: v_xor_b32_e32 v10, v1, v8
; GFX11-NEXT: v_xor_b32_e32 v6, v6, v8
+; GFX11-NEXT: v_xor_b32_e32 v10, v1, v8
; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v2, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_sub_co_ci_u32_e64 v1, null, v3, v5, vcc_lo
@@ -34938,40 +34939,40 @@ define <4 x i64> @v_fptosi_v4bf16_to_v4i64(<4 x bfloat> %x) {
; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v2
; GFX11-NEXT: v_floor_f32_e32 v1, v1
; GFX11-NEXT: v_floor_f32_e32 v6, v6
-; GFX11-NEXT: v_ashrrev_i32_e32 v7, 31, v0
; GFX11-NEXT: v_floor_f32_e32 v8, v8
+; GFX11-NEXT: v_ashrrev_i32_e32 v7, 31, v0
; GFX11-NEXT: v_floor_f32_e32 v9, v9
; GFX11-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v2|
; GFX11-NEXT: v_fma_f32 v0, 0xcf800000, v6, |v0|
; GFX11-NEXT: v_ashrrev_i32_e32 v10, 31, v3
-; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v8, |v3|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX11-NEXT: v_fma_f32 v11, 0xcf800000, v9, |v4|
-; GFX11-NEXT: v_xor_b32_e32 v1, v1, v5
-; GFX11-NEXT: v_xor_b32_e32 v2, v2, v5
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX11-NEXT: v_xor_b32_e32 v3, v0, v7
+; GFX11-NEXT: v_xor_b32_e32 v2, v2, v5
; GFX11-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX11-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX11-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX11-NEXT: v_xor_b32_e32 v6, v6, v7
; GFX11-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX11-NEXT: v_xor_b32_e32 v3, v0, v7
; GFX11-NEXT: v_ashrrev_i32_e32 v13, 31, v4
; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v2, v5
-; GFX11-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX11-NEXT: v_xor_b32_e32 v4, v12, v10
; GFX11-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v3, v7
-; GFX11-NEXT: v_xor_b32_e32 v4, v12, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, v6, v7, vcc_lo
; GFX11-NEXT: v_xor_b32_e32 v5, v8, v10
-; GFX11-NEXT: v_xor_b32_e32 v6, v11, v13
; GFX11-NEXT: v_xor_b32_e32 v7, v9, v13
+; GFX11-NEXT: v_xor_b32_e32 v6, v11, v13
; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v5, v10, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_sub_co_ci_u32_e64 v7, null, v7, v13, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -41341,8 +41342,8 @@ define <2 x bfloat> @v_select_v2bf16(i1 %cond, <2 x bfloat> %a, <2 x bfloat> %b)
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -41485,8 +41486,8 @@ define <2 x bfloat> @v_vselect_v2bf16(<2 x i1> %cond, <2 x bfloat> %a, <2 x bflo
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5]
; GFX8-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
@@ -41527,8 +41528,8 @@ define <2 x bfloat> @v_vselect_v2bf16(<2 x i1> %cond, <2 x bfloat> %a, <2 x bflo
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v0
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v2, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -41716,8 +41717,8 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GCN-NEXT: v_mov_b32_e32 v4, s2
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_readfirstlane_b32 s0, v0
@@ -41795,8 +41796,8 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo
+; GFX10-NEXT: s_lshr_b32 s0, s1, 16
+; GFX10-NEXT: v_cndmask_b32_e32 v0, s0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, s1, v2, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
@@ -41821,9 +41822,9 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX11FAKE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11FAKE16-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s0
-; GFX11FAKE16-NEXT: s_lshr_b32 s3, s1, 16
+; GFX11FAKE16-NEXT: s_lshr_b32 s0, s1, 16
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, s0, v1, vcc_lo
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, s1, v2, vcc_lo
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
@@ -41852,9 +41853,9 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX1250FAKE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250FAKE16-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s0
-; GFX1250FAKE16-NEXT: s_lshr_b32 s3, s1, 16
+; GFX1250FAKE16-NEXT: s_lshr_b32 s0, s1, 16
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo
+; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, s0, v1, vcc_lo
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, s1, v2, vcc_lo
; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
@@ -43285,9 +43286,9 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX900-NEXT: v_and_b32_e32 v1, 1, v2
; GFX900-NEXT: v_cndmask_b32_sdwa v2, v7, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX900-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v1
; GFX900-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
; GFX900-NEXT: s_mov_b64 vcc, s[4:5]
+; GFX900-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v1
; GFX900-NEXT: v_cndmask_b32_e64 v1, v7, v5, s[6:7]
; GFX900-NEXT: v_cndmask_b32_sdwa v3, v6, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
@@ -43327,13 +43328,13 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v1
; GFX10-NEXT: v_and_b32_e32 v1, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v4, s5
; GFX10-NEXT: v_cndmask_b32_sdwa v2, v7, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_sdwa v3, v6, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v4, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v3, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc_lo
; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -43888,9 +43889,9 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX7-NEXT: v_and_b32_e32 v10, 1, v12
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v10
; GFX7-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX7-NEXT: v_and_b32_e32 v10, 1, v13
; GFX7-NEXT: v_cndmask_b32_e64 v12, v30, v22, s[4:5]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
-; GFX7-NEXT: v_and_b32_e32 v10, 1, v13
; GFX7-NEXT: v_cndmask_b32_e64 v11, v29, v21, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e32 v13, v29, v21, vcc
; GFX7-NEXT: buffer_load_dword v21, off, s[0:3], s32
@@ -44222,22 +44223,22 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v17
; GFX10-NEXT: v_cndmask_b32_e32 v11, v36, v35, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v17
; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v25
; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v12
+; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
; GFX10-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
-; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v12
; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v16
; GFX10-NEXT: v_cndmask_b32_e64 v22, v30, v22, s4
-; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v24
; GFX10-NEXT: v_cndmask_b32_e32 v9, v38, v37, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v24
; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v18
; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v26
; GFX10-NEXT: v_and_b32_e32 v14, 1, v14
@@ -44543,9 +44544,9 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GCN-NEXT: v_and_b32_e32 v0, 1, v1
-; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
; GCN-NEXT: v_and_b32_e32 v0, 1, v2
; GCN-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0
; GCN-NEXT: v_and_b32_e32 v0, 1, v3
@@ -44584,9 +44585,9 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GCN-NEXT: v_and_b32_e32 v19, 1, v29
; GCN-NEXT: v_and_b32_e32 v20, 1, v30
; GCN-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:24
+; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20
; GCN-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v1
-; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88
+; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:24
; GCN-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v2
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:28
; GCN-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v3
@@ -44613,24 +44614,24 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124
; GCN-NEXT: v_cmp_eq_u32_e64 s[78:79], 1, v14
; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v19
; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_cndmask_b32_e32 v14, v12, v11, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
+; GCN-NEXT: v_cndmask_b32_e64 v14, v12, v11, s[6:7]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v15
; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:120
-; GCN-NEXT: v_cndmask_b32_e32 v15, v12, v11, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v15, v12, v11, s[6:7]
; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:52
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v18
; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_cndmask_b32_e32 v13, v19, v22, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
+; GCN-NEXT: v_cndmask_b32_e64 v13, v19, v22, s[6:7]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v16
; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:116
-; GCN-NEXT: v_cndmask_b32_e32 v16, v19, v22, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v16, v19, v22, s[6:7]
; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v17
; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_cndmask_b32_e32 v12, v18, v11, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v20
+; GCN-NEXT: v_cndmask_b32_e64 v12, v18, v11, s[6:7]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v20
; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108
; GCN-NEXT: v_cndmask_b32_e64 v17, v18, v11, s[78:79]
; GCN-NEXT: s_waitcnt vmcnt(1)
@@ -44645,61 +44646,62 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GCN-NEXT: v_cndmask_b32_e64 v21, v7, v6, s[46:47]
; GCN-NEXT: v_cndmask_b32_e64 v7, v5, v4, s[44:45]
; GCN-NEXT: v_cndmask_b32_e64 v22, v5, v4, s[42:43]
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88
+; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:84
; GCN-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[40:41]
; GCN-NEXT: v_cndmask_b32_e64 v23, v3, v2, s[28:29]
-; GCN-NEXT: v_cndmask_b32_e64 v5, v1, v0, s[26:27]
-; GCN-NEXT: v_cndmask_b32_e64 v24, v1, v0, s[24:25]
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12
-; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:20
-; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84
-; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:16
-; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:80
-; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
-; GCN-NEXT: s_waitcnt vmcnt(3)
-; GCN-NEXT: v_cndmask_b32_e64 v4, v2, v1, s[22:23]
-; GCN-NEXT: v_cndmask_b32_e64 v25, v2, v1, s[20:21]
; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_cndmask_b32_e64 v3, v27, v26, s[18:19]
-; GCN-NEXT: v_cndmask_b32_e64 v26, v27, v26, s[16:17]
+; GCN-NEXT: v_cndmask_b32_e64 v5, v4, v1, s[26:27]
+; GCN-NEXT: v_cndmask_b32_e64 v24, v4, v1, s[24:25]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_cndmask_b32_e64 v2, v28, v0, s[14:15]
-; GCN-NEXT: v_cndmask_b32_e64 v27, v28, v0, s[12:13]
+; GCN-NEXT: v_cndmask_b32_e64 v4, v25, v0, s[22:23]
+; GCN-NEXT: v_cndmask_b32_e64 v25, v25, v0, s[20:21]
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8
-; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72
-; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:4
-; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:68
-; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32
+; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80
+; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:12
+; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
+; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:72
; GCN-NEXT: s_waitcnt vmcnt(3)
-; GCN-NEXT: v_cndmask_b32_e64 v31, v1, v0, s[10:11]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v0, s[8:9]
+; GCN-NEXT: v_cndmask_b32_e64 v3, v2, v1, s[18:19]
+; GCN-NEXT: v_cndmask_b32_e64 v26, v2, v1, s[16:17]
; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_cndmask_b32_e64 v0, v29, v28, s[6:7]
-; GCN-NEXT: v_cndmask_b32_e64 v28, v29, v28, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e64 v2, v28, v27, s[14:15]
+; GCN-NEXT: v_cndmask_b32_e64 v27, v28, v27, s[12:13]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v29, 1, v30
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29
-; GCN-NEXT: s_mov_b32 s6, 0xffff
-; GCN-NEXT: v_bfi_b32 v0, s6, v28, v0
-; GCN-NEXT: v_bfi_b32 v1, s6, v1, v31
-; GCN-NEXT: v_bfi_b32 v2, s6, v27, v2
-; GCN-NEXT: v_bfi_b32 v3, s6, v26, v3
-; GCN-NEXT: v_bfi_b32 v4, s6, v25, v4
-; GCN-NEXT: v_bfi_b32 v5, s6, v24, v5
-; GCN-NEXT: v_bfi_b32 v6, s6, v23, v6
-; GCN-NEXT: v_bfi_b32 v7, s6, v22, v7
-; GCN-NEXT: v_bfi_b32 v8, s6, v21, v8
-; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64
-; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128
-; GCN-NEXT: v_bfi_b32 v9, s6, v20, v9
-; GCN-NEXT: v_bfi_b32 v10, s6, v19, v10
-; GCN-NEXT: v_bfi_b32 v11, s6, v18, v11
+; GCN-NEXT: v_cndmask_b32_e64 v1, v29, v0, s[10:11]
+; GCN-NEXT: v_cndmask_b32_e64 v28, v29, v0, s[8:9]
+; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:4
+; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:68
+; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:64
+; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: v_cndmask_b32_e64 v33, v30, v29, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v29, v30, v29, vcc
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_and_b32_e32 v30, 1, v31
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc
-; GCN-NEXT: v_bfi_b32 v12, s6, v17, v12
-; GCN-NEXT: v_bfi_b32 v13, s6, v16, v13
-; GCN-NEXT: v_cndmask_b32_e64 v16, v22, v21, s[4:5]
-; GCN-NEXT: v_bfi_b32 v14, s6, v15, v14
-; GCN-NEXT: v_bfi_b32 v15, s6, v18, v16
+; GCN-NEXT: v_cndmask_b32_e64 v30, v32, v0, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e32 v31, v32, v0, vcc
+; GCN-NEXT: s_mov_b32 s4, 0xffff
+; GCN-NEXT: v_bfi_b32 v0, s4, v29, v33
+; GCN-NEXT: v_bfi_b32 v1, s4, v28, v1
+; GCN-NEXT: v_bfi_b32 v2, s4, v27, v2
+; GCN-NEXT: v_bfi_b32 v3, s4, v26, v3
+; GCN-NEXT: v_bfi_b32 v4, s4, v25, v4
+; GCN-NEXT: v_bfi_b32 v5, s4, v24, v5
+; GCN-NEXT: v_bfi_b32 v6, s4, v23, v6
+; GCN-NEXT: v_bfi_b32 v7, s4, v22, v7
+; GCN-NEXT: v_bfi_b32 v8, s4, v21, v8
+; GCN-NEXT: v_bfi_b32 v9, s4, v20, v9
+; GCN-NEXT: v_bfi_b32 v10, s4, v19, v10
+; GCN-NEXT: v_bfi_b32 v11, s4, v18, v11
+; GCN-NEXT: v_bfi_b32 v12, s4, v17, v12
+; GCN-NEXT: v_bfi_b32 v13, s4, v16, v13
+; GCN-NEXT: v_bfi_b32 v14, s4, v15, v14
+; GCN-NEXT: v_bfi_b32 v15, s4, v30, v31
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_vselect_v32bf16:
@@ -46274,16 +46276,15 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x1a
; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v83, 16, v32 :: v_dual_bitop2_b32 v17, 1, v17 bitop3:0x40
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v30
-; GFX1250FAKE16-NEXT: v_and_b32_e32 v28, 1, v28
; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x17
-; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v30, v34, v35, s1 :: v_dual_bitop2_b32 v33, 1, v33 bitop3:0x40
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v30, v34, v35, s1 :: v_dual_bitop2_b32 v28, 1, v28 bitop3:0x40
+; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v35, 16, v35 :: v_dual_bitop2_b32 v33, 1, v33 bitop3:0x40
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28
; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v31
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v29
; GFX1250FAKE16-NEXT: scratch_load_b32 v29, off, s32 offset:16
-; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v35, 16, v35 :: v_dual_lshrrev_b32 v34, 16, v34
-; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc_lo
+; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v31, v32, v31 :: v_dual_lshrrev_b32 v34, 16, v34
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v33
; GFX1250FAKE16-NEXT: scratch_load_b32 v32, off, s32 offset:72
; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v28, v83, v28, s0
@@ -50804,11 +50805,12 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v31, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v129
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v33, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v14, v132, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v149, v2, v3, s0
; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v129, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
@@ -51125,7 +51127,6 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v31, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v128, v114, v113
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v54, v118, v117
; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v129
@@ -51142,7 +51143,9 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_bfe_u32 v101, v52, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v113, v53, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v117, v32, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v148, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v149, v2, v3, s0
; GFX11FAKE16-NEXT: v_add3_u32 v2, v4, v129, 0x7fff
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index b5844049fd287..174c1950aeb5b 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -8993,8 +8993,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
@@ -9124,8 +9124,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v5, v1, v0, 16
@@ -9421,8 +9421,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
@@ -9549,8 +9549,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v0, v5, v0, 16
@@ -10587,8 +10587,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add
; GFX10-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
@@ -10718,8 +10718,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v5, v1, v0, 16
@@ -11015,8 +11015,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset(ptr addrspace
; GFX10-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
@@ -11143,8 +11143,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset(ptr addrspace
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v0, v5, v0, 16
@@ -11444,8 +11444,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
@@ -11575,8 +11575,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v5, v1, v0, 16
@@ -11872,8 +11872,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_re
; GFX10-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
@@ -12000,8 +12000,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_re
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v0, v5, v0, 16
@@ -12290,8 +12290,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
@@ -12418,8 +12418,8 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v0, v5, v0, 16
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index 3d85bf7019426..c8f2e76954336 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -7506,8 +7506,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
@@ -7637,8 +7637,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v5, v1, v0, 16
@@ -8018,8 +8018,8 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
@@ -8146,8 +8146,8 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v0, v5, v0, 16
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 3f15d35320573..497fef759db78 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -7506,8 +7506,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
@@ -7637,8 +7637,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v5, v1, v0, 16
@@ -8018,8 +8018,8 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
@@ -8146,8 +8146,8 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v0, v5, v0, 16
diff --git a/llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll b/llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll
index ea93e3ac1e595..7545bf51ecd70 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll
@@ -12,8 +12,8 @@ define amdgpu_cs <2 x i32> @f() {
; CHECK-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; CHECK-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
index 150d8cfe22cfd..6e7b9304484a7 100644
--- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll
+++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
@@ -100,10 +100,10 @@ define i64 @sdiv64(i64 %a, i64 %b) {
; GFX9-NEXT: v_add_co_u32_e64 v6, s[4:5], 2, v2
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[4:5], 0, v3, s[4:5]
; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 1, v2
-; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v3, s[4:5]
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v8, v1, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v3, s[4:5]
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v10
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v13, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v11
@@ -236,19 +236,19 @@ define i64 @udiv64(i64 %a, i64 %b) {
; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v8, s[4:5]
; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], 2, v6
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
-; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v6
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v6
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v11, v9, s[4:5]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]
@@ -380,14 +380,14 @@ define i64 @srem64(i64 %a, i64 %b) {
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[6:7]
; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v3, v10
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v4, v9
; GFX9-NEXT: v_subb_co_u32_e64 v2, s[4:5], v2, v9, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v4, v9
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[6:7]
; GFX9-NEXT: v_sub_co_u32_e64 v7, s[4:5], v3, v10
-; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[4:5], 0, v2, s[4:5]
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v8, v1, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
+; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[4:5], 0, v2, s[4:5]
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v9
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v10
@@ -512,23 +512,23 @@ define i64 @urem64(i64 %a, i64 %b) {
; GFX9-NEXT: v_subb_co_u32_e64 v4, s[4:5], v6, v3, vcc
; GFX9-NEXT: v_sub_co_u32_e64 v6, s[4:5], v0, v2
; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[6:7], 0, v4, s[4:5]
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v2
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3
; GFX9-NEXT: v_subb_co_u32_e64 v4, s[4:5], v4, v3, s[4:5]
-; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]
-; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v6, v2
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]
+; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v6, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
+; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[4:5], 0, v4, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
@@ -786,13 +786,13 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[6:7]
; GFX9-NEXT: v_add_co_u32_e64 v5, s[6:7], 2, v2
; GFX9-NEXT: v_addc_co_u32_e64 v14, s[6:7], 0, v3, s[6:7]
-; GFX9-NEXT: v_add_co_u32_e64 v15, s[6:7], 1, v2
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v8, v1, vcc
-; GFX9-NEXT: v_addc_co_u32_e64 v16, s[6:7], 0, v3, s[6:7]
+; GFX9-NEXT: v_add_co_u32_e64 v15, s[6:7], 1, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v10
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v16, s[6:7], 0, v3, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v11
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v16, v14, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v10
@@ -946,13 +946,13 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) {
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v11, s[6:7]
; GFX9-NEXT: v_add_co_u32_e64 v11, s[6:7], 2, v6
; GFX9-NEXT: v_addc_co_u32_e64 v12, s[6:7], 0, v7, s[6:7]
-; GFX9-NEXT: v_add_co_u32_e64 v13, s[6:7], 1, v6
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
-; GFX9-NEXT: v_addc_co_u32_e64 v14, s[6:7], 0, v7, s[6:7]
+; GFX9-NEXT: v_add_co_u32_e64 v13, s[6:7], 1, v6
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v14, s[6:7], 0, v7, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v14, v12, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
@@ -1095,19 +1095,19 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) {
; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v3
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v8, s[4:5]
; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], 2, v6
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
-; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
-; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v6
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v6
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v0
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
+; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v11, v9, s[4:5]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index 0193feec27c86..962ec51b1ac47 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -455,8 +455,8 @@ define amdgpu_kernel void @vadd64ri(ptr addrspace(1) %out) {
; GFX1030W32-LABEL: vadd64ri:
; GFX1030W32: ; %bb.0: ; %entry
; GFX1030W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1030W32-NEXT: v_add_co_u32 v0, s2, 0x56789876, v0
; GFX1030W32-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030W32-NEXT: v_add_co_u32 v0, s2, 0x56789876, v0
; GFX1030W32-NEXT: v_add_co_ci_u32_e64 v1, null, 0x1234, 0, s2
; GFX1030W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030W32-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -465,8 +465,8 @@ define amdgpu_kernel void @vadd64ri(ptr addrspace(1) %out) {
; GFX1030W64-LABEL: vadd64ri:
; GFX1030W64: ; %bb.0: ; %entry
; GFX1030W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1030W64-NEXT: v_add_co_u32 v0, s[2:3], 0x56789876, v0
; GFX1030W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030W64-NEXT: v_add_co_u32 v0, s[2:3], 0x56789876, v0
; GFX1030W64-NEXT: v_add_co_ci_u32_e64 v1, null, 0x1234, 0, s[2:3]
; GFX1030W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030W64-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -1007,10 +1007,10 @@ define amdgpu_kernel void @vuaddo64(ptr addrspace(1) %out, ptr addrspace(1) %car
; VI-NEXT: v_mov_b32_e32 v1, s0
; VI-NEXT: v_mov_b32_e32 v6, s5
; VI-NEXT: v_add_u32_e32 v5, vcc, s4, v0
-; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: v_mov_b32_e32 v4, s3
+; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6]
; VI-NEXT: flat_store_byte v[3:4], v0
@@ -1595,8 +1595,8 @@ define amdgpu_kernel void @vsub64ri(ptr addrspace(1) %out) {
; GFX1030W32-LABEL: vsub64ri:
; GFX1030W32: ; %bb.0: ; %entry
; GFX1030W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1030W32-NEXT: v_sub_co_u32 v0, s2, 0x56789876, v0
; GFX1030W32-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030W32-NEXT: v_sub_co_u32 v0, s2, 0x56789876, v0
; GFX1030W32-NEXT: v_sub_co_ci_u32_e64 v1, null, 0x1234, 0, s2
; GFX1030W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030W32-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -1605,8 +1605,8 @@ define amdgpu_kernel void @vsub64ri(ptr addrspace(1) %out) {
; GFX1030W64-LABEL: vsub64ri:
; GFX1030W64: ; %bb.0: ; %entry
; GFX1030W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1030W64-NEXT: v_sub_co_u32 v0, s[2:3], 0x56789876, v0
; GFX1030W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030W64-NEXT: v_sub_co_u32 v0, s[2:3], 0x56789876, v0
; GFX1030W64-NEXT: v_sub_co_ci_u32_e64 v1, null, 0x1234, 0, s[2:3]
; GFX1030W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030W64-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -2148,10 +2148,10 @@ define amdgpu_kernel void @vusubo64(ptr addrspace(1) %out, ptr addrspace(1) %car
; VI-NEXT: v_mov_b32_e32 v1, s0
; VI-NEXT: v_mov_b32_e32 v6, s5
; VI-NEXT: v_sub_u32_e32 v5, vcc, s4, v0
-; VI-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v6, vcc
; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: v_mov_b32_e32 v4, s3
+; VI-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v6, vcc
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6]
; VI-NEXT: flat_store_byte v[3:4], v0
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index f0827bc60483e..290b2e1326c86 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -1750,8 +1750,8 @@ define amdgpu_kernel void @v_ctlz_i64_sel_ne_bitwidth(ptr addrspace(1) noalias %
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 64, v0
; GFX10-GISEL-NEXT: v_cmp_ne_u64_e32 vcc_lo, 64, v[0:1]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, -1, 0, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX10-GISEL-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 3aa89a7210ca0..f5c31c7b4288b 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -139,8 +139,8 @@ define <2 x float> @fmul_select_v2f32_test3(<2 x float> %x, <2 x i32> %bool.arg1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5
-; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -211,8 +211,8 @@ define <2 x float> @fmul_select_v2f32_test4(<2 x float> %x, <2 x i32> %bool.arg1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5
-; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -769,8 +769,8 @@ define <2 x double> @fmul_select_v2f64_test3(<2 x double> %x, <2 x i32> %bool.ar
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -780,8 +780,8 @@ define <2 x double> @fmul_select_v2f64_test3(<2 x double> %x, <2 x i32> %bool.ar
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -792,8 +792,8 @@ define <2 x double> @fmul_select_v2f64_test3(<2 x double> %x, <2 x i32> %bool.ar
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX10-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -803,9 +803,9 @@ define <2 x double> @fmul_select_v2f64_test3(<2 x double> %x, <2 x i32> %bool.ar
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX11-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
@@ -820,8 +820,8 @@ define <2 x double> @fmul_select_v2f64_test4(<2 x double> %x, <2 x i32> %bool.ar
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX7-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -831,8 +831,8 @@ define <2 x double> @fmul_select_v2f64_test4(<2 x double> %x, <2 x i32> %bool.ar
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -843,8 +843,8 @@ define <2 x double> @fmul_select_v2f64_test4(<2 x double> %x, <2 x i32> %bool.ar
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX10-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -854,9 +854,9 @@ define <2 x double> @fmul_select_v2f64_test4(<2 x double> %x, <2 x i32> %bool.ar
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
; GFX11-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
@@ -958,8 +958,8 @@ define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_mov_b32_e32 v5, 0xbff00000
-; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 2.0, vcc
; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -978,8 +978,8 @@ define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xbff00000
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 2.0, vcc
; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -987,8 +987,8 @@ define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX10-LABEL: fmul_select_f64_test7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -996,8 +996,8 @@ define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-LABEL: fmul_select_f64_test7:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
@@ -1053,8 +1053,8 @@ define <2 x double> @fmul_select_v2f64_test9(<2 x double> %x, <2 x i32> %bool.ar
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v4
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -1064,8 +1064,8 @@ define <2 x double> @fmul_select_v2f64_test9(<2 x double> %x, <2 x i32> %bool.ar
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1076,8 +1076,8 @@ define <2 x double> @fmul_select_v2f64_test9(<2 x double> %x, <2 x i32> %bool.ar
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX10-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4
; GFX10-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -1087,9 +1087,9 @@ define <2 x double> @fmul_select_v2f64_test9(<2 x double> %x, <2 x i32> %bool.ar
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4
; GFX11-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
@@ -1106,8 +1106,8 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX7-SDAG-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc
-; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-SDAG-NEXT: v_mov_b32_e32 v8, 0
+; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX7-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -1119,9 +1119,9 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX7-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX7-GISEL-NEXT: v_mov_b32_e32 v10, 0xbff00000
; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
+; GFX7-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
-; GFX7-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX7-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -1134,8 +1134,8 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX9-SDAG-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX9-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -1147,9 +1147,9 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX9-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0xbff00000
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX9-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -1161,8 +1161,8 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX10-SDAG-NEXT: v_mov_b32_e32 v8, 0x3fe00000
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, 0xbff00000, v8, vcc_lo
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
; GFX10-SDAG-NEXT: v_mov_b32_e32 v8, 0
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX10-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -1176,8 +1176,8 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX10-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v9, 0x3fe00000, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX10-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1186,12 +1186,12 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_mov_b32_e32 v8, 0x3fe00000
; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, 0xbff00000, v8 :: v_dual_mov_b32 v8, 0
; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1200,12 +1200,12 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_dual_mov_b32 v9, 0xbff00000 :: v_dual_mov_b32 v8, 0
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v9, 0x3fe00000, vcc_lo
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
@@ -1229,8 +1229,8 @@ define double @fmul_select_f64_test11(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -2.0, vcc
; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1249,8 +1249,8 @@ define double @fmul_select_f64_test11(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -2.0, vcc
; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1258,8 +1258,8 @@ define double @fmul_select_f64_test11(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX10-LABEL: fmul_select_f64_test11:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x80000000, -2.0, vcc_lo
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1267,8 +1267,8 @@ define double @fmul_select_f64_test11(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-LABEL: fmul_select_f64_test11:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x80000000, -2.0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
@@ -1284,8 +1284,8 @@ define double @fmul_select_f64_test12(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-NEXT: v_mov_b32_e32 v4, 0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX7-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -1294,8 +1294,8 @@ define double @fmul_select_f64_test12(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1303,8 +1303,8 @@ define double @fmul_select_f64_test12(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX10-LABEL: fmul_select_f64_test12:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x80000000, 0, vcc_lo
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1312,8 +1312,8 @@ define double @fmul_select_f64_test12(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-LABEL: fmul_select_f64_test12:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x80000000, 0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
@@ -1329,8 +1329,8 @@ define double @fmul_select_f64_test13(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v5, 0x40300000
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-NEXT: v_mov_b32_e32 v4, 0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX7-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -1339,8 +1339,8 @@ define double @fmul_select_f64_test13(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v5, 0x40300000
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1348,8 +1348,8 @@ define double @fmul_select_f64_test13(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX10-LABEL: fmul_select_f64_test13:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x40300000, 0, vcc_lo
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1357,8 +1357,8 @@ define double @fmul_select_f64_test13(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-LABEL: fmul_select_f64_test13:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x40300000, 0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
@@ -1580,8 +1580,8 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1608,8 +1608,8 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
@@ -1619,8 +1619,8 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
@@ -1668,8 +1668,8 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1678,8 +1678,8 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1688,10 +1688,11 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1699,10 +1700,11 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1710,8 +1712,8 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
@@ -1721,8 +1723,8 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
@@ -1819,15 +1821,15 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX10-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1862,15 +1864,15 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1878,19 +1880,19 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
@@ -1985,15 +1987,15 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX10-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2028,15 +2030,15 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2044,19 +2046,19 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
@@ -2490,8 +2492,8 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 5, v1
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1
@@ -2519,10 +2521,9 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 5, v1
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v2, 0x7fff :: v_dual_add_nc_u32 v1, 5, v1
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v0.l, v1.l
@@ -2532,10 +2533,9 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 5, v1
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v2, 0x7fff :: v_dual_add_nc_u32 v1, 5, v1
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, -v0, v1
@@ -2580,8 +2580,8 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
+; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -2598,10 +2598,11 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2609,10 +2610,11 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2673,8 +2675,8 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
+; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -2691,10 +2693,11 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2702,10 +2705,11 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3845,8 +3849,8 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffff8000, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-NEXT: v_bfe_u32 v1, v0, 16, 1
@@ -3880,9 +3884,9 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffff8000, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -3918,9 +3922,9 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffff8000, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 40b1b1f83b642..a93a456dd25e1 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -60,21 +60,20 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 64, v6
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[6:7], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v4, v7, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v19, v17
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v20, v18
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v19, v17
; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
@@ -84,6 +83,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GFX9-NEXT: s_xor_b64 s[6:7], s[4:5], -1
+; GFX9-NEXT: v_mov_b32_e32 v20, v18
; GFX9-NEXT: v_cndmask_b32_e64 v13, v11, 0, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v12, v10, 0, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, 0, s[4:5]
@@ -1235,14 +1235,13 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_mov_b32_e32 v6, 0x7f
; GFX9-G-NEXT: v_mov_b32_e32 v7, 0
; GFX9-G-NEXT: v_subb_co_u32_e64 v2, s[4:5], 0, 0, s[4:5]
-; GFX9-G-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[6:7]
; GFX9-G-NEXT: v_subb_co_u32_e64 v3, s[4:5], 0, 0, s[4:5]
+; GFX9-G-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[6:7]
; GFX9-G-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-G-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[2:3]
-; GFX9-G-NEXT: s_mov_b64 s[6:7], exec
; GFX9-G-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-G-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
+; GFX9-G-NEXT: s_mov_b64 s[6:7], exec
; GFX9-G-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX9-G-NEXT: v_and_b32_e32 v6, 1, v6
; GFX9-G-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
@@ -1252,6 +1251,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[6:7]
; GFX9-G-NEXT: s_or_b64 s[10:11], s[10:11], vcc
; GFX9-G-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
; GFX9-G-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[10:11]
; GFX9-G-NEXT: v_cndmask_b32_e64 v7, v9, 0, s[10:11]
; GFX9-G-NEXT: v_cndmask_b32_e64 v12, v10, 0, s[10:11]
@@ -1307,8 +1307,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
; GFX9-G-NEXT: v_add_co_u32_e32 v24, vcc, -1, v18
; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
-; GFX9-G-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v20
; GFX9-G-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v19, vcc
+; GFX9-G-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v20
; GFX9-G-NEXT: v_cndmask_b32_e64 v10, v0, v8, s[4:5]
; GFX9-G-NEXT: v_cndmask_b32_e64 v11, v1, v9, s[4:5]
; GFX9-G-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v4, vcc
@@ -2276,20 +2276,20 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, 64, v11
; GFX9-NEXT: v_addc_co_u32_e64 v12, s[6:7], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v13, v12, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v12, vcc, v8, v9
; GFX9-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v13, vcc
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, 0, v8, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, 0, v8, vcc
+; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[12:13]
-; GFX9-NEXT: v_or_b32_e32 v11, v13, v15
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; GFX9-NEXT: v_or_b32_e32 v11, v13, v15
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
@@ -3313,14 +3313,13 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_mov_b32_e32 v8, 0x7f
; GFX9-G-NEXT: v_mov_b32_e32 v9, 0
; GFX9-G-NEXT: v_subb_co_u32_e64 v14, s[4:5], 0, 0, s[4:5]
-; GFX9-G-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[8:9]
; GFX9-G-NEXT: v_subb_co_u32_e64 v15, s[4:5], 0, 0, s[4:5]
+; GFX9-G-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[8:9]
; GFX9-G-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-G-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[14:15]
-; GFX9-G-NEXT: s_mov_b64 s[6:7], exec
; GFX9-G-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-G-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
-; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
+; GFX9-G-NEXT: s_mov_b64 s[6:7], exec
; GFX9-G-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX9-G-NEXT: v_and_b32_e32 v8, 1, v8
; GFX9-G-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
@@ -3330,6 +3329,7 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[8:9]
; GFX9-G-NEXT: s_or_b64 s[10:11], s[10:11], vcc
; GFX9-G-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
; GFX9-G-NEXT: v_cndmask_b32_e64 v10, v0, 0, s[10:11]
; GFX9-G-NEXT: v_cndmask_b32_e64 v11, v1, 0, s[10:11]
; GFX9-G-NEXT: v_cndmask_b32_e64 v8, v2, 0, s[10:11]
@@ -3387,9 +3387,9 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_add_co_u32_e32 v22, vcc, -1, v4
; GFX9-G-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v5, vcc
; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GFX9-G-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
; GFX9-G-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v6, vcc
; GFX9-G-NEXT: v_mov_b32_e32 v13, s11
+; GFX9-G-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
; GFX9-G-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5]
; GFX9-G-NEXT: v_cndmask_b32_e64 v3, v3, v1, s[4:5]
; GFX9-G-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v7, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 3f6750546618f..213b69d0d4c6f 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -3538,8 +3538,8 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX8-NEXT: v_cvt_f64_f32_e32 v[5:6], v7
; GFX8-NEXT: v_and_b32_e32 v9, 1, v7
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v9
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[5:6]|
; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[5:6]
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[5:6]|
; GFX8-NEXT: v_cndmask_b32_e64 v5, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v5, s[6:7], v7, v5
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -3549,13 +3549,13 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX8-NEXT: v_cvt_f64_f32_e32 v[5:6], v8
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[5:6]|
; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[5:6]
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v7
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX8-NEXT: v_and_b32_e32 v1, 1, v8
; GFX8-NEXT: v_cndmask_b32_e64 v0, v9, v7, s[4:5]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[5:6]|
; GFX8-NEXT: v_cndmask_b32_e64 v1, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v1, s[6:7], v8, v1
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -3582,18 +3582,18 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX9-NEXT: v_cvt_f64_f32_e32 v[7:8], v10
; GFX9-NEXT: v_and_b32_e32 v11, 1, v9
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[5:6]|
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[5:6]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[5:6]|
; GFX9-NEXT: v_cndmask_b32_e64 v5, -1, 1, s[6:7]
; GFX9-NEXT: v_add_u32_e32 v5, v9, v5
-; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[7:8]|
+; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[7:8]
; GFX9-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v6, v6, v5, s8
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v5
+; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX9-NEXT: v_and_b32_e32 v1, 1, v10
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, v5, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
@@ -3622,14 +3622,14 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX10-NEXT: v_and_b32_e32 v11, 1, v9
; GFX10-NEXT: v_and_b32_e32 v12, 1, v10
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v12
-; GFX10-NEXT: v_cmp_gt_f64_e64 s5, |v[0:1]|, |v[5:6]|
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[5:6]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s4, v[2:3], v[7:8]
+; GFX10-NEXT: v_cmp_gt_f64_e64 s5, |v[0:1]|, |v[5:6]|
; GFX10-NEXT: v_cndmask_b32_e64 v5, -1, 1, s5
; GFX10-NEXT: v_cmp_gt_f64_e64 s5, |v[2:3]|, |v[7:8]|
-; GFX10-NEXT: v_add_nc_u32_e32 v5, v9, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, -1, 1, s5
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v11
+; GFX10-NEXT: v_add_nc_u32_e32 v5, v9, v5
; GFX10-NEXT: v_add_nc_u32_e32 v6, v10, v6
; GFX10-NEXT: s_or_b32 vcc_lo, vcc_lo, s5
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
@@ -3657,19 +3657,19 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[5:6], v9
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[7:8], v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[5:6]|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[5:6]
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[2:3], v[7:8]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[5:6]|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v5, -1, 1, s1
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[2:3]|, |v[7:8]|
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v7, -1, 1, s1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v5, v9, v5
; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 1, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v7, -1, 1, s1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v6, v10, v7
; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 1, v9
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v11
@@ -3703,16 +3703,16 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[5:6], v9
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[7:8], v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[5:6]|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[5:6]
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s0, v[2:3], v[7:8]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[5:6]|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v5, -1, 1, s1
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s1, |v[2:3]|, |v[7:8]|
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v5, v9, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v6, -1, 1, s1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v5, v9, v5
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v6, v10, v6
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 1, v9
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
@@ -5331,8 +5331,8 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX8-NEXT: v_and_b32_e32 v11, 1, v10
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
; GFX8-NEXT: v_cvt_f32_f64_e32 v11, v[0:1]
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[8:9]|
; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[8:9]|
; GFX8-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v8, s[6:7], v10, v8
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -5358,13 +5358,13 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX8-NEXT: v_add_u32_e32 v11, vcc, v4, v8
; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v9
; GFX8-NEXT: v_add_u32_e32 v11, vcc, s8, v11
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
-; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v8
+; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX8-NEXT: v_and_b32_e32 v1, 1, v9
; GFX8-NEXT: v_cndmask_b32_e64 v0, v11, v8, s[4:5]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
; GFX8-NEXT: v_cndmask_b32_e64 v1, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v1, s[6:7], v9, v1
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -5391,20 +5391,20 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX9-NEXT: v_cvt_f64_f32_e32 v[8:9], v10
; GFX9-NEXT: v_and_b32_e32 v12, 1, v10
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v12
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[8:9]|
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[8:9]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[8:9]|
; GFX9-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[6:7]
; GFX9-NEXT: v_add_u32_e32 v8, v10, v8
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v10, v8, v10, vcc
; GFX9-NEXT: v_cvt_f64_f32_e32 v[8:9], v11
-; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[4:5]
; GFX9-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX9-NEXT: v_add3_u32 v12, v12, v10, s8
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[8:9]|
+; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v10
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[8:9]|
; GFX9-NEXT: v_cvt_f32_f64_e32 v8, v[2:3]
-; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v10
+; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[4:5]
; GFX9-NEXT: v_and_b32_e32 v4, 1, v11
; GFX9-NEXT: v_cndmask_b32_e64 v10, v12, v10, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v4
@@ -5413,15 +5413,15 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v9, v4, v11, vcc
; GFX9-NEXT: v_cvt_f64_f32_e32 v[4:5], v8
-; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX9-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v11, v11, v9, s8
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
-; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v9
+; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX9-NEXT: v_and_b32_e32 v1, 1, v8
; GFX9-NEXT: v_cndmask_b32_e64 v0, v11, v9, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
; GFX9-NEXT: v_cndmask_b32_e64 v1, -1, 1, s[6:7]
; GFX9-NEXT: v_add_u32_e32 v1, v8, v1
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -5453,32 +5453,32 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX10-NEXT: v_and_b32_e32 v19, 1, v16
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v17
; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v19
-; GFX10-NEXT: v_cmp_gt_f64_e64 s7, |v[4:5]|, |v[8:9]|
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[4:5], v[8:9]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s4, v[0:1], v[10:11]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s5, v[2:3], v[12:13]
+; GFX10-NEXT: v_cmp_gt_f64_e64 s7, |v[4:5]|, |v[8:9]|
; GFX10-NEXT: v_cndmask_b32_e64 v8, -1, 1, s7
; GFX10-NEXT: v_cmp_gt_f64_e64 s7, |v[0:1]|, |v[10:11]|
-; GFX10-NEXT: s_or_b32 vcc_lo, vcc_lo, s6
-; GFX10-NEXT: v_add_nc_u32_e32 v8, v14, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
-; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX10-NEXT: v_cndmask_b32_e64 v9, -1, 1, s7
; GFX10-NEXT: v_cmp_gt_f64_e64 s7, |v[2:3]|, |v[12:13]|
-; GFX10-NEXT: v_bfe_u32 v12, v8, 16, 1
-; GFX10-NEXT: v_add_nc_u32_e32 v9, v15, v9
-; GFX10-NEXT: v_add3_u32 v8, v12, v8, 0x7fff
; GFX10-NEXT: v_cndmask_b32_e64 v10, -1, 1, s7
; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v18
+; GFX10-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v9, v15, v9
; GFX10-NEXT: v_add_nc_u32_e32 v10, v16, v10
+; GFX10-NEXT: s_or_b32 vcc_lo, vcc_lo, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
; GFX10-NEXT: s_or_b32 vcc_lo, s4, s7
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo
; GFX10-NEXT: s_or_b32 vcc_lo, s5, s8
+; GFX10-NEXT: v_bfe_u32 v12, v8, 16, 1
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
; GFX10-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v9
+; GFX10-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX10-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX10-NEXT: v_add3_u32 v8, v12, v8, 0x7fff
; GFX10-NEXT: v_add3_u32 v9, v11, v9, 0x7fff
; GFX10-NEXT: v_or_b32_e32 v11, 0x400000, v10
; GFX10-NEXT: v_add3_u32 v10, v13, v10, 0x7fff
@@ -5504,56 +5504,56 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[10:11], v15
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[12:13], v16
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[8:9]|
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[4:5], v[10:11]
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s1, v[2:3], v[12:13]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[8:9]|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v8, -1, 1, s3
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[4:5]|, |v[10:11]|
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v9, -1, 1, s3
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[2:3]|, |v[12:13]|
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s3
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, v16, v10
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 1, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v19
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_and_b32 v17, 1, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s0, s2
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_and_b32 v18, 1, v16
; GFX11TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v8, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s1, s4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v9, v12, v9, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v14, v10, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v15, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[4:5]
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v7
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v2, v6
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5569,21 +5569,22 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[12:13], v16
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 1, v15
-; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[4:5]|, |v[8:9]|
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[4:5], v[8:9]
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s0, v[0:1], v[10:11]
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s1, v[2:3], v[12:13]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[4:5]|, |v[8:9]|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v8, -1, 1, s3
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[10:11]|
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v9, -1, 1, s3
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[2:3]|, |v[12:13]|
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s3
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v10, v16, v10
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 1, v14
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
@@ -6505,8 +6506,8 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX8-NEXT: v_and_b32_e32 v13, 1, v12
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v13
; GFX8-NEXT: v_cvt_f32_f64_e32 v13, v[6:7]
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[10:11]|
; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[10:11]
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[10:11]|
; GFX8-NEXT: v_cndmask_b32_e64 v10, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v10, s[6:7], v12, v10
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -6515,14 +6516,13 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX8-NEXT: v_add_u32_e32 v14, vcc, v10, v12
; GFX8-NEXT: v_cvt_f64_f32_e32 v[10:11], v13
; GFX8-NEXT: v_add_u32_e32 v14, vcc, s8, v14
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[4:5]
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[10:11]|
-; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[6:7], v[10:11]
; GFX8-NEXT: v_or_b32_e32 v12, 0x400000, v12
+; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[6:7], v[10:11]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[4:5]
; GFX8-NEXT: v_and_b32_e32 v4, 1, v13
-; GFX8-NEXT: v_cvt_f32_f64_e32 v11, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v12, v14, v12, s[4:5]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v4
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[10:11]|
; GFX8-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v4, s[6:7], v13, v4
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -6530,31 +6530,32 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX8-NEXT: v_bfe_u32 v4, v10, 16, 1
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v10
; GFX8-NEXT: v_add_u32_e32 v13, vcc, s8, v4
+; GFX8-NEXT: v_cvt_f32_f64_e32 v11, v[0:1]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[6:7]
-; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v11
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v10
+; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v11
; GFX8-NEXT: v_and_b32_e32 v7, 1, v11
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; GFX8-NEXT: v_cndmask_b32_e32 v6, v13, v10, vcc
; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cvt_f32_f64_e32 v10, v[2:3]
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
+; GFX8-NEXT: v_cvt_f32_f64_e32 v10, v[2:3]
; GFX8-NEXT: v_add_u32_e64 v4, s[6:7], v11, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v11, vcc
; GFX8-NEXT: v_bfe_u32 v4, v7, 16, 1
; GFX8-NEXT: v_add_u32_e32 v11, vcc, v4, v7
; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v10
; GFX8-NEXT: v_add_u32_e32 v11, vcc, s8, v11
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
-; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v7
+; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX8-NEXT: v_and_b32_e32 v1, 1, v10
; GFX8-NEXT: v_cndmask_b32_e64 v0, v11, v7, s[4:5]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
; GFX8-NEXT: v_cndmask_b32_e64 v1, -1, 1, s[6:7]
; GFX8-NEXT: v_add_u32_e64 v1, s[6:7], v10, v1
; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -6582,20 +6583,20 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX9-NEXT: v_and_b32_e32 v13, 1, v12
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v13
; GFX9-NEXT: v_cvt_f32_f64_e32 v13, v[6:7]
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[10:11]|
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[10:11]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[10:11]|
; GFX9-NEXT: v_cndmask_b32_e64 v10, -1, 1, s[6:7]
; GFX9-NEXT: v_add_u32_e32 v10, v12, v10
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc
; GFX9-NEXT: v_cvt_f64_f32_e32 v[10:11], v13
-; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[4:5]
; GFX9-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX9-NEXT: v_add3_u32 v14, v14, v12, s8
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[10:11]|
+; GFX9-NEXT: v_or_b32_e32 v12, 0x400000, v12
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[6:7], v[10:11]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[10:11]|
; GFX9-NEXT: v_cvt_f32_f64_e32 v10, v[0:1]
-; GFX9-NEXT: v_or_b32_e32 v12, 0x400000, v12
+; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[4:5]
; GFX9-NEXT: v_and_b32_e32 v4, 1, v13
; GFX9-NEXT: v_cndmask_b32_e64 v12, v14, v12, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v4
@@ -6604,30 +6605,30 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v11, v4, v13, vcc
; GFX9-NEXT: v_cvt_f64_f32_e32 v[4:5], v10
-; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[6:7]
; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX9-NEXT: v_add3_u32 v13, v13, v11, s8
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
-; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v11
+; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[6:7]
; GFX9-NEXT: v_and_b32_e32 v7, 1, v10
; GFX9-NEXT: v_cndmask_b32_e64 v6, v13, v11, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
; GFX9-NEXT: v_cvt_f32_f64_e32 v7, v[2:3]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; GFX9-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; GFX9-NEXT: v_add_u32_e32 v4, v10, v4
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v10, v4, v10, vcc
; GFX9-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
-; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX9-NEXT: v_bfe_u32 v11, v10, 16, 1
; GFX9-NEXT: v_add3_u32 v11, v11, v10, s8
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
-; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v10
+; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[0:1]
; GFX9-NEXT: v_and_b32_e32 v1, 1, v7
; GFX9-NEXT: v_cndmask_b32_e64 v0, v11, v10, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[4:5]|
; GFX9-NEXT: v_cndmask_b32_e64 v1, -1, 1, s[6:7]
; GFX9-NEXT: v_add_u32_e32 v1, v7, v1
; GFX9-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -6663,44 +6664,44 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v22
; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v23
; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v24
-; GFX10-NEXT: v_cmp_gt_f64_e64 s10, |v[4:5]|, |v[10:11]|
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[4:5], v[10:11]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s4, v[6:7], v[12:13]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s5, v[0:1], v[14:15]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s7, v[2:3], v[16:17]
+; GFX10-NEXT: v_cmp_gt_f64_e64 s10, |v[4:5]|, |v[10:11]|
; GFX10-NEXT: v_cndmask_b32_e64 v10, -1, 1, s10
; GFX10-NEXT: v_cmp_gt_f64_e64 s10, |v[6:7]|, |v[12:13]|
-; GFX10-NEXT: s_or_b32 vcc_lo, vcc_lo, s6
-; GFX10-NEXT: v_add_nc_u32_e32 v10, v18, v10
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v18, vcc_lo
-; GFX10-NEXT: s_or_b32 vcc_lo, s4, s8
; GFX10-NEXT: v_cndmask_b32_e64 v11, -1, 1, s10
; GFX10-NEXT: v_cmp_gt_f64_e64 s10, |v[0:1]|, |v[14:15]|
-; GFX10-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v10
-; GFX10-NEXT: v_add_nc_u32_e32 v11, v19, v11
-; GFX10-NEXT: v_add3_u32 v10, v14, v10, 0x7fff
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc_lo
-; GFX10-NEXT: s_or_b32 vcc_lo, s5, s9
; GFX10-NEXT: v_cndmask_b32_e64 v12, -1, 1, s10
+; GFX10-NEXT: v_add_nc_u32_e32 v10, v18, v10
; GFX10-NEXT: v_cmp_gt_f64_e64 s10, |v[2:3]|, |v[16:17]|
-; GFX10-NEXT: v_bfe_u32 v16, v11, 16, 1
-; GFX10-NEXT: v_or_b32_e32 v17, 0x400000, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v12, v20, v12
-; GFX10-NEXT: v_add3_u32 v11, v16, v11, 0x7fff
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v20, vcc_lo
-; GFX10-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v12
-; GFX10-NEXT: v_add3_u32 v12, v18, v12, 0x7fff
; GFX10-NEXT: v_cndmask_b32_e64 v13, -1, 1, s10
+; GFX10-NEXT: v_add_nc_u32_e32 v11, v19, v11
; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v25
+; GFX10-NEXT: v_add_nc_u32_e32 v12, v20, v12
; GFX10-NEXT: v_add_nc_u32_e32 v13, v21, v13
+; GFX10-NEXT: s_or_b32 vcc_lo, vcc_lo, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v18, vcc_lo
+; GFX10-NEXT: s_or_b32 vcc_lo, s4, s8
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc_lo
+; GFX10-NEXT: s_or_b32 vcc_lo, s5, s9
+; GFX10-NEXT: v_bfe_u32 v14, v10, 16, 1
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v20, vcc_lo
; GFX10-NEXT: s_or_b32 vcc_lo, s7, s10
+; GFX10-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v21, vcc_lo
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[4:5]
+; GFX10-NEXT: v_add3_u32 v10, v14, v10, 0x7fff
+; GFX10-NEXT: v_bfe_u32 v18, v12, 16, 1
+; GFX10-NEXT: v_or_b32_e32 v19, 0x400000, v12
; GFX10-NEXT: v_bfe_u32 v20, v13, 16, 1
; GFX10-NEXT: v_or_b32_e32 v21, 0x400000, v13
+; GFX10-NEXT: v_bfe_u32 v16, v11, 16, 1
+; GFX10-NEXT: v_add3_u32 v12, v18, v12, 0x7fff
+; GFX10-NEXT: v_or_b32_e32 v17, 0x400000, v11
; GFX10-NEXT: v_add3_u32 v13, v20, v13, 0x7fff
+; GFX10-NEXT: v_add3_u32 v11, v16, v11, 0x7fff
; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v15, vcc_lo
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v12, v19, vcc_lo
@@ -6727,70 +6728,71 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[14:15], v20
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[16:17], v21
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s6, |v[6:7]|, |v[10:11]|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[6:7], v[10:11]
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[4:5], v[12:13]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s1, v[2:3], v[14:15]
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s2, v[0:1], v[16:17]
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s6, |v[6:7]|, |v[10:11]|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s6
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s6, |v[4:5]|, |v[12:13]|
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, v18, v10
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v11, -1, 1, s6
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s6, |v[2:3]|, |v[14:15]|
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v12, -1, 1, s6
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s6, |v[0:1]|, |v[16:17]|
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v13, -1, 1, s6
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, v19, v11
; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 1, v18
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, v18, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v13, v21, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 1, v20
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v22
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v24
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v10, v10, v18 :: v_dual_and_b32 v23, 1, v19
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v23
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s0, s4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v14, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v12, -1, 1, s6
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s6, |v[0:1]|, |v[16:17]|
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v11, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, v20, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v16, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v13, -1, 1, s6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v13, v21, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 1, v20
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v24
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v11, v11, v19 :: v_dual_add_nc_u32 v12, v20, v12
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s1, s5
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v12, v12, v20 :: v_dual_and_b32 v25, 1, v21
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v12, v12, v20 :: v_dual_and_b32 v25, 1, v21
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v11, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v25
; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v11, v16, v11, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s2, s6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v18, v12, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v21, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[4:5]
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v18, v12, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v13, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v11, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v21, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[6:7]
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v9
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v20, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v2, v8
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6807,21 +6809,26 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[14:15], v20
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[16:17], v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s6, |v[4:5]|, |v[10:11]|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[4:5], v[10:11]
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s0, v[6:7], v[12:13]
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s1, v[0:1], v[14:15]
-; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s2, v[2:3], v[16:17]
+; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s6, |v[4:5]|, |v[10:11]|
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s6
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s6, |v[6:7]|, |v[12:13]|
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v10, v18, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v11, -1, 1, s6
+; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s2, v[2:3], v[16:17]
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s6, |v[0:1]|, |v[14:15]|
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v10, v18, v10
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v12, -1, 1, s6
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v11, v19, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 1, v18
+; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s6, |v[2:3]|, |v[16:17]|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v13, -1, 1, s6
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v12, v20, v12
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v22
; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v18 :: v_dual_and_b32 v23, 1, v19
@@ -6830,24 +6837,18 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX11FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, s0, s4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add3_u32 v10, v14, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v12, -1, 1, s6
-; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s6, |v[2:3]|, |v[16:17]|
-; GFX11FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v11
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v12, v20, v12
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v16, v11, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v13, -1, 1, s6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v13, v21, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v24, 1, v20
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v11, v11, v19 :: v_dual_and_b32 v24, 1, v20
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v24
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v11
; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, s1, s5
; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v20 :: v_dual_and_b32 v25, 1, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_add3_u32 v11, v16, v11, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v25
; GFX11FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v12
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 0ae807783a151..cef47f32b50cc 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -852,8 +852,8 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v1, v1, 20, 11
@@ -898,8 +898,8 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; VI-NEXT: v_or_b32_e32 v0, v3, v0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; VI-NEXT: v_bfe_u32 v1, v1, 20, 11
@@ -989,12 +989,12 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v1, 20, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0xfffffc10, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v3, v4, 0, 13
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1003,10 +1003,10 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v3, v5
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v1, 12, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v1, 12, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v5, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1038,12 +1038,12 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v1, 20, 11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0xfffffc10, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
; GFX11-FAKE16-NEXT: v_med3_i32 v3, v4, 0, 13
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1052,10 +1052,10 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v3, v5
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 12, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 12, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2943,10 +2943,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v7, 0x1ff, v3
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v3
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; SI-NEXT: v_or_b32_e32 v2, v7, v2
; SI-NEXT: v_and_b32_e32 v6, 0xffe, v6
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v3, v3, 20, 11
; SI-NEXT: s_movk_i32 s4, 0x3f1
@@ -2983,10 +2983,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; SI-NEXT: v_and_b32_e32 v6, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v6, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, v6, v0
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v1, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
@@ -3032,10 +3032,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v6, 0x1ff, v3
-; VI-NEXT: v_or_b32_e32 v2, v6, v2
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v3
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; VI-NEXT: v_or_b32_e32 v2, v6, v2
; VI-NEXT: v_and_b32_e32 v5, 0xffe, v5
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v3, v3, 20, 11
; VI-NEXT: s_movk_i32 s4, 0x3f1
@@ -3072,10 +3072,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; VI-NEXT: v_and_b32_e32 v5, 0x1ff, v1
-; VI-NEXT: v_or_b32_e32 v0, v5, v0
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-NEXT: v_or_b32_e32 v0, v5, v0
; VI-NEXT: v_and_b32_e32 v3, 0xffe, v3
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v1, v1, 20, 11
; VI-NEXT: v_or_b32_e32 v0, v3, v0
@@ -3205,16 +3205,14 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 20, 11
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 20, 11
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v5, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v1
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v6
+; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v5, v2
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v8, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v8, v9, 0, 13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x1000, v2
@@ -3228,16 +3226,16 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v5, v12
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v6, 12, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v6, 12, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0xfffffc10, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v12, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v7, 12, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v7
@@ -3253,35 +3251,32 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v12
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, 0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v8, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v12
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, 0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, 0x7c00, v10 :: v_dual_add_nc_u32 v3, v8, v9
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v10 :: v_dual_add_nc_u32 v5, v5, v11
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x8000, v12, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v12, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3294,66 +3289,63 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v1, 20, 11
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 20, 11
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v3
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, 0x7e00
-; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v5, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v3
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v6
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v5, v0
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v7
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, 0x7e00
; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v8, v2
; GFX11-FAKE16-NEXT: v_med3_i32 v8, v9, 0, 13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x1000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_med3_i32 v5, v5, 0, 13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x1000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, v8, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, v5, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, v8, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v5, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v6, 12, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v6, 12, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0xfffffc10, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v12, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v7, 12, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 7, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 7, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 7, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v11
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v13, vcc_lo
@@ -4546,10 +4538,10 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v9, 0x1ff, v3
-; SI-NEXT: v_or_b32_e32 v2, v9, v2
; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v3
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; SI-NEXT: v_or_b32_e32 v2, v9, v2
; SI-NEXT: v_and_b32_e32 v8, 0xffe, v8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v3, v3, 20, 11
; SI-NEXT: s_movk_i32 s4, 0x3f1
@@ -4586,10 +4578,10 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; SI-NEXT: v_and_b32_e32 v8, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v8, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, v8, v0
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v1, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
@@ -4621,10 +4613,10 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v5
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffe, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v4, v5, 20, 11
; SI-NEXT: v_or_b32_e32 v1, v1, v3
@@ -4673,10 +4665,10 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v9, 0x1ff, v5
-; VI-NEXT: v_or_b32_e32 v4, v9, v4
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; VI-NEXT: v_or_b32_e32 v4, v9, v4
; VI-NEXT: v_and_b32_e32 v8, 0xffe, v8
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v5, v5, 20, 11
; VI-NEXT: s_movk_i32 s4, 0x3f1
@@ -4713,10 +4705,10 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v5
; VI-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; VI-NEXT: v_and_b32_e32 v8, 0x1ff, v1
-; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: v_and_b32_e32 v5, 0xffe, v5
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v1, v1, 20, 11
; VI-NEXT: v_or_b32_e32 v0, v5, v0
@@ -4748,10 +4740,10 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; VI-NEXT: v_and_b32_e32 v5, 0x1ff, v3
-; VI-NEXT: v_or_b32_e32 v2, v5, v2
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; VI-NEXT: v_or_b32_e32 v2, v5, v2
; VI-NEXT: v_and_b32_e32 v1, 0xffe, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v3, v3, 20, 11
; VI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -4915,94 +4907,92 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v3, 20, 11
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v5, 20, 11
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v1, 20, 11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v11, 0x3f1, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v8, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v5, 20, 11
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v8, v4
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v8, 0x3f1, v10
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_med3_i32 v11, v11, 0, 13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v9, v2
-; GFX11-TRUE16-NEXT: v_med3_i32 v8, v8, 0, 13
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v11, 0x3f1, v5
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x1000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_med3_i32 v8, v8, 0, 13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x1000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, v11, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v1, 20, 11
+; GFX11-TRUE16-NEXT: v_med3_i32 v11, v11, 0, 13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, v8, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v13, v0
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v13, 0x3f1, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, v8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, v11, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, v8, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0xfffffc10, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v11, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x1000, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v13, v13, 0, 13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, v8, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v11, v16
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, v13, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v10, 12, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, v13, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, v13, v17
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v10, 12, v2
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, v13, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0xfffffc10, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v16, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v13, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v5, 12, v4
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, 0x7e00
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 7, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v5
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, 0x7e00
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 7, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 12, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 12, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v12, v11 :: v_dual_and_b32 v12, 7, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 2, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 7, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v12, v16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, 0x7c00, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, 0x7c00, v17 :: v_dual_add_nc_u32 v9, v9, v12
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.h
@@ -5034,102 +5024,97 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0x1ff, v5, v4
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 20, 11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v2
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 20, 11
-; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 8, v3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 20, 11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v8
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: v_med3_i32 v9, v9, 0, 13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0xffe, v5, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 20, 11
+; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0xffe, v5, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT: v_med3_i32 v9, v9, 0, 13
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x1000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 8, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 20, 11
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v5, v0
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, v9, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x1000, v0
-; GFX11-FAKE16-NEXT: v_med3_i32 v5, v5, 0, 13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v12, v2
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v12, 0x3f1, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x1000, v0
+; GFX11-FAKE16-NEXT: v_med3_i32 v5, v5, 0, 13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, v9, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0xfffffc10, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, v5, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x1000, v2
; GFX11-FAKE16-NEXT: v_med3_i32 v12, v12, 0, 13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0xfffffc10, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, v5, v14
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v9, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v5, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, v12, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, v12, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, v12, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v5, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v15, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, v12, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0xfffffc10, v8
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v12, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v8, 12, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v10, 12, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 12, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v10, 12, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 12, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 7, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 2, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, 0x7e00 :: v_dual_add_nc_u32 v9, v9, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 7, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 7, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v17
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v12 :: v_dual_add_nc_u32 v11, v11, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, 0x7c00, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
@@ -5654,10 +5639,10 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v13, 0x1ff, v3
-; SI-NEXT: v_or_b32_e32 v2, v13, v2
; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v3
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; SI-NEXT: v_or_b32_e32 v2, v13, v2
; SI-NEXT: v_and_b32_e32 v12, 0xffe, v12
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v3, v3, 20, 11
; SI-NEXT: s_movk_i32 s4, 0x3f1
@@ -5694,10 +5679,10 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc
; SI-NEXT: v_and_b32_e32 v12, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v12, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, v12, v0
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v1, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
@@ -5729,10 +5714,10 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v7
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v7
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v6
; SI-NEXT: v_and_b32_e32 v1, 0xffe, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v6, v7, 20, 11
; SI-NEXT: v_or_b32_e32 v1, v1, v3
@@ -5763,11 +5748,11 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; SI-NEXT: v_cndmask_b32_e32 v1, v13, v14, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v6
; SI-NEXT: v_and_b32_e32 v6, 0x1ff, v5
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v5
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v5, v5, 20, 11
; SI-NEXT: v_or_b32_e32 v3, v3, v4
@@ -5822,10 +5807,10 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v11, 0x1ff, v5
-; VI-NEXT: v_or_b32_e32 v4, v11, v4
; VI-NEXT: v_lshrrev_b32_e32 v10, 8, v5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; VI-NEXT: v_or_b32_e32 v4, v11, v4
; VI-NEXT: v_and_b32_e32 v10, 0xffe, v10
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v5, v5, 20, 11
; VI-NEXT: s_movk_i32 s4, 0x3f1
@@ -5862,10 +5847,10 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v5
; VI-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
; VI-NEXT: v_and_b32_e32 v10, 0x1ff, v7
-; VI-NEXT: v_or_b32_e32 v6, v10, v6
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v7
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; VI-NEXT: v_or_b32_e32 v6, v10, v6
; VI-NEXT: v_and_b32_e32 v5, 0xffe, v5
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v7, v7, 20, 11
; VI-NEXT: v_or_b32_e32 v5, v5, v6
@@ -5896,11 +5881,11 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v7
; VI-NEXT: v_and_b32_e32 v7, 0x1ff, v1
-; VI-NEXT: v_or_b32_e32 v0, v7, v0
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-NEXT: v_or_b32_e32 v0, v7, v0
; VI-NEXT: v_and_b32_e32 v6, 0xffe, v6
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v1, v1, 20, 11
; VI-NEXT: v_or_b32_e32 v0, v6, v0
@@ -5932,10 +5917,10 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; VI-NEXT: v_and_b32_e32 v6, 0x1ff, v3
-; VI-NEXT: v_or_b32_e32 v2, v6, v2
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; VI-NEXT: v_or_b32_e32 v2, v6, v2
; VI-NEXT: v_and_b32_e32 v1, 0xffe, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_bfe_u32 v3, v3, 20, 11
; VI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -6051,11 +6036,11 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v12, v13, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v10
-; GFX9-NEXT: v_and_or_b32 v0, v1, s4, v0
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v7
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_and_or_b32 v0, v1, s4, v0
; GFX9-NEXT: v_and_or_b32 v5, v6, s7, v5
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX9-NEXT: v_bfe_u32 v7, v1, 20, 11
@@ -6137,78 +6122,77 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 20, 11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 8, v7
; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0x1ff, v5, v4
-; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v5
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v12, 0x3f1, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v5
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 20, 11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v2
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX11-TRUE16-NEXT: v_and_or_b32 v6, 0xffe, v11, v6
+; GFX11-TRUE16-NEXT: v_med3_i32 v11, v12, 0, 13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v3, 20, 11
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v1, 20, 11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x1000, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v7.h
-; GFX11-TRUE16-NEXT: v_and_or_b32 v6, 0xffe, v11, v6
-; GFX11-TRUE16-NEXT: v_med3_i32 v11, v12, 0, 13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x1000, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v11, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 8, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 8, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v14, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v16, v4
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v14, 0x3f1, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v10, 12, v6
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v16, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_med3_i32 v14, v14, 0, 13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x1000, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v21, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, 0x7e00
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x1000, v4
-; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v21, 0x3f1, v19
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 7, v11
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 7, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
-; GFX11-TRUE16-NEXT: v_med3_i32 v21, v21, 0, 13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v18, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, v14, v22
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v12, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v12, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v21, 0x3f1, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v23
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 0x7c00, v13 :: v_dual_add_nc_u32 v11, v11, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, 0x7c00, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_med3_i32 v21, v21, 0, 13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v16
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, v14, v18
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x1000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v12, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, v21, v14
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, v21, v14
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v18, v12
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, 0x7c00, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0xfffffc10, v17
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v10, 0x3f1, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v17, 12, v4
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v21, v22
@@ -6217,42 +6201,40 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v5.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0xfffffc10, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x1000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v14, 12, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, v10, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v22, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v14, 12, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 7, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, v10, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, v10, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 2, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v18
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, v10, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 7, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v10, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 7, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v18, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0xfffffc10, v20
+; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v19
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 12, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 12, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v7 :: v_dual_add_nc_u32 v10, v12, v18
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v19, v20
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 7, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 2, v7
@@ -6303,33 +6285,31 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0x1ff, v7, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v7
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v12, 0x3f1, v10
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v7, 20, 11
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v17, 0x3f1, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0xffe, v11, v4
; GFX11-FAKE16-NEXT: v_med3_i32 v11, v12, 0, 13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x1000, v4
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v17, 0x3f1, v15
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0xffe, v13, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x1000, v4
+; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v2
; GFX11-FAKE16-NEXT: v_med3_i32 v13, v17, 0, 13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, v11, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x1000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, v11, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, v11, v14
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v1, 20, 11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0xfffffc10, v15
@@ -6340,60 +6320,58 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, v13, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v18, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v18, 0x3f1, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 7, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
-; GFX11-FAKE16-NEXT: v_med3_i32 v18, v18, 0, 13
-; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 7, v11
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v13, v17
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v14, 12, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v18, 0x3f1, v12
+; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v16, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v14, 12, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x1000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v3, 20, 11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x1000, v0
+; GFX11-FAKE16-NEXT: v_med3_i32 v18, v18, 0, 13
+; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v17, v2
+; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v17, 0x3f1, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v15
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, v18, v16
-; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v17, v2
-; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v17, 0x3f1, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x1000, v2
+; GFX11-FAKE16-NEXT: v_med3_i32 v17, v17, 0, 13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0xfffffc10, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, 0x7c00, v11 :: v_dual_lshlrev_b32 v18, v18, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 7, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x1000, v2
-; GFX11-FAKE16-NEXT: v_med3_i32 v17, v17, 0, 13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, v17, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 2, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, v17, v21
+; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v18, v16
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, 0x7e00 :: v_dual_lshlrev_b32 v17, v17, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v22
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v22
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v17, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v20, v16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v20, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v23, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0xfffffc10, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v12, 12, v0
@@ -6418,21 +6396,18 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 2, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 2, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v15, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 2, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 2, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7c00, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_add_nc_u32 v13, v15, v13
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v12
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, 0x7c00, v13 :: v_dual_add_nc_u32 v10, v16, v11
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -6968,8 +6943,8 @@ define half @v_copysign_f16_0_f64(double %sign) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.ll b/llvm/test/CodeGen/AMDGPU/fdiv.ll
index 73d55bd72a0f9..e4f782b23e702 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.ll
@@ -4895,8 +4895,8 @@ define float @v_fdiv_neglhs_f32_ieee_25ulp(float %x, float %y) #1 {
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e64 v3, -v0
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e64 v3, -v0, v3, s[4:5]
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
@@ -5101,8 +5101,8 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #2 {
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e64 v3, -v0
-; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e64 v3, -v0, v3, s[4:5]
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
index f01879d98da41..58ec1a6ab67b8 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
@@ -18676,8 +18676,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[5:6] glc
@@ -18797,8 +18797,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -19005,8 +19005,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -19127,8 +19127,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19343,8 +19343,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -19473,8 +19473,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19633,9 +19633,9 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19676,8 +19676,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -19794,8 +19794,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -19948,9 +19948,9 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19993,8 +19993,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -20113,8 +20113,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -20279,9 +20279,9 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -20324,8 +20324,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -20454,8 +20454,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -20662,8 +20662,8 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -20787,8 +20787,8 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -20948,9 +20948,9 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -20993,8 +20993,8 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -21116,8 +21116,8 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -21321,8 +21321,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[5:6] glc
@@ -21442,8 +21442,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -21600,9 +21600,9 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -21643,8 +21643,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -21761,8 +21761,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -21963,8 +21963,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[5:6] glc
@@ -22084,8 +22084,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -22242,9 +22242,9 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -22285,8 +22285,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -22403,8 +22403,8 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 4e3d7947bfbbd..ae4d1fbf9f64d 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -16338,8 +16338,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[5:6] glc
@@ -16459,8 +16459,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -16790,8 +16790,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -16912,8 +16912,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17253,8 +17253,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -17383,8 +17383,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17526,12 +17526,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17661,9 +17660,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17704,8 +17703,8 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -17822,8 +17821,8 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -17959,12 +17958,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18094,9 +18092,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18139,8 +18137,8 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -18259,8 +18257,8 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18399,12 +18397,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18546,9 +18543,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18591,8 +18588,8 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -18721,8 +18718,8 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -19053,8 +19050,8 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -19178,8 +19175,8 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19322,12 +19319,11 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -19458,9 +19454,9 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19503,8 +19499,8 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -19626,8 +19622,8 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 40f58f5ce5902..3ff74eb2e0d80 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -16338,8 +16338,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[5:6] glc
@@ -16459,8 +16459,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -16790,8 +16790,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -16912,8 +16912,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17253,8 +17253,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -17383,8 +17383,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17526,12 +17526,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17661,9 +17660,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17704,8 +17703,8 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -17822,8 +17821,8 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -17959,12 +17958,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18094,9 +18092,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18139,8 +18137,8 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -18259,8 +18257,8 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18399,12 +18397,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18546,9 +18543,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18591,8 +18588,8 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -18721,8 +18718,8 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -19053,8 +19050,8 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -19178,8 +19175,8 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19322,12 +19319,11 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -19458,9 +19454,9 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19503,8 +19499,8 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -19626,8 +19622,8 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
index d2bc7b3f4e48e..82f9337be2cde 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
@@ -15757,8 +15757,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[5:6] glc
@@ -15878,8 +15878,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -16209,8 +16209,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -16331,8 +16331,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -16672,8 +16672,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -16802,8 +16802,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -16945,12 +16945,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17080,9 +17079,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17123,8 +17122,8 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -17241,8 +17240,8 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -17378,12 +17377,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17513,9 +17511,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17558,8 +17556,8 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -17678,8 +17676,8 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -17818,12 +17816,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17965,9 +17962,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18010,8 +18007,8 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -18140,8 +18137,8 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18472,8 +18469,8 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX10-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v0, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v0, v[3:4], v[5:6] glc
@@ -18597,8 +18594,8 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -18741,12 +18738,11 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -18877,9 +18873,9 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18922,8 +18918,8 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
@@ -19045,8 +19041,8 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index 0f10b47a8245e..4af20a0f77fab 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -561,8 +561,8 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX9-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -593,8 +593,8 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
-; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index ea1abbdf3b1c6..efd7d6e2f9dae 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -302,7 +302,6 @@ define amdgpu_ps <16 x float> @test_fmaximum_v16f32(<16 x float> %a, <16 x float
; GFX9-NEXT: v_mov_b32_e32 v33, 0x7fc00000
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v17
; GFX9-NEXT: v_max_f32_e32 v1, v0, v16
-; GFX9-NEXT: v_cmp_o_f32_e64 s[12:13], v0, v16
; GFX9-NEXT: v_max_f32_e32 v17, v2, v18
; GFX9-NEXT: v_cmp_o_f32_e64 s[0:1], v2, v18
; GFX9-NEXT: v_max_f32_e32 v18, v3, v19
@@ -316,6 +315,7 @@ define amdgpu_ps <16 x float> @test_fmaximum_v16f32(<16 x float> %a, <16 x float
; GFX9-NEXT: v_max_f32_e32 v22, v7, v23
; GFX9-NEXT: v_cmp_o_f32_e64 s[10:11], v7, v23
; GFX9-NEXT: v_max_f32_e32 v23, v8, v24
+; GFX9-NEXT: v_cmp_o_f32_e64 s[12:13], v0, v16
; GFX9-NEXT: v_cndmask_b32_e64 v0, v33, v1, s[12:13]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v8, v24
@@ -512,8 +512,8 @@ define amdgpu_ps <2 x half> @test_fmaximum_v2f16_vv(<2 x half> %a, <2 x half> %b
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_pk_max_f16 v2, v0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7e00
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -792,8 +792,8 @@ define amdgpu_ps <4 x half> @test_fmaximum_v4f16(<4 x half> %a, <4 x half> %b) {
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX9-GISEL-NEXT: v_pk_max_f16 v2, v1, v3
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v1, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v1, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v2, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v6, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -908,18 +908,18 @@ define amdgpu_ps <2 x float> @test_fmaximum_f64_vv(double %a, double %b) {
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_f64_vv:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX1170-LABEL: test_fmaximum_f64_vv:
@@ -943,9 +943,9 @@ define amdgpu_ps <2 x float> @test_fmaximum_f64_ss(double inreg %a, double inreg
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff80000
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_f64_ss:
@@ -1006,15 +1006,15 @@ define amdgpu_ps <4 x float> @test_fmaximum_v2f64_ss(<2 x double> inreg %a, <2 x
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s5
; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s7
-; GFX9-SDAG-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, s6
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, s7
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX9-SDAG-NEXT: v_max_f64 v[6:7], s[2:3], v[4:5]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[2:3], v[4:5]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_v2f64_ss:
@@ -1095,42 +1095,42 @@ define amdgpu_ps <8 x float> @test_fmaximum_v4f64(<4 x double> %a, <4 x double>
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX9-SDAG-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX9-SDAG-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], v[2:3], v[10:11]
-; GFX9-SDAG-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-SDAG-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[14:15]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX9-SDAG-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[4:5]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[0:1]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[0:1]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_v4f64:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
-; GFX9-GISEL-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v20, 0x7ff80000
+; GFX9-GISEL-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], v[2:3], v[10:11]
-; GFX9-GISEL-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], v[6:7], v[14:15]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v18, 0x7ff80000
+; GFX9-GISEL-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v18, v9, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v18, v11, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v18, v13, s[4:5]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v20, v17, vcc
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v18, s[0:1]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v20, v19, s[0:1]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v20, v9, vcc
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[14:15]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v10, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v7, v20, v11, vcc
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX1170-LABEL: test_fmaximum_v4f64:
@@ -1160,27 +1160,27 @@ define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9
; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, s10
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, s11
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX9-SDAG-NEXT: v_max_f64 v[6:7], s[2:3], v[4:5]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, s12
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v9, s13
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s11
-; GFX9-SDAG-NEXT: v_max_f64 v[4:5], s[2:3], v[1:2]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[1:2]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s12
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s13
-; GFX9-SDAG-NEXT: v_max_f64 v[6:7], s[4:5], v[1:2]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], s[4:5], v[1:2]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s14
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s15
-; GFX9-SDAG-NEXT: v_max_f64 v[8:9], s[6:7], v[1:2]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[4:5], s[6:7], v[1:2]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v10, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v7, v10, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v10, s[4:5]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[2:3], v[4:5]
+; GFX9-SDAG-NEXT: v_max_f64 v[10:11], s[4:5], v[8:9]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v12, s14
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v13, s15
+; GFX9-SDAG-NEXT: v_max_f64 v[14:15], s[6:7], v[12:13]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[8:9]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v11, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[6:7], v[12:13]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v15, v16, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fmaximum_v4f64_ss:
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 7deaa1d0c62b5..1a86e9ac4406c 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -302,7 +302,6 @@ define amdgpu_ps <16 x float> @test_fminimum_v16f32(<16 x float> %a, <16 x float
; GFX9-NEXT: v_mov_b32_e32 v33, 0x7fc00000
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v17
; GFX9-NEXT: v_min_f32_e32 v1, v0, v16
-; GFX9-NEXT: v_cmp_o_f32_e64 s[12:13], v0, v16
; GFX9-NEXT: v_min_f32_e32 v17, v2, v18
; GFX9-NEXT: v_cmp_o_f32_e64 s[0:1], v2, v18
; GFX9-NEXT: v_min_f32_e32 v18, v3, v19
@@ -316,6 +315,7 @@ define amdgpu_ps <16 x float> @test_fminimum_v16f32(<16 x float> %a, <16 x float
; GFX9-NEXT: v_min_f32_e32 v22, v7, v23
; GFX9-NEXT: v_cmp_o_f32_e64 s[10:11], v7, v23
; GFX9-NEXT: v_min_f32_e32 v23, v8, v24
+; GFX9-NEXT: v_cmp_o_f32_e64 s[12:13], v0, v16
; GFX9-NEXT: v_cndmask_b32_e64 v0, v33, v1, s[12:13]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v8, v24
@@ -512,8 +512,8 @@ define amdgpu_ps <2 x half> @test_fminimum_v2f16_vv(<2 x half> %a, <2 x half> %b
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_pk_min_f16 v2, v0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7e00
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v1
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v1
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -792,8 +792,8 @@ define amdgpu_ps <4 x half> @test_fminimum_v4f16(<4 x half> %a, <4 x half> %b) {
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX9-GISEL-NEXT: v_pk_min_f16 v2, v1, v3
-; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v1, v3
; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v1, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v2, s[0:1]
; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v6, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -908,18 +908,18 @@ define amdgpu_ps <2 x float> @test_fminimum_f64_vv(double %a, double %b) {
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_f64_vv:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX1170-LABEL: test_fminimum_f64_vv:
@@ -943,9 +943,9 @@ define amdgpu_ps <2 x float> @test_fminimum_f64_ss(double inreg %a, double inreg
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX9-SDAG-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff80000
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_f64_ss:
@@ -1006,15 +1006,15 @@ define amdgpu_ps <4 x float> @test_fminimum_v2f64_ss(<2 x double> inreg %a, <2 x
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s5
; GFX9-SDAG-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s7
-; GFX9-SDAG-NEXT: v_min_f64 v[4:5], s[2:3], v[0:1]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, s6
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, s7
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX9-SDAG-NEXT: v_min_f64 v[6:7], s[2:3], v[4:5]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[2:3], v[4:5]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_v2f64_ss:
@@ -1095,42 +1095,42 @@ define amdgpu_ps <8 x float> @test_fminimum_v4f64(<4 x double> %a, <4 x double>
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX9-SDAG-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX9-SDAG-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], v[2:3], v[10:11]
-; GFX9-SDAG-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-SDAG-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[14:15]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX9-SDAG-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[4:5]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[0:1]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[0:1]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_v4f64:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
-; GFX9-GISEL-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v20, 0x7ff80000
+; GFX9-GISEL-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], v[2:3], v[10:11]
-; GFX9-GISEL-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], v[6:7], v[14:15]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v18, 0x7ff80000
+; GFX9-GISEL-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v18, v9, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v18, v11, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v18, v13, s[4:5]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v20, v17, vcc
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v18, s[0:1]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v20, v19, s[0:1]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v20, v9, vcc
+; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[14:15]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v10, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v7, v20, v11, vcc
; GFX9-GISEL-NEXT: ; return to shader part epilog
;
; GFX1170-LABEL: test_fminimum_v4f64:
@@ -1160,27 +1160,27 @@ define amdgpu_ps <8 x float> @test_fminimum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9
; GFX9-SDAG-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff80000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, s10
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, s11
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX9-SDAG-NEXT: v_min_f64 v[6:7], s[2:3], v[4:5]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, s12
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v9, s13
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s11
-; GFX9-SDAG-NEXT: v_min_f64 v[4:5], s[2:3], v[1:2]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[1:2]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s12
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s13
-; GFX9-SDAG-NEXT: v_min_f64 v[6:7], s[4:5], v[1:2]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], s[4:5], v[1:2]
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s14
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s15
-; GFX9-SDAG-NEXT: v_min_f64 v[8:9], s[6:7], v[1:2]
-; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[4:5], s[6:7], v[1:2]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v10, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v7, v10, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v10, s[4:5]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[2:3], v[4:5]
+; GFX9-SDAG-NEXT: v_min_f64 v[10:11], s[4:5], v[8:9]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v12, s14
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v13, s15
+; GFX9-SDAG-NEXT: v_min_f64 v[14:15], s[6:7], v[12:13]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[8:9]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v11, v16, vcc
+; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[6:7], v[12:13]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, 0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v15, v16, vcc
; GFX9-SDAG-NEXT: ; return to shader part epilog
;
; GFX9-GISEL-LABEL: test_fminimum_v4f64_ss:
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index 95d2f07402dd4..e8483740fa354 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -5543,8 +5543,8 @@ define double @v_contract_mul_add_f64_select_2_4(i32 %arg, double %x, double %y)
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x40100000
-; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v6, 2.0, vcc
; GFX9-SDAG-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4]
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -5562,8 +5562,8 @@ define double @v_contract_mul_add_f64_select_2_4(i32 %arg, double %x, double %y)
; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_2_4:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, 0x40100000, 2.0, vcc_lo
; GFX10-SDAG-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4]
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -5581,8 +5581,8 @@ define double @v_contract_mul_add_f64_select_2_4(i32 %arg, double %x, double %y)
; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_2_4:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0
+; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, 0x40100000, 2.0, vcc_lo
; GFX11-SDAG-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4]
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -5862,8 +5862,8 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
@@ -5889,8 +5889,8 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
@@ -5900,8 +5900,8 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
@@ -5945,8 +5945,8 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
@@ -5972,8 +5972,8 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
@@ -5983,8 +5983,8 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, -v1, v0
@@ -6406,8 +6406,8 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
@@ -6436,9 +6436,8 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
@@ -6448,9 +6447,8 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
@@ -6579,8 +6577,8 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
@@ -6609,9 +6607,8 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 2, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
@@ -6621,9 +6618,8 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 2, v0
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
@@ -6759,10 +6755,10 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) {
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -6795,8 +6791,8 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6804,13 +6800,13 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
@@ -6863,10 +6859,10 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) {
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -6899,8 +6895,8 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6908,13 +6904,13 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
@@ -6941,9 +6937,9 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -6965,14 +6961,14 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX10-GISEL-LABEL: v_mul_v2f16_select_n1_n64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -7006,23 +7002,23 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_n1_n64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
@@ -7079,17 +7075,17 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -7122,12 +7118,12 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7135,18 +7131,17 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
@@ -7204,18 +7199,18 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
-; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -7246,15 +7241,16 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7262,19 +7258,18 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
@@ -7301,9 +7296,9 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -7325,14 +7320,14 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) {
; GFX10-GISEL-LABEL: v_mul_v2f16_select_n128_n16:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -7366,23 +7361,23 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_n128_n16:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
@@ -7436,10 +7431,10 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -7473,8 +7468,8 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7483,13 +7478,13 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7545,10 +7540,10 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -7582,8 +7577,8 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7592,13 +7587,13 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7627,9 +7622,9 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -7652,14 +7647,14 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h
; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -7694,8 +7689,8 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h
; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7703,15 +7698,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7740,9 +7735,9 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -7765,14 +7760,14 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h
; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -7807,8 +7802,8 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h
; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7816,15 +7811,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7884,17 +7879,17 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -7928,9 +7923,10 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
@@ -7942,12 +7938,13 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
@@ -8008,10 +8005,10 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 2, 7, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -8045,8 +8042,8 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 2, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -8055,13 +8052,13 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 2, 7, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -8121,17 +8118,17 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 2, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -8165,9 +8162,10 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 2, v1
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
@@ -8179,12 +8177,13 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 2, v1
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
@@ -8245,10 +8244,10 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 7, 2, vcc_lo
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -8282,8 +8281,8 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 7, 2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -8292,13 +8291,13 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 7, 2, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index 13e4206ab7f57..c9b0f00dc082e 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -2001,8 +2001,8 @@ define half @v_fneg_fma_f16(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2077,8 +2077,8 @@ define { half, half } @v_fneg_fma_store_use_fma_f16(half %a, half %b, half %c) #
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2155,8 +2155,8 @@ define { half, half } @v_fneg_fma_multi_use_fma_f16(half %a, half %b, half %c) #
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2239,8 +2239,8 @@ define { half, half } @v_fneg_fma_multi_use_fma_f16_nsz(half %a, half %b, half %
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2320,8 +2320,8 @@ define half @v_fneg_fma_fneg_x_y_f16(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2397,8 +2397,8 @@ define half @v_fneg_fma_fneg_x_y_f16_nsz(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2470,8 +2470,8 @@ define half @v_fneg_fma_x_fneg_y_f16(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2547,8 +2547,8 @@ define half @v_fneg_fma_x_fneg_y_f16_nsz(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2620,8 +2620,8 @@ define half @v_fneg_fma_fneg_fneg_y_f16(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2698,8 +2698,8 @@ define half @v_fneg_fma_fneg_fneg_y_f16_nsz(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2772,8 +2772,8 @@ define half @v_fneg_fma_fneg_x_fneg_f16(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2850,8 +2850,8 @@ define half @v_fneg_fma_fneg_x_fneg_f16_nsz(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -2924,8 +2924,8 @@ define half @v_fneg_fma_x_y_fneg_f16(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -3001,8 +3001,8 @@ define half @v_fneg_fma_x_y_fneg_f16_nsz(half %a, half %b, half %c) #0 {
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -3075,8 +3075,8 @@ define { half, half } @v_fneg_fma_store_use_fneg_x_y_f16(half %a, half %b, half
; SI-NEXT: v_fma_f64 v[0:1], v[6:7], v[4:5], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
@@ -3160,8 +3160,8 @@ define { half, half } @v_fneg_fma_store_use_fneg_x_y_f16_nsz(half %a, half %b, h
; SI-NEXT: v_xor_b32_e32 v1, 0xffff8000, v0
; SI-NEXT: v_and_b32_e32 v0, 0x1ff, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v4, v3, 20, 11
@@ -3241,8 +3241,8 @@ define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16(half %a, half %b, half
; SI-NEXT: v_fma_f64 v[0:1], v[6:7], v[4:5], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
@@ -3329,8 +3329,8 @@ define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16_nsz(half %a, half %b, h
; SI-NEXT: v_fma_f64 v[1:2], v[6:7], v[4:5], v[1:2]
; SI-NEXT: v_and_b32_e32 v4, 0x1ff, v2
; SI-NEXT: v_or_b32_e32 v1, v4, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v4, 0xffe, v4
; SI-NEXT: v_bfe_u32 v5, v2, 20, 11
@@ -3923,8 +3923,8 @@ define half @v_fneg_fp_round_f64_to_f16(double %a) #0 {
; SI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -3972,8 +3972,8 @@ define half @v_fneg_fp_round_f64_to_f16(double %a) #0 {
; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; VI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; VI-NEXT: v_or_b32_e32 v0, v2, v0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; VI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -4025,11 +4025,11 @@ define half @v_fneg_fp_round_f64_to_f16(double %a) #0 {
; GFX11-NEXT: v_bfe_u32 v3, v1, 20, 11
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX11-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_med3_i32 v2, v4, 0, 13
; GFX11-NEXT: v_or_b32_e32 v4, 0x1000, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4075,8 +4075,8 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -4122,8 +4122,8 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; VI-NEXT: v_or_b32_e32 v0, v2, v0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; VI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -4171,11 +4171,11 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v1
; GFX11-NEXT: v_bfe_u32 v3, v1, 20, 11
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
; GFX11-NEXT: v_med3_i32 v2, v4, 0, 13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4225,8 +4225,8 @@ define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0
; SI-NEXT: v_mov_b32_e32 v3, v0
; SI-NEXT: v_and_b32_e32 v0, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v4, 0xffe, v4
; SI-NEXT: v_bfe_u32 v5, v1, 20, 11
@@ -4276,8 +4276,8 @@ define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0
; VI-NEXT: v_mov_b32_e32 v3, v0
; VI-NEXT: v_and_b32_e32 v0, 0x1ff, v1
; VI-NEXT: v_or_b32_e32 v0, v0, v3
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_and_b32_e32 v4, 0xffe, v4
; VI-NEXT: v_bfe_u32 v5, v1, 20, 11
@@ -4327,11 +4327,11 @@ define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0
; GFX11-NEXT: v_and_or_b32 v2, 0x1ff, v1, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX11-NEXT: v_bfe_u32 v4, v1, 20, 11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v4
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v2, 0xffe, v3, v2
; GFX11-NEXT: v_med3_i32 v3, v5, 0, 13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4385,8 +4385,8 @@ define { half, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f16(double %a, do
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v4, v4, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v5, 0xffe, v5
; SI-NEXT: v_bfe_u32 v6, v1, 20, 11
@@ -4435,8 +4435,8 @@ define { half, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f16(double %a, do
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v4, 0x1ff, v1
; VI-NEXT: v_or_b32_e32 v4, v4, v0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-NEXT: v_and_b32_e32 v5, 0xffe, v5
; VI-NEXT: v_bfe_u32 v6, v1, 20, 11
@@ -4490,43 +4490,43 @@ define { half, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f16(double %a, do
; GFX11-NEXT: v_mul_f64 v[2:3], -v[0:1], v[2:3]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 0x3f1, v6
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 0x3f1, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v4, 0xffe, v5, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_med3_i32 v5, v7, 0, 13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v7, 0x1000, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v8, v5, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v5, v5, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v7
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshl_or_b32 v7, v6, 12, v4
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v0, 7, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v0
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_mov_b32 v7, 0x7e00 :: v_dual_add_nc_u32 v0, v5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7c00, v7, vcc_lo
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
; GFX11-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4545,8 +4545,8 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -4593,8 +4593,8 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; VI-NEXT: v_or_b32_e32 v0, v2, v0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; VI-NEXT: v_bfe_u32 v3, v1, 20, 11
@@ -4643,11 +4643,11 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v1
; GFX11-NEXT: v_bfe_u32 v3, v1, 20, 11
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
; GFX11-NEXT: v_med3_i32 v2, v4, 0, 13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5146,8 +5146,8 @@ define { half, half } @multiuse_fneg_2_vop3_users_f16(half %a, half %b, half %c)
; SI-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v6, 0x1ff, v3
; SI-NEXT: v_or_b32_e32 v2, v6, v2
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v6, 0xffe, v6
; SI-NEXT: v_bfe_u32 v7, v3, 20, 11
@@ -5187,8 +5187,8 @@ define { half, half } @multiuse_fneg_2_vop3_users_f16(half %a, half %b, half %c)
; SI-NEXT: v_or_b32_e32 v0, v3, v6
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v2
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v4, v2, 20, 11
@@ -5301,10 +5301,10 @@ define { half, half } @multiuse_fneg_vop2_vop3_users_f16(ptr addrspace(1) %out,
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v5
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], 2.0
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v2, v0
@@ -5385,8 +5385,8 @@ define { half, half } @free_fold_src_code_size_cost_use_f16(ptr addrspace(1) %ou
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], 2.0
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
@@ -5476,8 +5476,8 @@ define { half, half } @free_fold_src_code_size_cost_use_f16_nsz(ptr addrspace(1)
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], -2.0
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
@@ -5657,11 +5657,11 @@ define { half, half } @multi_use_cost_to_fold_into_src(ptr addrspace(1) %out, ha
; SI-NEXT: v_cvt_f64_f32_e32 v[6:7], v4
; SI-NEXT: v_fma_f64 v[0:1], v[6:7], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_sub_i32_e32 v3, vcc, s4, v4
@@ -5756,8 +5756,8 @@ define <2 x half> @fneg_fma_fneg_dagcombine_loop(<2 x half> %arg, <2 x half> %ar
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_and_b32_e32 v5, 0x1ff, v4
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v5, 0xffe, v5
; SI-NEXT: v_bfe_u32 v6, v4, 20, 11
@@ -5802,8 +5802,8 @@ define <2 x half> @fneg_fma_fneg_dagcombine_loop(<2 x half> %arg, <2 x half> %ar
; SI-NEXT: v_cvt_f32_f16_e32 v5, v9
; SI-NEXT: v_and_b32_e32 v6, 0x1ff, v4
; SI-NEXT: v_or_b32_e32 v3, v6, v3
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v4
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v6, 0xffe, v6
; SI-NEXT: v_bfe_u32 v7, v4, 20, 11
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 3cbde439cdf99..4543389ede993 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -578,59 +578,32 @@ define { double, double } @v_fneg_add_multi_use_fneg_x_f64_nsz(double %a, double
; This one asserted with -enable-no-signed-zeros-fp-math
define amdgpu_ps double @fneg_fadd_0_f64(double inreg %tmp2, double inreg %tmp6, <4 x i32> %arg) #0 {
-; SI-LABEL: fneg_fadd_0_f64:
-; SI: ; %bb.0: ; %.entry
-; SI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; SI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; SI-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; SI-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; SI-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
-; SI-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; SI-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; SI-NEXT: v_mov_b32_e32 v2, s1
-; SI-NEXT: v_mov_b32_e32 v3, s0
-; SI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; SI-NEXT: v_add_f64 v[0:1], v[0:1], 0
-; SI-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
-; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v1
-; SI-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; SI-NEXT: s_mov_b32 s0, 0
-; SI-NEXT: ; return to shader part epilog
-;
-; VI-LABEL: fneg_fadd_0_f64:
-; VI: ; %bb.0: ; %.entry
-; VI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; VI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; VI-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; VI-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; VI-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; VI-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
-; VI-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; VI-NEXT: v_mov_b32_e32 v4, s0
-; VI-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; VI-NEXT: v_mov_b32_e32 v2, s1
-; VI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; VI-NEXT: v_add_f64 v[0:1], v[0:1], 0
-; VI-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
-; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; VI-NEXT: s_mov_b32 s0, 0
-; VI-NEXT: ; return to shader part epilog
+; GCN-LABEL: fneg_fadd_0_f64:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
+; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GCN-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
+; GCN-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
+; GCN-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
+; GCN-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
+; GCN-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
+; GCN-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
+; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], 0
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 0
+; GCN-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
+; GCN-NEXT: v_xor_b32_e32 v4, 0x80000000, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GCN-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
+; GCN-NEXT: s_and_b64 s[0:1], vcc, exec
+; GCN-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
+; GCN-NEXT: s_mov_b32 s0, 0
+; GCN-NEXT: ; return to shader part epilog
.entry:
%tmp7 = fdiv double 1.000000e+00, %tmp6
%tmp8 = fmul double 0.000000e+00, %tmp7
@@ -1661,10 +1634,10 @@ define double @v_fneg_inv2pi_minimum_f64(double %a) #0 {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_min_f64 v[2:3], v[0:1], 0.15915494309189532
+; VI-NEXT: v_mov_b32_e32 v4, 0xfff80000
; VI-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, 0xfff80000
; VI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, -v3, v1, vcc
+; VI-NEXT: v_cndmask_b32_e64 v1, -v3, v4, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
%min = call double @llvm.minimum.f64(double 0x3fc45f306dc9c882, double %a)
%fneg = fneg double %min
@@ -1689,9 +1662,9 @@ define double @v_fneg_neg_inv2pi_minimum_f64(double %a) #0 {
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_max_f64 v[2:3], -v[0:1], 0.15915494309189532
; VI-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; VI-NEXT: v_mov_b32_e32 v4, 0x7ff80000
; VI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
%min = call double @llvm.minimum.f64(double 0xbfc45f306dc9c882, double %a)
%fneg = fneg double %min
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 64431cb31ea6e..a80b61d31efab 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -133,11 +133,11 @@ define <2 x i64> @fneg_xor_select_v2i64(<2 x i1> %cond, <2 x i64> %arg0, <2 x i6
; GCN-LABEL: fneg_xor_select_v2i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 1, v1
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_and_b32_e32 v1, 1, v1
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
; GCN-NEXT: v_cndmask_b32_e64 v2, v8, v4, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v1, -v7, -v3, vcc
; GCN-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, s[4:5]
@@ -147,29 +147,28 @@ define <2 x i64> @fneg_xor_select_v2i64(<2 x i1> %cond, <2 x i64> %arg0, <2 x i6
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v8, v4, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, -v7, -v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v10.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v4, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fneg_xor_select_v2i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v6, v2 :: v_dual_and_b32 v1, 1, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, -v7, -v3, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v8, v4, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%select = select <2 x i1> %cond, <2 x i64> %arg0, <2 x i64> %arg1
%fneg = xor <2 x i64> %select, <i64 9223372036854775808, i64 9223372036854775808>
@@ -570,8 +569,8 @@ define i64 @select_fneg_xor_select_i64(i1 %cond0, i1 %cond1, i64 %arg0, i64 %arg
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
-; GCN-NEXT: v_and_b32_e32 v1, 1, v1
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_and_b32_e32 v1, 1, v1
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, -v3, v5, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
@@ -1054,12 +1053,12 @@ define float @cospiD_pattern0_half(i16 %arg, float %arg1, float %arg2) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 1, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffff8000, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
index cb0ebc495c5a7..744bc32e56992 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
@@ -525,18 +525,18 @@ define amdgpu_kernel void @fp_to_sint_v2i64(ptr addrspace(1) %out, <2 x float> %
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v1, 31, v1
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_xor_b32_e32 v7, v2, v0
; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_xor_b32_e32 v5, v5, v1
; GFX11-SDAG-NEXT: v_xor_b32_e32 v8, v3, v1
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v5, v5, v1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v4, v0
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v3, null, v7, v0, vcc_lo
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v5, v1
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v8, v1, vcc_lo
; GFX11-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]
@@ -816,32 +816,32 @@ define amdgpu_kernel void @fp_to_sint_v4i64(ptr addrspace(1) %out, <4 x float> %
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v12, 31, v3
; GFX11-SDAG-NEXT: v_fma_f32 v3, 0xcf800000, v11, |v3|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v9, 31, v1
-; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-SDAG-NEXT: v_fma_f32 v1, 0xcf800000, v6, |v1|
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v13, v4
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v6
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v6, v7
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v5
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v7, v11
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v5
; GFX11-SDAG-NEXT: v_xor_b32_e32 v11, v13, v5
; GFX11-SDAG-NEXT: v_xor_b32_e32 v13, v4, v9
; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v6, v10
; GFX11-SDAG-NEXT: v_xor_b32_e32 v6, v2, v10
-; GFX11-SDAG-NEXT: v_xor_b32_e32 v15, v3, v12
-; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v5
; GFX11-SDAG-NEXT: v_xor_b32_e32 v14, v7, v12
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v15, v3, v12
; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v9
+; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v3, null, v11, v5, vcc_lo
; GFX11-SDAG-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v10
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v7, null, v4, v10, vcc_lo
; GFX11-SDAG-NEXT: v_sub_co_u32 v4, vcc_lo, v15, v12
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v5, null, v14, v12, vcc_lo
; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v9
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v13, v9, vcc_lo
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll b/llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll
index c685ad75b47f7..f016d01785884 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll
@@ -8,9 +8,9 @@ define void @scalar(double %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; CHECK-NEXT: v_and_b32_e32 v7, 1, v6
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v4, v6, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -37,9 +37,9 @@ define void @v2(<2 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v8, v[0:1]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[6:7], v8
; CHECK-NEXT: v_and_b32_e32 v9, 1, v8
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[6:7]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[6:7]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v9
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[6:7]|
; CHECK-NEXT: v_cndmask_b32_e64 v6, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v6, v8, v6
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -53,9 +53,9 @@ define void @v2(<2 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v7, v[2:3]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v7
; CHECK-NEXT: v_and_b32_e32 v8, 1, v7
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v8
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v0, v7, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -83,9 +83,9 @@ define void @v3(<3 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v10, v[0:1]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[8:9], v10
; CHECK-NEXT: v_and_b32_e32 v11, 1, v10
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[8:9]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[8:9]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[8:9]|
; CHECK-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v8, v10, v8
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -99,9 +99,9 @@ define void @v3(<3 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v9, v[2:3]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v9
; CHECK-NEXT: v_and_b32_e32 v10, 1, v9
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v10
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v0, v9, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -116,9 +116,9 @@ define void @v3(<3 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v2, v0, v8, s4
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v3
; CHECK-NEXT: v_and_b32_e32 v8, 1, v3
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v8
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v0, v3, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -145,9 +145,9 @@ define void @v4(<4 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v12, v[4:5]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[10:11], v12
; CHECK-NEXT: v_and_b32_e32 v13, 1, v12
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[10:11]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[10:11]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v13
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[10:11]|
; CHECK-NEXT: v_cndmask_b32_e64 v10, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v10, v12, v10
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -161,9 +161,9 @@ define void @v4(<4 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v11, v[6:7]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v11
; CHECK-NEXT: v_and_b32_e32 v12, 1, v11
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[6:7], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v12
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v4, v11, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -178,9 +178,9 @@ define void @v4(<4 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v4, v[0:1]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[6:7], v4
; CHECK-NEXT: v_and_b32_e32 v10, 1, v4
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[6:7]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[6:7]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v10
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[6:7]|
; CHECK-NEXT: v_cndmask_b32_e64 v6, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v6, v4, v6
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -193,9 +193,9 @@ define void @v4(<4 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v6, v[2:3]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v6
; CHECK-NEXT: v_and_b32_e32 v7, 1, v6
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v0, v6, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -222,9 +222,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v20, v[12:13]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[18:19], v20
; CHECK-NEXT: v_and_b32_e32 v21, 1, v20
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[12:13]|, |v[18:19]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[12:13], v[18:19]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v21
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[12:13]|, |v[18:19]|
; CHECK-NEXT: v_cndmask_b32_e64 v18, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v18, v20, v18
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -238,9 +238,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v19, v[14:15]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[12:13], v19
; CHECK-NEXT: v_and_b32_e32 v20, 1, v19
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[14:15]|, |v[12:13]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[14:15], v[12:13]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v20
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[14:15]|, |v[12:13]|
; CHECK-NEXT: v_cndmask_b32_e64 v12, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v12, v19, v12
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -255,9 +255,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v12, v[8:9]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[14:15], v12
; CHECK-NEXT: v_and_b32_e32 v18, 1, v12
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[8:9]|, |v[14:15]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[8:9], v[14:15]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v18
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[8:9]|, |v[14:15]|
; CHECK-NEXT: v_cndmask_b32_e64 v14, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v14, v12, v14
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -270,9 +270,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v14, v[10:11]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[8:9], v14
; CHECK-NEXT: v_and_b32_e32 v15, 1, v14
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[10:11]|, |v[8:9]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[10:11], v[8:9]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v15
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[10:11]|, |v[8:9]|
; CHECK-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v8, v14, v8
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -286,9 +286,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v12, v8, v12, s9
; CHECK-NEXT: v_cvt_f64_f32_e32 v[8:9], v10
; CHECK-NEXT: v_and_b32_e32 v11, 1, v10
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[8:9]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[8:9]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, |v[8:9]|
; CHECK-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v8, v10, v8
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -301,9 +301,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v9, v[6:7]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v9
; CHECK-NEXT: v_and_b32_e32 v10, 1, v9
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[6:7], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v10
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[6:7]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v4, v9, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -317,9 +317,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v11, v4, v8, s9
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; CHECK-NEXT: v_and_b32_e32 v7, 1, v6
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v4, v6, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -332,9 +332,9 @@ define void @v8(<8 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v5, v[2:3]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
; CHECK-NEXT: v_and_b32_e32 v6, 1, v5
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v6
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v0, v5, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -364,9 +364,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v36, v[12:13]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[34:35], v36
; CHECK-NEXT: v_and_b32_e32 v37, 1, v36
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[12:13]|, |v[34:35]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[12:13], v[34:35]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v37
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[12:13]|, |v[34:35]|
; CHECK-NEXT: v_cndmask_b32_e64 v34, -1, 1, s[6:7]
; CHECK-NEXT: v_add_u32_e32 v34, v36, v34
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -380,9 +380,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v35, v[14:15]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[12:13], v35
; CHECK-NEXT: v_and_b32_e32 v36, 1, v35
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[14:15]|, |v[12:13]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[14:15], v[12:13]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v36
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[14:15]|, |v[12:13]|
; CHECK-NEXT: v_cndmask_b32_e64 v12, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v12, v35, v12
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -397,9 +397,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v12, v[8:9]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[14:15], v12
; CHECK-NEXT: v_and_b32_e32 v34, 1, v12
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[8:9]|, |v[14:15]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[8:9], v[14:15]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v34
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[8:9]|, |v[14:15]|
; CHECK-NEXT: v_cndmask_b32_e64 v14, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v14, v12, v14
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -412,9 +412,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v14, v[10:11]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[8:9], v14
; CHECK-NEXT: v_and_b32_e32 v15, 1, v14
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[10:11]|, |v[8:9]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[10:11], v[8:9]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v15
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[10:11]|, |v[8:9]|
; CHECK-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v8, v14, v8
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -428,9 +428,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v12, v8, v12, s7
; CHECK-NEXT: v_cvt_f64_f32_e32 v[8:9], v10
; CHECK-NEXT: v_and_b32_e32 v11, 1, v10
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[4:5]|, |v[8:9]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[4:5], v[8:9]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[4:5]|, |v[8:9]|
; CHECK-NEXT: v_cndmask_b32_e64 v8, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v8, v10, v8
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -443,9 +443,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v9, v[6:7]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v9
; CHECK-NEXT: v_and_b32_e32 v10, 1, v9
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[6:7]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[6:7], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v10
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[6:7]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v4, v9, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -459,9 +459,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v11, v4, v8, s7
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; CHECK-NEXT: v_and_b32_e32 v7, 1, v6
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[0:1]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[0:1]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v4, v6, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -474,9 +474,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v5, v[2:3]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
; CHECK-NEXT: v_and_b32_e32 v6, 1, v5
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v6
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[2:3]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v5, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -490,9 +490,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v10, v0, v4, s7
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
; CHECK-NEXT: v_and_b32_e32 v3, 1, v2
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[28:29]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[28:29], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v3
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[28:29]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v2, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -506,9 +506,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v3
; CHECK-NEXT: v_and_b32_e32 v4, 1, v3
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[30:31]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[30:31], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v4
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[30:31]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v3, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -522,9 +522,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v2, v[24:25]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
; CHECK-NEXT: v_and_b32_e32 v4, 1, v2
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[24:25]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[24:25], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v4
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[24:25]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v2, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -537,9 +537,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v4
; CHECK-NEXT: v_and_b32_e32 v5, 1, v4
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[26:27]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[26:27], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v5
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[26:27]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v4, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -553,9 +553,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_perm_b32 v2, v0, v2, s7
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v4
; CHECK-NEXT: v_and_b32_e32 v5, 1, v4
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[20:21]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[20:21], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v5
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[20:21]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v4, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -568,9 +568,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc
; CHECK-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
; CHECK-NEXT: v_and_b32_e32 v6, 1, v5
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[22:23]|, |v[0:1]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[22:23], v[0:1]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v6
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[22:23]|, |v[0:1]|
; CHECK-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v0, v5, v0
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -584,9 +584,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cvt_f32_f64_e32 v0, v[16:17]
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v0
; CHECK-NEXT: v_and_b32_e32 v6, 1, v0
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[16:17]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[16:17], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v6
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[16:17]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v4, v0, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
@@ -599,9 +599,9 @@ define void @v16(<16 x double> %num, ptr addrspace(1) %p) {
; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; CHECK-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; CHECK-NEXT: v_and_b32_e32 v7, 1, v6
-; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[18:19]|, |v[4:5]|
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, v[18:19], v[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; CHECK-NEXT: v_cmp_gt_f64_e64 s[8:9], |v[18:19]|, |v[4:5]|
; CHECK-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[8:9]
; CHECK-NEXT: v_add_u32_e32 v4, v6, v4
; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
index 4233430eafb83..8024c799dac55 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
@@ -265,8 +265,8 @@ define i128 @fptoui_f64_to_i128(double %x) {
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; SDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
; SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
; SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
@@ -326,10 +326,10 @@ define i128 @fptoui_f64_to_i128(double %x) {
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
@@ -657,10 +657,10 @@ define i128 @fptoui_f32_to_i128(float %x) {
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
@@ -960,8 +960,8 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
; SDAG-NEXT: v_cmp_gt_u16_e32 vcc, 64, v6
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; SDAG-NEXT: v_cmp_ne_u16_e64 s[4:5], 0, v6
; SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SDAG-NEXT: v_cmp_ne_u16_e64 s[4:5], 0, v6
; SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index df84d78e8e355..3fd5d3080ae65 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -233,8 +233,8 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; GFX7-ISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v1
; GFX7-ISEL-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s4, v0
-; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5effffff
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5effffff
; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v0
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
@@ -295,8 +295,8 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v1
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s4, v0
-; GFX9-NEXT: s_mov_b32 s4, 0x5effffff
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5effffff
; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v0
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
@@ -1071,26 +1071,26 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
; GFX7-ISEL-NEXT: s_movk_i32 s4, 0xffe0
-; GFX7-ISEL-NEXT: s_mov_b32 s8, 0
-; GFX7-ISEL-NEXT: s_mov_b32 s9, 0xc1f00000
+; GFX7-ISEL-NEXT: s_mov_b32 s6, 0
+; GFX7-ISEL-NEXT: s_mov_b32 s7, 0xc1f00000
; GFX7-ISEL-NEXT: s_mov_b32 s5, 0xc3e00000
-; GFX7-ISEL-NEXT: s_mov_b32 s6, -1
-; GFX7-ISEL-NEXT: s_mov_b32 s7, 0x43dfffff
; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v6, 1
; GFX7-ISEL-NEXT: v_ldexp_f64 v[4:5], v[2:3], s4
; GFX7-ISEL-NEXT: s_mov_b32 s4, 0
; GFX7-ISEL-NEXT: v_cmp_nle_f64_e32 vcc, s[4:5], v[0:1]
+; GFX7-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
+; GFX7-ISEL-NEXT: v_fma_f64 v[2:3], v[4:5], s[6:7], v[2:3]
+; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v4, v[4:5]
+; GFX7-ISEL-NEXT: s_mov_b32 s6, -1
+; GFX7-ISEL-NEXT: s_mov_b32 s7, 0x43dfffff
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], s[6:7], v[0:1]
; GFX7-ISEL-NEXT: v_cmp_u_f64_e64 s[6:7], v[0:1], v[0:1]
-; GFX7-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
-; GFX7-ISEL-NEXT: v_fma_f64 v[2:3], v[4:5], s[8:9], v[2:3]
-; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v7, v[4:5]
-; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v4, -2
-; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0, s[6:7]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[2:3]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v4, v5, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1103,26 +1103,26 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x3df00000
; GFX7-GI-NEXT: v_mov_b32_e32 v6, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0xc1f00000
-; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[6:7], v[0:1], v[0:1]
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v10, 1
+; GFX7-GI-NEXT: v_mov_b32_e32 v8, -1
+; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0x43dfffff
; GFX7-GI-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
; GFX7-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-GI-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], v[2:3]
-; GFX7-GI-NEXT: v_mov_b32_e32 v6, -1
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0x43dfffff
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[4:5], v[0:1], v[6:7]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v8, v[2:3]
-; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0xc3e00000
-; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v1, v[4:5]
-; GFX7-GI-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, 0
+; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0xc3e00000
+; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v3, v[4:5]
; GFX7-GI-NEXT: v_bfrev_b32_e32 v4, -2
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX7-GI-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i64_f64:
@@ -1130,26 +1130,26 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
; GFX9-NEXT: s_movk_i32 s4, 0xffe0
-; GFX9-NEXT: s_mov_b32 s8, 0
-; GFX9-NEXT: s_mov_b32 s9, 0xc1f00000
+; GFX9-NEXT: s_mov_b32 s6, 0
+; GFX9-NEXT: s_mov_b32 s7, 0xc1f00000
; GFX9-NEXT: s_mov_b32 s5, 0xc3e00000
-; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: s_mov_b32 s7, 0x43dfffff
; GFX9-NEXT: v_bfrev_b32_e32 v6, 1
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[2:3], s4
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: v_cmp_nle_f64_e32 vcc, s[4:5], v[0:1]
+; GFX9-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
+; GFX9-NEXT: v_fma_f64 v[2:3], v[4:5], s[6:7], v[2:3]
+; GFX9-NEXT: v_cvt_i32_f64_e32 v4, v[4:5]
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: s_mov_b32 s7, 0x43dfffff
+; GFX9-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_cmp_lt_f64_e64 s[4:5], s[6:7], v[0:1]
; GFX9-NEXT: v_cmp_u_f64_e64 s[6:7], v[0:1], v[0:1]
-; GFX9-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
-; GFX9-NEXT: v_fma_f64 v[2:3], v[4:5], s[8:9], v[2:3]
-; GFX9-NEXT: v_cvt_i32_f64_e32 v7, v[4:5]
-; GFX9-NEXT: v_bfrev_b32_e32 v4, -2
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, 0, s[6:7]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1161,19 +1161,19 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: s_mov_b32 s1, 0x43dfffff
-; GFX11-NEXT: v_cmp_lt_f64_e64 s0, s[0:1], v[0:1]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[0:1], v[0:1]
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[2:3], 0xffffffe0
; GFX11-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
; GFX11-NEXT: v_cvt_i32_f64_e32 v4, v[4:5]
; GFX11-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, 0x80000000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i64_f64:
@@ -1187,9 +1187,6 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX12-ISEL-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
; GFX12-ISEL-NEXT: s_mov_b32 s0, -1
; GFX12-ISEL-NEXT: s_mov_b32 s1, 0x43dfffff
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s0, s[0:1], v[0:1]
-; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s1, v[0:1], v[0:1]
; GFX12-ISEL-NEXT: v_ldexp_f64 v[4:5], v[2:3], 0xffffffe0
; GFX12-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-ISEL-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
@@ -1197,12 +1194,16 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v4, 0x80000000, vcc_lo
-; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0, s1
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX12-ISEL-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i64_f64:
@@ -1214,22 +1215,23 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
; GFX12-GI-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
-; GFX12-GI-NEXT: v_cmp_u_f64_e64 s1, v[0:1], v[0:1]
; GFX12-GI-NEXT: v_mul_f64_e32 v[4:5], 0x3df00000, v[2:3]
; GFX12-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-GI-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v4, v[4:5]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v6, v[2:3]
; GFX12-GI-NEXT: v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v3, 0x43dfffff
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s0, v[0:1], v[2:3]
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v4, 0x80000000, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0x80000000, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc_lo
-; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v5, -1, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v0, 0x7fffffff, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v2, 0, s1
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s1
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v5, -1, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
ret i64 %x
@@ -1440,22 +1442,22 @@ define i64 @test_s_signed_i64_f64(double inreg %f) nounwind {
; GFX7-ISEL-NEXT: s_mov_b32 s5, 0xc1f00000
; GFX7-ISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX7-ISEL-NEXT: v_mov_b32_e32 v5, 0xc3e00000
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v6, -1
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v7, 0x43dfffff
; GFX7-ISEL-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[4:5]
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v8, 1
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v6, -1
; GFX7-ISEL-NEXT: v_ldexp_f64 v[2:3], v[0:1], s4
; GFX7-ISEL-NEXT: s_mov_b32 s4, 0
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v7, 0x43dfffff
; GFX7-ISEL-NEXT: v_cmp_u_f64_e64 s[6:7], s[16:17], s[16:17]
-; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v8, 1
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
; GFX7-ISEL-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v3, -2
; GFX7-ISEL-NEXT: v_cmp_gt_f64_e64 s[4:5], s[16:17], v[6:7]
-; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v9, v[2:3]
-; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v2, -2
-; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
@@ -1469,26 +1471,26 @@ define i64 @test_s_signed_i64_f64(double inreg %f) nounwind {
; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x3df00000
; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0xc1f00000
-; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[6:7], s[16:17], s[16:17]
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v8, 1
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, -1
+; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0x43dfffff
; GFX7-GI-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], s[16:17]
; GFX7-GI-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
; GFX7-GI-NEXT: v_fma_f64 v[0:1], v[2:3], v[4:5], v[0:1]
-; GFX7-GI-NEXT: v_mov_b32_e32 v4, -1
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x43dfffff
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[4:5], s[16:17], v[4:5]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v6, v[0:1]
-; GFX7-GI-NEXT: v_mov_b32_e32 v0, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xc3e00000
-; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[0:1]
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0xc3e00000
+; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[4:5]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
-; GFX7-GI-NEXT: v_bfrev_b32_e32 v2, 1
-; GFX7-GI-NEXT: v_bfrev_b32_e32 v3, -2
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[6:7]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i64_f64:
@@ -1499,22 +1501,22 @@ define i64 @test_s_signed_i64_f64(double inreg %f) nounwind {
; GFX9-NEXT: s_mov_b32 s5, 0xc1f00000
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0xc3e00000
-; GFX9-NEXT: v_mov_b32_e32 v6, -1
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x43dfffff
; GFX9-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[4:5]
+; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
+; GFX9-NEXT: v_mov_b32_e32 v6, -1
; GFX9-NEXT: v_ldexp_f64 v[2:3], v[0:1], s4
; GFX9-NEXT: s_mov_b32 s4, 0
+; GFX9-NEXT: v_mov_b32_e32 v7, 0x43dfffff
; GFX9-NEXT: v_cmp_u_f64_e64 s[6:7], s[16:17], s[16:17]
-; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
; GFX9-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; GFX9-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX9-NEXT: v_bfrev_b32_e32 v3, -2
; GFX9-NEXT: v_cmp_gt_f64_e64 s[4:5], s[16:17], v[6:7]
-; GFX9-NEXT: v_cvt_i32_f64_e32 v9, v[2:3]
-; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
@@ -1585,16 +1587,17 @@ define i64 @test_s_signed_i64_f64(double inreg %f) nounwind {
; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v4, v[0:1]
; GFX12-GI-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, 0x43dfffff
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0x80000000, s2
; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fffffff, vcc_lo
; GFX12-GI-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, 0x80000000, s2
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s2
-; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
ret i64 %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index eaadd335ba98d..4d3ca7ba0976b 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -1653,18 +1653,18 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v13, -2
; GFX7-ISEL-NEXT: v_fma_f64 v[4:5], v[8:9], s[6:7], v[4:5]
; GFX7-ISEL-NEXT: v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7]
-; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], s[8:9], v[0:1]
-; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v14, v[8:9]
; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v15, v[10:11]
+; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], s[8:9], v[0:1]
+; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v8, v14, v12, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v15, v12, s[4:5]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[6:7]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v15, v12, s[4:5]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v9, v13, s[8:9]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v9, v13, s[8:9]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v8, 0, s[10:11]
@@ -1682,15 +1682,11 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0x3df00000
; GFX7-GI-NEXT: v_mov_b32_e32 v12, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0xc1f00000
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v16, 1
; GFX7-GI-NEXT: v_mov_b32_e32 v14, -1
-; GFX7-GI-NEXT: v_mov_b32_e32 v15, 0x43dfffff
; GFX7-GI-NEXT: v_mul_f64 v[10:11], v[4:5], v[8:9]
; GFX7-GI-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[10:11], v[2:3], v[14:15]
-; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[12:13], v[2:3], v[2:3]
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[6:7], v[0:1], v[14:15]
-; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[8:9], v[0:1], v[0:1]
-; GFX7-GI-NEXT: v_bfrev_b32_e32 v16, 1
+; GFX7-GI-NEXT: v_mov_b32_e32 v15, 0x43dfffff
; GFX7-GI-NEXT: v_bfrev_b32_e32 v17, -2
; GFX7-GI-NEXT: v_floor_f64_e32 v[10:11], v[10:11]
; GFX7-GI-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
@@ -1698,24 +1694,28 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX7-GI-NEXT: v_fma_f64 v[6:7], v[8:9], v[12:13], v[6:7]
; GFX7-GI-NEXT: v_mov_b32_e32 v12, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0xc3e00000
-; GFX7-GI-NEXT: v_cmp_nge_f64_e64 s[4:5], v[2:3], v[12:13]
; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[12:13]
; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v10, v[10:11]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v6, v[6:7]
; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v5, v[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v6, -1, s[10:11]
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v7, v10, v16, vcc
; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[12:13]
-; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v10, v16, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v5, v16, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, v17, s[10:11]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[12:13]
+; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, v[2:3], v[12:13]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[14:15]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, v[2:3], v[14:15]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc
+; GFX7-GI-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v7, 0, vcc
+; GFX7-GI-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[2:3]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_v2f64_v2i64:
@@ -1742,18 +1742,18 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX9-NEXT: v_bfrev_b32_e32 v13, -2
; GFX9-NEXT: v_fma_f64 v[4:5], v[8:9], s[6:7], v[4:5]
; GFX9-NEXT: v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7]
-; GFX9-NEXT: v_cmp_lt_f64_e64 s[6:7], s[8:9], v[0:1]
-; GFX9-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
; GFX9-NEXT: v_cvt_i32_f64_e32 v14, v[8:9]
; GFX9-NEXT: v_cvt_i32_f64_e32 v15, v[10:11]
+; GFX9-NEXT: v_cmp_lt_f64_e64 s[6:7], s[8:9], v[0:1]
+; GFX9-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v8, v14, v12, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v15, v12, s[4:5]
; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v15, v12, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v13, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v13, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, 0, s[10:11]
@@ -1771,10 +1771,6 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX11-NEXT: v_cmp_nle_f64_e64 s0, 0xc3e00000, v[2:3]
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: s_mov_b32 s3, 0x43dfffff
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_lt_f64_e64 s1, s[2:3], v[0:1]
-; GFX11-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[0:1], v[0:1]
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[4:5], 0xffffffe0
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[6:7], 0xffffffe0
; GFX11-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
@@ -1787,16 +1783,20 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX11-NEXT: v_cvt_u32_f64_e32 v5, v[6:7]
; GFX11-NEXT: v_cndmask_b32_e64 v6, v8, 0x80000000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, 0x80000000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0x7fffffff, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v7, 0x7fffffff, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v0, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
+; GFX11-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0x7fffffff, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f64_e64 s0, s[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0x7fffffff, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, -1, s0
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v6, 0, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v1, -1, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, -1, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v6, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_v2f64_v2i64:
@@ -1812,11 +1812,6 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX12-ISEL-NEXT: v_cmp_nle_f64_e64 s0, 0xc3e00000, v[2:3]
; GFX12-ISEL-NEXT: s_mov_b32 s2, -1
; GFX12-ISEL-NEXT: s_mov_b32 s3, 0x43dfffff
-; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[2:3]
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s1, s[2:3], v[0:1]
-; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], v[2:3]
-; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s3, v[0:1], v[0:1]
; GFX12-ISEL-NEXT: v_ldexp_f64 v[8:9], v[4:5], 0xffffffe0
; GFX12-ISEL-NEXT: v_ldexp_f64 v[10:11], v[6:7], 0xffffffe0
; GFX12-ISEL-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
@@ -1831,16 +1826,25 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v6, v8, 0x80000000, vcc_lo
; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v7, v9, 0x80000000, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x7fffffff, s1
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v7, 0x7fffffff, s2
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v0, 0, s4
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x7fffffff, vcc_lo
+; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s0, s[2:3], v[2:3]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, 0x7fffffff, s0
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s0
+; GFX12-ISEL-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v6, 0, vcc_lo
+; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[2:3]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v7, 0, s0
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v5, 0, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v4, v1, -1, s1
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s2
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v6, 0, s3
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0, s3
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v2f64_v2i64:
@@ -1853,36 +1857,40 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; GFX12-GI-NEXT: v_trunc_f64_e32 v[4:5], v[0:1]
; GFX12-GI-NEXT: v_trunc_f64_e32 v[6:7], v[2:3]
; GFX12-GI-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
-; GFX12-GI-NEXT: v_cmp_nle_f64_e64 s0, 0xc3e00000, v[2:3]
-; GFX12-GI-NEXT: v_cmp_u_f64_e64 s3, v[0:1], v[0:1]
-; GFX12-GI-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[2:3]
; GFX12-GI-NEXT: v_mul_f64_e32 v[8:9], 0x3df00000, v[4:5]
; GFX12-GI-NEXT: v_mul_f64_e32 v[10:11], 0x3df00000, v[6:7]
; GFX12-GI-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
; GFX12-GI-NEXT: v_floor_f64_e32 v[10:11], v[10:11]
; GFX12-GI-NEXT: v_fma_f64 v[4:5], 0xc1f00000, v[8:9], v[4:5]
; GFX12-GI-NEXT: v_fma_f64 v[6:7], 0xc1f00000, v[10:11], v[6:7]
+; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v12, v[4:5]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v6, v[6:7]
+; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v7, v[10:11]
; GFX12-GI-NEXT: v_dual_mov_b32 v4, -1 :: v_dual_mov_b32 v5, 0x43dfffff
-; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v7, v[8:9]
-; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v8, v[10:11]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s1, v[0:1], v[4:5]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s2, v[2:3], v[4:5]
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v12, 0, vcc_lo
-; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v7, 0x80000000, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v8, 0x80000000, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v9, -1, s1
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v6, -1, s2
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v0, 0x7fffffff, s1
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v2, 0x7fffffff, s2
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v4, 0, s3
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v1, 0, s4
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, s3
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v5, 0, s4
+; GFX12-GI-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0x80000000, vcc_lo
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v9, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v6, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v7, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v9, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x
@@ -2147,44 +2155,44 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX7-ISEL-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
; GFX7-ISEL-NEXT: v_trunc_f64_e32 v[2:3], s[18:19]
; GFX7-ISEL-NEXT: s_movk_i32 s4, 0xffe0
-; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x43dfffff
; GFX7-ISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX7-ISEL-NEXT: v_mov_b32_e32 v9, 0xc3e00000
+; GFX7-ISEL-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[8:9]
; GFX7-ISEL-NEXT: s_mov_b32 s6, 0
; GFX7-ISEL-NEXT: s_mov_b32 s7, 0xc1f00000
; GFX7-ISEL-NEXT: v_ldexp_f64 v[4:5], v[0:1], s4
; GFX7-ISEL-NEXT: v_ldexp_f64 v[6:7], v[2:3], s4
+; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x43dfffff
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v12, 1
; GFX7-ISEL-NEXT: s_mov_b32 s4, -1
; GFX7-ISEL-NEXT: v_mov_b32_e32 v11, s5
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v13, -2
; GFX7-ISEL-NEXT: v_mov_b32_e32 v10, s4
-; GFX7-ISEL-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[8:9]
-; GFX7-ISEL-NEXT: v_cmp_nge_f64_e64 s[4:5], s[18:19], v[8:9]
-; GFX7-ISEL-NEXT: v_cmp_gt_f64_e64 s[8:9], s[18:19], v[10:11]
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nge_f64_e64 s[4:5], s[18:19], v[8:9]
+; GFX7-ISEL-NEXT: v_cmp_gt_f64_e64 s[8:9], s[18:19], v[10:11]
; GFX7-ISEL-NEXT: v_cmp_u_f64_e64 s[10:11], s[16:17], s[16:17]
; GFX7-ISEL-NEXT: v_cmp_u_f64_e64 s[12:13], s[18:19], s[18:19]
-; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v12, 1
-; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v13, -2
; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v14, v[4:5]
; GFX7-ISEL-NEXT: v_cvt_i32_f64_e32 v15, v[6:7]
; GFX7-ISEL-NEXT: v_fma_f64 v[4:5], v[4:5], s[6:7], v[0:1]
; GFX7-ISEL-NEXT: v_fma_f64 v[6:7], v[6:7], s[6:7], v[2:3]
-; GFX7-ISEL-NEXT: v_cmp_gt_f64_e64 s[6:7], s[16:17], v[10:11]
; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v0, v14, v12, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v15, v12, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v1, v13, s[8:9]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v2, 0, s[12:13]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[6:7]
+; GFX7-ISEL-NEXT: v_cmp_gt_f64_e64 s[6:7], s[16:17], v[10:11]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, v13, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v1, v13, s[8:9]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v2, 0, s[12:13]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[6:7]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_v2f64_v2i64:
@@ -2196,16 +2204,13 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x3df00000
; GFX7-GI-NEXT: v_mov_b32_e32 v8, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0xc1f00000
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v12, 1
; GFX7-GI-NEXT: v_mov_b32_e32 v10, -1
-; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0x43dfffff
; GFX7-GI-NEXT: v_mul_f64 v[6:7], v[0:1], v[4:5]
; GFX7-GI-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[16:17], v[10:11]
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[18:19], v[10:11]
-; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[10:11], s[16:17], s[16:17]
-; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[12:13], s[18:19], s[18:19]
-; GFX7-GI-NEXT: v_bfrev_b32_e32 v12, 1
+; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0x43dfffff
; GFX7-GI-NEXT: v_bfrev_b32_e32 v13, -2
+; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], s[16:17]
; GFX7-GI-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
; GFX7-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-GI-NEXT: v_fma_f64 v[0:1], v[6:7], v[8:9], v[0:1]
@@ -2213,23 +2218,26 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX7-GI-NEXT: v_mov_b32_e32 v8, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0xc3e00000
; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[8:9]
-; GFX7-GI-NEXT: v_cmp_nge_f64_e64 s[4:5], s[18:19], v[8:9]
; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
-; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v1, v[4:5]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX7-GI-NEXT: v_cvt_i32_f64_e32 v1, v[4:5]
; GFX7-GI-NEXT: v_cndmask_b32_e32 v3, v6, v12, vcc
; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-GI-NEXT: v_cmp_nge_f64_e32 vcc, s[18:19], v[8:9]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[10:11]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[18:19], v[10:11]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v4, v1, v13, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[4:5]
+; GFX7-GI-NEXT: v_cmp_u_f64_e64 s[4:5], s[18:19], s[18:19]
; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, v12, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, v13, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v1, v13, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[10:11]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s[12:13]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s[4:5]
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_v2f64_v2i64:
@@ -2238,44 +2246,44 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX9-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
; GFX9-NEXT: v_trunc_f64_e32 v[2:3], s[18:19]
; GFX9-NEXT: s_movk_i32 s4, 0xffe0
-; GFX9-NEXT: s_mov_b32 s5, 0x43dfffff
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc3e00000
+; GFX9-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[8:9]
; GFX9-NEXT: s_mov_b32 s6, 0
; GFX9-NEXT: s_mov_b32 s7, 0xc1f00000
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[0:1], s4
; GFX9-NEXT: v_ldexp_f64 v[6:7], v[2:3], s4
+; GFX9-NEXT: s_mov_b32 s5, 0x43dfffff
+; GFX9-NEXT: v_bfrev_b32_e32 v12, 1
; GFX9-NEXT: s_mov_b32 s4, -1
; GFX9-NEXT: v_mov_b32_e32 v11, s5
+; GFX9-NEXT: v_bfrev_b32_e32 v13, -2
; GFX9-NEXT: v_mov_b32_e32 v10, s4
-; GFX9-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[8:9]
-; GFX9-NEXT: v_cmp_nge_f64_e64 s[4:5], s[18:19], v[8:9]
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[8:9], s[18:19], v[10:11]
; GFX9-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
+; GFX9-NEXT: v_cmp_nge_f64_e64 s[4:5], s[18:19], v[8:9]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[8:9], s[18:19], v[10:11]
; GFX9-NEXT: v_cmp_u_f64_e64 s[10:11], s[16:17], s[16:17]
; GFX9-NEXT: v_cmp_u_f64_e64 s[12:13], s[18:19], s[18:19]
-; GFX9-NEXT: v_bfrev_b32_e32 v12, 1
-; GFX9-NEXT: v_bfrev_b32_e32 v13, -2
; GFX9-NEXT: v_cvt_i32_f64_e32 v14, v[4:5]
; GFX9-NEXT: v_cvt_i32_f64_e32 v15, v[6:7]
; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], s[6:7], v[0:1]
; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], s[6:7], v[2:3]
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], s[16:17], v[10:11]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v14, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v15, v12, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v1, v13, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v2, 0, s[12:13]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[6:7]
+; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], s[16:17], v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v13, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v1, v13, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11]
; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v2, 0, s[12:13]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_v2f64_v2i64:
@@ -2287,10 +2295,6 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX11-NEXT: v_cmp_nle_f64_e64 s7, 0xc3e00000, s[2:3]
; GFX11-NEXT: s_mov_b32 s4, -1
; GFX11-NEXT: s_mov_b32 s5, 0x43dfffff
-; GFX11-NEXT: v_cmp_gt_f64_e64 s8, s[0:1], s[4:5]
-; GFX11-NEXT: v_cmp_gt_f64_e64 s4, s[2:3], s[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, s[2:3], s[2:3]
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[0:1], 0xffffffe0
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[2:3], 0xffffffe0
; GFX11-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
@@ -2303,14 +2307,18 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX11-NEXT: v_cvt_u32_f64_e32 v1, v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0x80000000, s6
; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x80000000, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0x7fffffff, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, s1
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s6
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -1, s8
+; GFX11-NEXT: v_cmp_gt_f64_e64 s6, s[0:1], s[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0x7fffffff, s6
+; GFX11-NEXT: v_cmp_gt_f64_e64 s4, s[2:3], s[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -1, s6
; GFX11-NEXT: v_cndmask_b32_e64 v4, v1, -1, s4
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, s[2:3], s[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, s1
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2328,11 +2336,6 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: v_cmp_nle_f64_e64 s7, 0xc3e00000, s[2:3]
; GFX12-ISEL-NEXT: s_mov_b32 s4, -1
; GFX12-ISEL-NEXT: s_mov_b32 s5, 0x43dfffff
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_cmp_gt_f64_e64 s8, s[0:1], s[4:5]
-; GFX12-ISEL-NEXT: v_cmp_gt_f64_e64 s4, s[2:3], s[4:5]
-; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
-; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s1, s[2:3], s[2:3]
; GFX12-ISEL-NEXT: v_ldexp_f64 v[4:5], v[0:1], 0xffffffe0
; GFX12-ISEL-NEXT: v_ldexp_f64 v[6:7], v[2:3], 0xffffffe0
; GFX12-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
@@ -2346,14 +2349,23 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0x80000000, s6
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v5, 0x80000000, s7
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0x7fffffff, s8
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s4
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s1
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s6
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s7
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_cmp_gt_f64_e64 s6, s[0:1], s[4:5]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0x7fffffff, s6
+; GFX12-ISEL-NEXT: v_cmp_gt_f64_e64 s4, s[2:3], s[4:5]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s4
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s6
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v4, v1, -1, s4
+; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
+; GFX12-ISEL-NEXT: v_cmp_u_f64_e64 s1, s[2:3], s[2:3]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s1
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s1
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2367,37 +2379,40 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_trunc_f64_e32 v[0:1], s[0:1]
; GFX12-GI-NEXT: v_trunc_f64_e32 v[2:3], s[2:3]
-; GFX12-GI-NEXT: v_cmp_nle_f64_e64 s6, 0xc3e00000, s[2:3]
-; GFX12-GI-NEXT: v_cmp_nle_f64_e64 s5, 0xc3e00000, s[0:1]
+; GFX12-GI-NEXT: v_cmp_nle_f64_e64 s4, 0xc3e00000, s[0:1]
; GFX12-GI-NEXT: v_mul_f64_e32 v[4:5], 0x3df00000, v[0:1]
; GFX12-GI-NEXT: v_mul_f64_e32 v[6:7], 0x3df00000, v[2:3]
; GFX12-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-GI-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
; GFX12-GI-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[4:5], v[0:1]
; GFX12-GI-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[6:7], v[2:3]
+; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v4, v[4:5]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v8, v[0:1]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v3, v[6:7]
; GFX12-GI-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, 0x43dfffff
-; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v3, v[4:5]
-; GFX12-GI-NEXT: v_cvt_i32_f64_e32 v4, v[6:7]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s4, s[2:3], v[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0x80000000, s4
; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0x7fffffff, vcc_lo
; GFX12-GI-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
-; GFX12-GI-NEXT: v_cmp_u_f64_e64 s1, s[2:3], s[2:3]
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v8, 0, s4
+; GFX12-GI-NEXT: v_cmp_nle_f64_e64 s4, 0xc3e00000, s[2:3]
; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v8, 0, s5
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s6
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, -1, s4
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v3, 0x80000000, s5
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0x80000000, s6
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0x80000000, s4
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, -1, vcc_lo
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v5, -1, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v2, 0x7fffffff, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, s4
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v1, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0x7fffffff, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v4, 0, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v5, 0, s0
+; GFX12-GI-NEXT: v_cmp_u_f64_e64 s0, s[2:3], s[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
index 334bca75f8711..fd7a357c2c2b7 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
@@ -441,14 +441,14 @@ define i64 @test_s_unsigned_i64_f32(float inreg %f) nounwind {
; GFX7-ISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX7-ISEL-NEXT: v_floor_f32_e32 v1, v1
; GFX7-ISEL-NEXT: s_mov_b32 s4, 0xcf800000
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX7-ISEL-NEXT: v_fma_f32 v0, v1, s4, v0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX7-ISEL-NEXT: v_cmp_nge_f32_e64 s[4:5], s16, 0
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[4:5]
; GFX7-ISEL-NEXT: v_mov_b32_e32 v2, 0x5f7fffff
-; GFX7-ISEL-NEXT: v_cmp_gt_f32_e32 vcc, s16, v2
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_gt_f32_e32 vcc, s16, v2
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
@@ -479,14 +479,14 @@ define i64 @test_s_unsigned_i64_f32(float inreg %f) nounwind {
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_floor_f32_e32 v1, v1
; GFX9-NEXT: s_mov_b32 s4, 0xcf800000
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX9-NEXT: v_fma_f32 v0, v1, s4, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cmp_nge_f32_e64 s[4:5], s16, 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v2, 0x5f7fffff
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s16, v2
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s16, v2
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -729,14 +729,14 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX7-ISEL-NEXT: s_mov_b32 s4, 0
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-ISEL-NEXT: v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
; GFX7-ISEL-NEXT: s_mov_b32 s4, -1
; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x43efffff
; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], s[4:5], v[0:1]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v6, v[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v6, 0, vcc
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[2:3]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v4, -1, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v4, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v3, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -752,15 +752,15 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX7-GI-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
; GFX7-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-GI-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], v[2:3]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v6, v[2:3]
; GFX7-GI-NEXT: v_mov_b32_e32 v2, -1
; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x43efffff
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[4:5], v[0:1], v[2:3]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v1, v[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v6, -1, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v5, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v4, -1, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_unsigned_i64_f64:
@@ -774,14 +774,14 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT: v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
; GFX9-NEXT: s_mov_b32 s4, -1
; GFX9-NEXT: s_mov_b32 s5, 0x43efffff
; GFX9-NEXT: v_cmp_lt_f64_e64 s[4:5], s[4:5], v[0:1]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v6, v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, 0, vcc
-; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, -1, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -792,16 +792,16 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: s_mov_b32 s1, 0x43efffff
-; GFX11-NEXT: v_cmp_lt_f64_e64 s0, s[0:1], v[0:1]
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[2:3], 0xffffffe0
; GFX11-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
; GFX11-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
; GFX11-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, -1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_unsigned_i64_f64:
@@ -815,8 +815,6 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX12-ISEL-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0, v[0:1]
; GFX12-ISEL-NEXT: s_mov_b32 s0, -1
; GFX12-ISEL-NEXT: s_mov_b32 s1, 0x43efffff
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s0, s[0:1], v[0:1]
; GFX12-ISEL-NEXT: v_ldexp_f64 v[4:5], v[2:3], 0xffffffe0
; GFX12-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-ISEL-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
@@ -824,10 +822,12 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v4, 0, vcc_lo
-; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v3, -1, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s0
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_i64_f64:
@@ -845,13 +845,13 @@ define i64 @test_unsigned_i64_f64(double %f) nounwind {
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v6, v[2:3]
; GFX12-GI-NEXT: v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v3, 0x43efffff
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s0, v[0:1], v[2:3]
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc_lo
-; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v5, -1, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, s0
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v4, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v5, -1, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
ret i64 %x
@@ -1004,19 +1004,19 @@ define i64 @test_s_unsigned_i64_f64(double inreg %f) nounwind {
; GFX7-ISEL-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
; GFX7-ISEL-NEXT: s_movk_i32 s4, 0xffe0
; GFX7-ISEL-NEXT: s_mov_b32 s5, 0xc1f00000
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v4, -1
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v5, 0x43efffff
+; GFX7-ISEL-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[4:5]
; GFX7-ISEL-NEXT: v_ldexp_f64 v[2:3], v[0:1], s4
; GFX7-ISEL-NEXT: s_mov_b32 s4, 0
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
; GFX7-ISEL-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v4, v[2:3]
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v2, -1
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v3, 0x43efffff
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX7-ISEL-NEXT: v_cmp_nge_f64_e64 s[4:5], s[16:17], 0
-; GFX7-ISEL-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[2:3]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v4, -1, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1032,15 +1032,15 @@ define i64 @test_s_unsigned_i64_f64(double inreg %f) nounwind {
; GFX7-GI-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX7-GI-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
; GFX7-GI-NEXT: v_fma_f64 v[0:1], v[2:3], v[4:5], v[0:1]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v4, v[0:1]
; GFX7-GI-NEXT: v_mov_b32_e32 v0, -1
; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x43efffff
; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[0:1]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v1, v[2:3]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v4, -1, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_unsigned_i64_f64:
@@ -1049,19 +1049,19 @@ define i64 @test_s_unsigned_i64_f64(double inreg %f) nounwind {
; GFX9-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
; GFX9-NEXT: s_movk_i32 s4, 0xffe0
; GFX9-NEXT: s_mov_b32 s5, 0xc1f00000
+; GFX9-NEXT: v_mov_b32_e32 v4, -1
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x43efffff
+; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[4:5]
; GFX9-NEXT: v_ldexp_f64 v[2:3], v[0:1], s4
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v4, v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v2, -1
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x43efffff
+; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX9-NEXT: v_cmp_nge_f64_e64 s[4:5], s[16:17], 0
-; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[2:3]
; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1124,13 +1124,13 @@ define i64 @test_s_unsigned_i64_f64(double inreg %f) nounwind {
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v4, v[0:1]
; GFX12-GI-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, 0x43efffff
-; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[0:1]
; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, 0, s2
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s2
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s2
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[0:1]
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s2
; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
ret i64 %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index bec0da9707fdf..eb2aa454debf4 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -1587,28 +1587,28 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX7-ISEL-NEXT: s_mov_b32 s5, 0xc1f00000
; GFX7-ISEL-NEXT: s_mov_b32 s8, -1
; GFX7-ISEL-NEXT: s_mov_b32 s9, 0x43efffff
-; GFX7-ISEL-NEXT: v_cmp_nle_f64_e64 s[6:7], 0, v[2:3]
; GFX7-ISEL-NEXT: v_cmp_nle_f64_e32 vcc, 0, v[0:1]
+; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], s[8:9], v[0:1]
; GFX7-ISEL-NEXT: v_ldexp_f64 v[8:9], v[4:5], s4
; GFX7-ISEL-NEXT: v_ldexp_f64 v[10:11], v[6:7], s4
; GFX7-ISEL-NEXT: s_mov_b32 s4, 0
+; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[10:11], v[10:11]
; GFX7-ISEL-NEXT: v_fma_f64 v[4:5], v[8:9], s[4:5], v[4:5]
; GFX7-ISEL-NEXT: v_fma_f64 v[6:7], v[10:11], s[4:5], v[6:7]
-; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], s[8:9], v[0:1]
-; GFX7-ISEL-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v13, v[10:11]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v12, v[8:9]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v13, 0, s[6:7]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[4:5]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v4, v[6:7]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v13, v[10:11]
+; GFX7-ISEL-NEXT: v_cmp_nle_f64_e64 s[4:5], 0, v[2:3]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v12, 0, vcc
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v0, -1, s[8:9]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[6:7]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v8, -1, s[4:5]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v13, 0, s[4:5]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v4, v[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v8, -1, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v9, -1, s[8:9]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1621,7 +1621,6 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0x3df00000
; GFX7-GI-NEXT: v_mov_b32_e32 v12, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0xc1f00000
-; GFX7-GI-NEXT: v_cmp_nle_f64_e64 s[6:7], 0, v[2:3]
; GFX7-GI-NEXT: v_cmp_nle_f64_e32 vcc, 0, v[0:1]
; GFX7-GI-NEXT: v_mul_f64 v[10:11], v[4:5], v[8:9]
; GFX7-GI-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
@@ -1629,22 +1628,23 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX7-GI-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
; GFX7-GI-NEXT: v_fma_f64 v[4:5], v[10:11], v[12:13], v[4:5]
; GFX7-GI-NEXT: v_fma_f64 v[6:7], v[8:9], v[12:13], v[6:7]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v12, v[4:5]
-; GFX7-GI-NEXT: v_mov_b32_e32 v4, -1
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x43efffff
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[8:9], v[2:3], v[4:5]
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[4:5], v[0:1], v[4:5]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v10, v[10:11]
+; GFX7-GI-NEXT: v_mov_b32_e32 v12, -1
+; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0x43efffff
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v5, v[8:9]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v6, v[6:7]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v3, v[10:11]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v4, v[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v12, 0, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v6, 0, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v1, -1, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v7, -1, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, -1, s[8:9]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v10, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f64_e32 vcc, 0, v[2:3]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[12:13]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v4, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v7, -1, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, v[2:3], v[12:13]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v6, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v5, -1, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_unsigned_v2f64_v2i64:
@@ -1656,28 +1656,28 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX9-NEXT: s_mov_b32 s5, 0xc1f00000
; GFX9-NEXT: s_mov_b32 s8, -1
; GFX9-NEXT: s_mov_b32 s9, 0x43efffff
-; GFX9-NEXT: v_cmp_nle_f64_e64 s[6:7], 0, v[2:3]
; GFX9-NEXT: v_cmp_nle_f64_e32 vcc, 0, v[0:1]
+; GFX9-NEXT: v_cmp_lt_f64_e64 s[6:7], s[8:9], v[0:1]
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[4:5], s4
; GFX9-NEXT: v_ldexp_f64 v[10:11], v[6:7], s4
; GFX9-NEXT: s_mov_b32 s4, 0
+; GFX9-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
; GFX9-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
; GFX9-NEXT: v_floor_f64_e32 v[10:11], v[10:11]
; GFX9-NEXT: v_fma_f64 v[4:5], v[8:9], s[4:5], v[4:5]
; GFX9-NEXT: v_fma_f64 v[6:7], v[10:11], s[4:5], v[6:7]
-; GFX9-NEXT: v_cmp_lt_f64_e64 s[4:5], s[8:9], v[0:1]
-; GFX9-NEXT: v_cmp_lt_f64_e64 s[8:9], s[8:9], v[2:3]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v13, v[10:11]
; GFX9-NEXT: v_cvt_u32_f64_e32 v12, v[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v13, 0, s[6:7]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[4:5]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v4, v[6:7]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v13, v[10:11]
+; GFX9-NEXT: v_cmp_nle_f64_e64 s[4:5], 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v8, v12, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v0, -1, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, -1, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v13, 0, s[4:5]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v4, v[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, -1, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[8:9]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1690,8 +1690,6 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX11-NEXT: v_cmp_nle_f64_e64 s0, 0, v[2:3]
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: s_mov_b32 s3, 0x43efffff
-; GFX11-NEXT: v_cmp_lt_f64_e64 s1, s[2:3], v[0:1]
-; GFX11-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], v[2:3]
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[4:5], 0xffffffe0
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[6:7], 0xffffffe0
; GFX11-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
@@ -1703,13 +1701,15 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX11-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
; GFX11-NEXT: v_cvt_u32_f64_e32 v5, v[6:7]
; GFX11-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v9, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v6, -1, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v0, -1, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -1, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, -1, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
+; GFX11-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v6, -1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f64_e64 s0, s[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, -1, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_unsigned_v2f64_v2i64:
@@ -1725,9 +1725,6 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX12-ISEL-NEXT: v_cmp_nle_f64_e64 s0, 0, v[2:3]
; GFX12-ISEL-NEXT: s_mov_b32 s2, -1
; GFX12-ISEL-NEXT: s_mov_b32 s3, 0x43efffff
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s1, s[2:3], v[0:1]
-; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], v[2:3]
; GFX12-ISEL-NEXT: v_ldexp_f64 v[8:9], v[4:5], 0xffffffe0
; GFX12-ISEL-NEXT: v_ldexp_f64 v[10:11], v[6:7], 0xffffffe0
; GFX12-ISEL-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
@@ -1741,13 +1738,18 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc_lo
; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v9, 0, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v6, -1, s1
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v0, -1, s2
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v4, v5, 0, s0
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v2, -1, s1
-; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v4, -1, s2
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v7, v9, 0, s0
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v1, v6, -1, vcc_lo
+; GFX12-ISEL-NEXT: v_cmp_lt_f64_e64 s0, s[2:3], v[2:3]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v3, v7, -1, s0
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v0, v4, -1, vcc_lo
+; GFX12-ISEL-NEXT: v_cndmask_b32_e64 v2, v5, -1, s0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v2f64_v2i64:
@@ -1760,30 +1762,32 @@ define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; GFX12-GI-NEXT: v_trunc_f64_e32 v[4:5], v[0:1]
; GFX12-GI-NEXT: v_trunc_f64_e32 v[6:7], v[2:3]
; GFX12-GI-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0, v[0:1]
-; GFX12-GI-NEXT: v_cmp_nle_f64_e64 s0, 0, v[2:3]
; GFX12-GI-NEXT: v_mul_f64_e32 v[8:9], 0x3df00000, v[4:5]
; GFX12-GI-NEXT: v_mul_f64_e32 v[10:11], 0x3df00000, v[6:7]
; GFX12-GI-NEXT: v_floor_f64_e32 v[8:9], v[8:9]
; GFX12-GI-NEXT: v_floor_f64_e32 v[10:11], v[10:11]
; GFX12-GI-NEXT: v_fma_f64 v[4:5], 0xc1f00000, v[8:9], v[4:5]
; GFX12-GI-NEXT: v_fma_f64 v[6:7], 0xc1f00000, v[10:11], v[6:7]
+; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v8, v[8:9]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v12, v[4:5]
; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v6, v[6:7]
+; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v7, v[10:11]
; GFX12-GI-NEXT: v_dual_mov_b32 v4, -1 :: v_dual_mov_b32 v5, 0x43efffff
-; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v7, v[8:9]
-; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v8, v[10:11]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s1, v[0:1], v[4:5]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s2, v[2:3], v[4:5]
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v12, 0, vcc_lo
-; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v6, 0, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v7, 0, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v8, 0, s0
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v9, -1, s1
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v1, -1, s2
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v3, -1, s1
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, -1, s2
+; GFX12-GI-NEXT: v_cmp_nle_f64_e32 vcc_lo, 0, v[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v9, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v8, -1, vcc_lo
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v6, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v7, -1, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x
@@ -2017,19 +2021,19 @@ define <2 x i64> @test_s_unsigned_v2f64_v2i64(<2 x double> inreg %f) {
; GFX7-ISEL-NEXT: v_cmp_gt_f64_e64 s[4:5], s[18:19], v[8:9]
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-ISEL-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
-; GFX7-ISEL-NEXT: v_fma_f64 v[0:1], v[4:5], s[6:7], v[0:1]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v10, v[4:5]
+; GFX7-ISEL-NEXT: v_fma_f64 v[4:5], v[4:5], s[6:7], v[0:1]
; GFX7-ISEL-NEXT: v_fma_f64 v[2:3], v[6:7], s[6:7], v[2:3]
; GFX7-ISEL-NEXT: v_cmp_nge_f64_e64 s[6:7], s[16:17], 0
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v10, v[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v10, 0, s[6:7]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v11, v[6:7]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, v11, 0, s[8:9]
-; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v0, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v11, 0, s[8:9]
+; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
; GFX7-ISEL-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v4, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v6, -1, s[4:5]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[8:9]
-; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v5, -1, s[4:5]
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2043,30 +2047,30 @@ define <2 x i64> @test_s_unsigned_v2f64_v2i64(<2 x double> inreg %f) {
; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x3df00000
; GFX7-GI-NEXT: v_mov_b32_e32 v8, 0
; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0xc1f00000
-; GFX7-GI-NEXT: v_cmp_nge_f64_e64 s[6:7], s[16:17], 0
-; GFX7-GI-NEXT: v_cmp_nge_f64_e64 s[8:9], s[18:19], 0
+; GFX7-GI-NEXT: v_cmp_nge_f64_e64 s[4:5], s[16:17], 0
; GFX7-GI-NEXT: v_mul_f64 v[6:7], v[0:1], v[4:5]
; GFX7-GI-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
; GFX7-GI-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
; GFX7-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-GI-NEXT: v_fma_f64 v[0:1], v[6:7], v[8:9], v[0:1]
; GFX7-GI-NEXT: v_fma_f64 v[2:3], v[4:5], v[8:9], v[2:3]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v4, v[4:5]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v8, v[0:1]
-; GFX7-GI-NEXT: v_mov_b32_e32 v0, -1
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x43efffff
-; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[0:1]
-; GFX7-GI-NEXT: v_cmp_gt_f64_e64 s[4:5], s[18:19], v[0:1]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v6, v[6:7]
+; GFX7-GI-NEXT: v_mov_b32_e32 v8, -1
+; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0x43efffff
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[16:17], v[8:9]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v1, v[4:5]
; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
-; GFX7-GI-NEXT: v_cvt_u32_f64_e32 v1, v[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v8, 0, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s[8:9]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
-; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, -1, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v6, 0, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX7-GI-NEXT: v_cmp_nge_f64_e64 s[4:5], s[18:19], 0
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f64_e32 vcc, s[18:19], v[8:9]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v4, -1, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_unsigned_v2f64_v2i64:
@@ -2088,19 +2092,19 @@ define <2 x i64> @test_s_unsigned_v2f64_v2i64(<2 x double> inreg %f) {
; GFX9-NEXT: v_cmp_gt_f64_e64 s[4:5], s[18:19], v[8:9]
; GFX9-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
-; GFX9-NEXT: v_fma_f64 v[0:1], v[4:5], s[6:7], v[0:1]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v10, v[4:5]
+; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], s[6:7], v[0:1]
; GFX9-NEXT: v_fma_f64 v[2:3], v[6:7], s[6:7], v[2:3]
; GFX9-NEXT: v_cmp_nge_f64_e64 s[6:7], s[16:17], 0
-; GFX9-NEXT: v_cvt_u32_f64_e32 v10, v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, 0, s[6:7]
; GFX9-NEXT: v_cvt_u32_f64_e32 v11, v[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v11, 0, s[8:9]
-; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, -1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v11, 0, s[8:9]
+; GFX9-NEXT: v_cvt_u32_f64_e32 v0, v[4:5]
; GFX9-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, -1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, -1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, -1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2183,30 +2187,32 @@ define <2 x i64> @test_s_unsigned_v2f64_v2i64(<2 x double> inreg %f) {
; GFX12-GI-NEXT: v_trunc_f64_e32 v[0:1], s[0:1]
; GFX12-GI-NEXT: v_trunc_f64_e32 v[2:3], s[2:3]
; GFX12-GI-NEXT: v_cmp_nge_f64_e64 s4, s[0:1], 0
-; GFX12-GI-NEXT: v_cmp_nge_f64_e64 s5, s[2:3], 0
; GFX12-GI-NEXT: v_mul_f64_e32 v[4:5], 0x3df00000, v[0:1]
; GFX12-GI-NEXT: v_mul_f64_e32 v[6:7], 0x3df00000, v[2:3]
; GFX12-GI-NEXT: v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-GI-NEXT: v_floor_f64_e32 v[6:7], v[6:7]
; GFX12-GI-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[4:5], v[0:1]
; GFX12-GI-NEXT: v_fma_f64 v[2:3], 0xc1f00000, v[6:7], v[2:3]
-; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v8, v[0:1]
-; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
-; GFX12-GI-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, 0x43efffff
-; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v3, v[4:5]
-; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v4, v[6:7]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX12-GI-NEXT: v_cmp_gt_f64_e64 s0, s[2:3], v[0:1]
+; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v1, v[4:5]
+; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v4, v[2:3]
+; GFX12-GI-NEXT: v_cvt_u32_f64_e32 v5, v[6:7]
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v3, 0x43efffff
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[2:3]
; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v8, 0, s4
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s5
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v3, 0, s4
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v4, 0, s5
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s4
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s4
+; GFX12-GI-NEXT: v_cmp_nge_f64_e64 s4, s[2:3], 0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, s4
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0, s4
; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v5, -1, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, -1, s0
+; GFX12-GI-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v4, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v5, -1, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
index 00b18a86f17cf..8261b408acf4f 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
@@ -672,12 +672,12 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
; VI-SDAG-NEXT: v_readfirstlane_b32 s4, v1
; VI-SDAG-NEXT: s_and_b32 s5, s4, 0x1ff
-; VI-SDAG-NEXT: v_or_b32_e32 v0, s5, v0
; VI-SDAG-NEXT: s_lshr_b32 s7, s4, 8
; VI-SDAG-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-SDAG-NEXT: v_or_b32_e32 v0, s5, v0
; VI-SDAG-NEXT: s_and_b32 s5, s7, 0xffe
; VI-SDAG-NEXT: s_sub_i32 s7, 0x3f1, s8
+; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-SDAG-NEXT: v_med3_i32 v1, s7, 0, 13
; VI-SDAG-NEXT: v_readfirstlane_b32 s7, v0
@@ -785,12 +785,12 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-SDAG-NEXT: s_and_b32 s6, s5, 0x1ff
-; GFX9-SDAG-NEXT: v_or_b32_e32 v0, s6, v0
; GFX9-SDAG-NEXT: s_lshr_b32 s7, s5, 8
; GFX9-SDAG-NEXT: s_bfe_u32 s8, s5, 0xb0014
-; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_or_b32_e32 v0, s6, v0
; GFX9-SDAG-NEXT: s_and_b32 s6, s7, 0xffe
; GFX9-SDAG-NEXT: s_sub_i32 s7, 0x3f1, s8
+; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-SDAG-NEXT: v_med3_i32 v1, s7, 0, 13
; GFX9-SDAG-NEXT: v_readfirstlane_b32 s7, v0
@@ -898,17 +898,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX950-SDAG-NEXT: v_readfirstlane_b32 s5, v1
; GFX950-SDAG-NEXT: s_and_b32 s6, s5, 0x1ff
-; GFX950-SDAG-NEXT: v_or_b32_e32 v0, s6, v0
; GFX950-SDAG-NEXT: s_lshr_b32 s7, s5, 8
; GFX950-SDAG-NEXT: s_bfe_u32 s8, s5, 0xb0014
-; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SDAG-NEXT: v_or_b32_e32 v0, s6, v0
; GFX950-SDAG-NEXT: s_and_b32 s6, s7, 0xffe
; GFX950-SDAG-NEXT: s_sub_i32 s7, 0x3f1, s8
-; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-SDAG-NEXT: v_med3_i32 v1, s7, 0, 13
+; GFX950-SDAG-NEXT: s_nop 0
+; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SDAG-NEXT: v_readfirstlane_b32 s9, v1
; GFX950-SDAG-NEXT: v_readfirstlane_b32 s7, v0
; GFX950-SDAG-NEXT: s_or_b32 s6, s6, s7
-; GFX950-SDAG-NEXT: v_readfirstlane_b32 s9, v1
; GFX950-SDAG-NEXT: s_or_b32 s7, s6, 0x1000
; GFX950-SDAG-NEXT: s_lshr_b32 s10, s7, s9
; GFX950-SDAG-NEXT: s_lshl_b32 s9, s10, s9
@@ -1015,11 +1016,11 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-SDAG-TRUE16-NEXT: s_sub_i32 s4, 0x3f1, s3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s4, s5, s4
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -1082,11 +1083,11 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-SDAG-FAKE16-NEXT: s_sub_i32 s4, 0x3f1, s3
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s4, s5, s4
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -1266,11 +1267,11 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-SDAG-TRUE16-NEXT: s_sub_co_i32 s4, 0x3f1, s3
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s4, s5, s4
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -1334,11 +1335,11 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-SDAG-FAKE16-NEXT: s_sub_co_i32 s4, 0x3f1, s3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1250-SDAG-FAKE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX1250-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_med3_i32 v1, s4, 0, 13
; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s4, s5, s4
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -2315,12 +2316,12 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; VI-SDAG-NEXT: v_readfirstlane_b32 s4, v3
; VI-SDAG-NEXT: s_and_b32 s7, s4, 0x1ff
; VI-SDAG-NEXT: v_readfirstlane_b32 s5, v1
-; VI-SDAG-NEXT: v_or_b32_e32 v1, s7, v2
; VI-SDAG-NEXT: s_lshr_b32 s8, s4, 8
; VI-SDAG-NEXT: s_bfe_u32 s9, s4, 0xb0014
-; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; VI-SDAG-NEXT: v_or_b32_e32 v1, s7, v2
; VI-SDAG-NEXT: s_and_b32 s7, s8, 0xffe
; VI-SDAG-NEXT: s_sub_i32 s8, 0x3f1, s9
+; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; VI-SDAG-NEXT: v_med3_i32 v2, s8, 0, 13
; VI-SDAG-NEXT: v_readfirstlane_b32 s8, v1
@@ -2352,12 +2353,12 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; VI-SDAG-NEXT: s_cmpk_eq_i32 s9, 0x40f
; VI-SDAG-NEXT: s_cselect_b32 s7, s7, s8
; VI-SDAG-NEXT: s_and_b32 s8, s5, 0x1ff
-; VI-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
; VI-SDAG-NEXT: s_lshr_b32 s4, s4, 16
-; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
; VI-SDAG-NEXT: s_lshr_b32 s9, s5, 8
; VI-SDAG-NEXT: s_bfe_u32 s10, s5, 0xb0014
; VI-SDAG-NEXT: s_and_b32 s4, s4, 0x8000
+; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-SDAG-NEXT: s_and_b32 s8, s9, 0xffe
; VI-SDAG-NEXT: s_sub_i32 s9, 0x3f1, s10
@@ -2517,12 +2518,12 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX9-SDAG-NEXT: v_readfirstlane_b32 s5, v3
; GFX9-SDAG-NEXT: s_and_b32 s7, s5, 0x1ff
; GFX9-SDAG-NEXT: v_readfirstlane_b32 s6, v1
-; GFX9-SDAG-NEXT: v_or_b32_e32 v1, s7, v2
; GFX9-SDAG-NEXT: s_lshr_b32 s8, s5, 8
; GFX9-SDAG-NEXT: s_bfe_u32 s9, s5, 0xb0014
-; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX9-SDAG-NEXT: v_or_b32_e32 v1, s7, v2
; GFX9-SDAG-NEXT: s_and_b32 s7, s8, 0xffe
; GFX9-SDAG-NEXT: s_sub_i32 s8, 0x3f1, s9
+; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-SDAG-NEXT: v_med3_i32 v2, s8, 0, 13
; GFX9-SDAG-NEXT: v_readfirstlane_b32 s8, v1
@@ -2554,12 +2555,12 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX9-SDAG-NEXT: s_cmpk_eq_i32 s9, 0x40f
; GFX9-SDAG-NEXT: s_cselect_b32 s7, s7, s8
; GFX9-SDAG-NEXT: s_and_b32 s8, s6, 0x1ff
-; GFX9-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
; GFX9-SDAG-NEXT: s_lshr_b32 s5, s5, 16
-; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
; GFX9-SDAG-NEXT: s_lshr_b32 s9, s6, 8
; GFX9-SDAG-NEXT: s_bfe_u32 s10, s6, 0xb0014
; GFX9-SDAG-NEXT: s_and_b32 s5, s5, 0x8000
+; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-SDAG-NEXT: s_and_b32 s8, s9, 0xffe
; GFX9-SDAG-NEXT: s_sub_i32 s9, 0x3f1, s10
@@ -2714,17 +2715,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX950-SDAG-NEXT: v_readfirstlane_b32 s5, v3
; GFX950-SDAG-NEXT: s_and_b32 s7, s5, 0x1ff
; GFX950-SDAG-NEXT: v_readfirstlane_b32 s6, v1
-; GFX950-SDAG-NEXT: v_or_b32_e32 v1, s7, v2
; GFX950-SDAG-NEXT: s_lshr_b32 s8, s5, 8
; GFX950-SDAG-NEXT: s_bfe_u32 s9, s5, 0xb0014
-; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SDAG-NEXT: v_or_b32_e32 v1, s7, v2
; GFX950-SDAG-NEXT: s_and_b32 s7, s8, 0xffe
; GFX950-SDAG-NEXT: s_sub_i32 s8, 0x3f1, s9
-; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; GFX950-SDAG-NEXT: v_med3_i32 v2, s8, 0, 13
+; GFX950-SDAG-NEXT: s_nop 0
+; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SDAG-NEXT: v_readfirstlane_b32 s10, v2
; GFX950-SDAG-NEXT: v_readfirstlane_b32 s8, v1
; GFX950-SDAG-NEXT: s_or_b32 s7, s7, s8
-; GFX950-SDAG-NEXT: v_readfirstlane_b32 s10, v2
; GFX950-SDAG-NEXT: s_or_b32 s8, s7, 0x1000
; GFX950-SDAG-NEXT: s_lshr_b32 s11, s8, s10
; GFX950-SDAG-NEXT: s_lshl_b32 s10, s11, s10
@@ -2751,15 +2753,15 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX950-SDAG-NEXT: s_cmpk_eq_i32 s9, 0x40f
; GFX950-SDAG-NEXT: s_cselect_b32 s7, s7, s8
; GFX950-SDAG-NEXT: s_and_b32 s8, s6, 0x1ff
-; GFX950-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
; GFX950-SDAG-NEXT: s_lshr_b32 s5, s5, 16
-; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
; GFX950-SDAG-NEXT: s_lshr_b32 s9, s6, 8
; GFX950-SDAG-NEXT: s_bfe_u32 s10, s6, 0xb0014
; GFX950-SDAG-NEXT: s_and_b32 s5, s5, 0x8000
-; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-SDAG-NEXT: s_and_b32 s8, s9, 0xffe
; GFX950-SDAG-NEXT: s_sub_i32 s9, 0x3f1, s10
+; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-SDAG-NEXT: s_or_b32 s5, s5, s7
; GFX950-SDAG-NEXT: v_readfirstlane_b32 s7, v0
; GFX950-SDAG-NEXT: v_med3_i32 v1, s9, 0, 13
@@ -2914,11 +2916,11 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-TRUE16-NEXT: s_sub_i32 s4, 0x3f1, s3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s4, s5, s4
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -2959,14 +2961,14 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-TRUE16-NEXT: s_sub_i32 s9, 0x3f1, s5
; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
; GFX11-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, s9, 0, 13
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s2, s2, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s2, s2, s3
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s11, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s11, v1
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s9, s10, s9
; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s10, s9, 0x1000
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -3030,11 +3032,11 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-FAKE16-NEXT: s_sub_i32 s4, 0x3f1, s3
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s4, v2
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s4, s5, s4
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -3075,14 +3077,14 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-FAKE16-NEXT: s_sub_i32 s9, 0x3f1, s5
; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s2, s2, 16
; GFX11-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v1, s9, 0, 13
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 s2, s2, 0x8000
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s2, s2, s3
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s11, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s11, v1
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s9, s10, s9
; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s10, s9, 0x1000
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -3357,11 +3359,11 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-TRUE16-NEXT: s_sub_co_i32 s4, 0x3f1, s3
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s4, s5, s4
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -3402,14 +3404,14 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-TRUE16-NEXT: s_sub_co_i32 s9, 0x3f1, s5
; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
; GFX1250-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v1, s9, 0, 13
; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s2, s2, 0x8000
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s11, v1
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s11, v1
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s9, s10, s9
; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s10, s9, 0x1000
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -3474,11 +3476,11 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-FAKE16-NEXT: s_sub_co_i32 s4, 0x3f1, s3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX1250-SDAG-FAKE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX1250-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_med3_i32 v3, s4, 0, 13
; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s4, s5, s4
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s5, s4, 0x1000
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -3519,14 +3521,14 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-FAKE16-NEXT: s_sub_co_i32 s9, 0x3f1, s5
; GFX1250-SDAG-FAKE16-NEXT: s_lshr_b32 s2, s2, 16
; GFX1250-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT: v_med3_i32 v1, s9, 0, 13
; GFX1250-SDAG-FAKE16-NEXT: s_and_b32 s2, s2, 0x8000
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s11, v1
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_readfirstlane_b32 s11, v1
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s9, s10, s9
; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s10, s9, 0x1000
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
index e8025e6c45cf0..ed2f6ddc7b7d4 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
@@ -384,18 +384,18 @@ define <2 x half> @v_test_cvt_v2f64_v2f16(<2 x double> %src) {
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, 0x1ff
-; GFX950-GISEL-NEXT: v_and_or_b32 v0, v1, v7, v0
; GFX950-GISEL-NEXT: v_bfe_u32 v4, v1, 20, 11
-; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-GISEL-NEXT: v_and_or_b32 v0, v1, v7, v0
; GFX950-GISEL-NEXT: v_add_u32_e32 v4, 0xfffffc10, v4
; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, 0xffe
+; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-GISEL-NEXT: v_sub_u32_e32 v10, 1, v4
+; GFX950-GISEL-NEXT: v_med3_i32 v10, v10, 0, 13
; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-GISEL-NEXT: v_and_or_b32 v0, v5, v6, v0
-; GFX950-GISEL-NEXT: v_sub_u32_e32 v10, 1, v4
; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-GISEL-NEXT: v_lshl_or_b32 v9, v4, 12, v0
-; GFX950-GISEL-NEXT: v_med3_i32 v10, v10, 0, 13
; GFX950-GISEL-NEXT: v_or_b32_e32 v0, 0x1000, v0
; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v11, v10, v0
; GFX950-GISEL-NEXT: v_lshlrev_b32_e32 v10, v10, v11
@@ -426,15 +426,15 @@ define <2 x half> @v_test_cvt_v2f64_v2f16(<2 x double> %src) {
; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX950-GISEL-NEXT: v_and_or_b32 v0, v1, v4, v0
; GFX950-GISEL-NEXT: v_bfe_u32 v1, v3, 20, 11
-; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-GISEL-NEXT: v_add_u32_e32 v1, 0xfffffc10, v1
; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
+; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-GISEL-NEXT: v_sub_u32_e32 v7, 1, v1
+; GFX950-GISEL-NEXT: v_med3_i32 v7, v7, 0, 13
; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX950-GISEL-NEXT: v_and_or_b32 v2, v5, v6, v2
-; GFX950-GISEL-NEXT: v_sub_u32_e32 v7, 1, v1
; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-GISEL-NEXT: v_lshl_or_b32 v6, v1, 12, v2
-; GFX950-GISEL-NEXT: v_med3_i32 v7, v7, 0, 13
; GFX950-GISEL-NEXT: v_or_b32_e32 v2, 0x1000, v2
; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v10, v7, v2
; GFX950-GISEL-NEXT: v_lshlrev_b32_e32 v7, v7, v10
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index 17c93482564f8..cbe53d1dc157f 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -148,14 +148,14 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX6-NEXT: v_cndmask_b32_e32 v8, v8, v2, vcc
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_mov_b32_e32 v10, 0x204
+; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v0, v10
-; GFX6-NEXT: s_mov_b32 s6, 0
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v9, 0, vcc
-; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v9, 0, vcc
+; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
; GFX6-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
; GFX6-NEXT: v_floor_f32_e32 v6, v1
; GFX6-NEXT: buffer_store_dword v7, v[3:4], s[4:7], 0 addr64 offset:8
@@ -167,19 +167,19 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v10, 0x204
-; GFX7-NEXT: v_fract_f32_e32 v8, v0
-; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v0, v10
; GFX7-NEXT: s_mov_b32 s6, 0
-; GFX7-NEXT: v_floor_f32_e32 v5, v0
+; GFX7-NEXT: v_fract_f32_e32 v8, v0
; GFX7-NEXT: v_fract_f32_e32 v9, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
+; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v0, v10
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b32 s4, s6
; GFX7-NEXT: s_mov_b32 s5, s6
; GFX7-NEXT: v_floor_f32_e32 v7, v2
; GFX7-NEXT: v_floor_f32_e32 v6, v1
+; GFX7-NEXT: v_floor_f32_e32 v5, v0
; GFX7-NEXT: v_fract_f32_e32 v1, v1
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
; GFX7-NEXT: v_cndmask_b32_e64 v2, v9, 0, vcc
; GFX7-NEXT: buffer_store_dwordx3 v[5:7], v[3:4], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -190,14 +190,14 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v10, 0x204
; GFX8-NEXT: v_fract_f32_e32 v8, v0
-; GFX8-NEXT: v_cmp_class_f32_e32 vcc, v0, v10
-; GFX8-NEXT: v_floor_f32_e32 v5, v0
; GFX8-NEXT: v_fract_f32_e32 v9, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
+; GFX8-NEXT: v_cmp_class_f32_e32 vcc, v0, v10
; GFX8-NEXT: v_floor_f32_e32 v7, v2
; GFX8-NEXT: v_floor_f32_e32 v6, v1
+; GFX8-NEXT: v_floor_f32_e32 v5, v0
; GFX8-NEXT: v_fract_f32_e32 v1, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
; GFX8-NEXT: v_cndmask_b32_e64 v2, v9, 0, vcc
; GFX8-NEXT: global_store_dwordx3 v[3:4], v[5:7], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -207,16 +207,17 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v8, v0
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
-; GFX11-NEXT: v_floor_f32_e32 v5, v0
; GFX11-NEXT: v_fract_f32_e32 v9, v2
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
; GFX11-NEXT: v_floor_f32_e32 v7, v2
; GFX11-NEXT: v_floor_f32_e32 v6, v1
+; GFX11-NEXT: v_floor_f32_e32 v5, v0
+; GFX11-NEXT: v_fract_f32_e32 v1, v1
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, s0
; GFX11-NEXT: v_cmp_class_f32_e64 s0, v2, 0x204
-; GFX11-NEXT: v_fract_f32_e32 v1, v1
-; GFX11-NEXT: global_store_b96 v[3:4], v[5:7], off
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v2, v9, 0, s0
+; GFX11-NEXT: global_store_b96 v[3:4], v[5:7], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: safe_math_fract_v3f32:
@@ -227,18 +228,19 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fract_f32_e32 v8, v0
-; GFX12-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
-; GFX12-NEXT: v_floor_f32_e32 v5, v0
; GFX12-NEXT: v_fract_f32_e32 v9, v2
+; GFX12-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
; GFX12-NEXT: v_floor_f32_e32 v7, v2
; GFX12-NEXT: v_floor_f32_e32 v6, v1
+; GFX12-NEXT: v_floor_f32_e32 v5, v0
+; GFX12-NEXT: v_fract_f32_e32 v1, v1
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, v8, 0, s0
; GFX12-NEXT: v_cmp_class_f32_e64 s0, v2, 0x204
-; GFX12-NEXT: v_fract_f32_e32 v1, v1
-; GFX12-NEXT: global_store_b96 v[3:4], v[5:7], off
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cndmask_b32_e64 v2, v9, 0, s0
+; GFX12-NEXT: global_store_b96 v[3:4], v[5:7], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX6-IR-LABEL: define <3 x float> @safe_math_fract_v3f32(
; GFX6-IR-SAME: <3 x float> [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0]] {
@@ -306,14 +308,14 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_mov_b32_e32 v8, 0x204
+; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v0, v8
-; GFX6-NEXT: s_mov_b32 s6, 0
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
-; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX6-NEXT: v_cndmask_b32_e64 v1, v7, 0, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
@@ -330,14 +332,14 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc
; GFX7-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX7-NEXT: v_mov_b32_e32 v8, 0x204
+; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v0, v8
-; GFX7-NEXT: s_mov_b32 s6, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b32 s4, s6
; GFX7-NEXT: s_mov_b32 s5, s6
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX7-NEXT: v_cndmask_b32_e64 v1, v7, 0, vcc
; GFX7-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -2534,14 +2536,14 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_mov_b32_e32 v8, 0x204
+; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v0, v8
-; GFX6-NEXT: s_mov_b32 s6, 0
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v7, 0, vcc
-; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v7, 0, vcc
+; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX6-NEXT: v_cndmask_b32_e64 v1, v6, 0, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
@@ -2551,17 +2553,17 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v8, 0x204
-; GFX7-NEXT: v_fract_f32_e32 v6, v0
-; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v0, v8
; GFX7-NEXT: s_mov_b32 s6, 0
-; GFX7-NEXT: v_floor_f32_e32 v4, v0
+; GFX7-NEXT: v_fract_f32_e32 v6, v0
; GFX7-NEXT: v_fract_f32_e32 v7, v1
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
+; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v0, v8
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b32 s4, s6
; GFX7-NEXT: s_mov_b32 s5, s6
; GFX7-NEXT: v_floor_f32_e32 v5, v1
+; GFX7-NEXT: v_floor_f32_e32 v4, v0
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
; GFX7-NEXT: v_cndmask_b32_e64 v1, v7, 0, vcc
; GFX7-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -2572,12 +2574,12 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v8, 0x204
; GFX8-NEXT: v_fract_f32_e32 v6, v0
+; GFX8-NEXT: v_fract_f32_e32 v7, v1
; GFX8-NEXT: v_cmp_class_f32_e32 vcc, v0, v8
+; GFX8-NEXT: v_floor_f32_e32 v5, v1
; GFX8-NEXT: v_floor_f32_e32 v4, v0
-; GFX8-NEXT: v_fract_f32_e32 v7, v1
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX8-NEXT: v_cmp_class_f32_e32 vcc, v1, v8
-; GFX8-NEXT: v_floor_f32_e32 v5, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, 0, vcc
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[4:5], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -2587,15 +2589,15 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v6, v0
-; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
; GFX11-NEXT: v_fract_f32_e32 v7, v1
-; GFX11-NEXT: v_floor_f32_e32 v4, v0
+; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
; GFX11-NEXT: v_floor_f32_e32 v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_floor_f32_e32 v4, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0
; GFX11-NEXT: v_cmp_class_f32_e64 s0, v1, 0x204
-; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX11-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0
+; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: safe_math_fract_v2f32:
@@ -2606,16 +2608,17 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fract_f32_e32 v6, v0
-; GFX12-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
; GFX12-NEXT: v_fract_f32_e32 v7, v1
-; GFX12-NEXT: v_floor_f32_e32 v4, v0
+; GFX12-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204
; GFX12-NEXT: v_floor_f32_e32 v5, v1
+; GFX12-NEXT: v_floor_f32_e32 v4, v0
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0
; GFX12-NEXT: v_cmp_class_f32_e64 s0, v1, 0x204
-; GFX12-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0
+; GFX12-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%floor = tail call <2 x float> @llvm.floor.v2f32(<2 x float> %x)
@@ -2690,10 +2693,10 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX7-LABEL: safe_math_fract_f64:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_mov_b32 s4, 0
-; GFX7-NEXT: s_mov_b32 s5, 0x7ff00000
+; GFX7-NEXT: s_mov_b32 s8, 0
+; GFX7-NEXT: s_mov_b32 s9, 0x7ff00000
; GFX7-NEXT: v_fract_f64_e32 v[4:5], v[0:1]
-; GFX7-NEXT: v_cmp_neq_f64_e64 vcc, |v[0:1]|, s[4:5]
+; GFX7-NEXT: v_cmp_neq_f64_e64 vcc, |v[0:1]|, s[8:9]
; GFX7-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000
@@ -3068,13 +3071,13 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX8-LABEL: safe_math_fract_v2f16:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s6, 0x204
; GFX8-NEXT: v_floor_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_floor_f16_e32 v4, v0
-; GFX8-NEXT: v_fract_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, s6 src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: s_movk_i32 s6, 0x204
; GFX8-NEXT: v_pack_b32_f16 v3, v4, v3
; GFX8-NEXT: v_fract_f16_e32 v4, v0
+; GFX8-NEXT: v_fract_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, s6 src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5]
; GFX8-NEXT: v_cmp_class_f16_e64 s[4:5], v0, s6
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
@@ -3110,11 +3113,12 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX11-FAKE16-NEXT: v_floor_f16_e32 v7, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v4, 0, s0
; GFX11-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_pack_b32_f16 v4, v5, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0
-; GFX11-FAKE16-NEXT: global_store_b32 v[1:2], v4, off
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v4, v5, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v3
+; GFX11-FAKE16-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: safe_math_fract_v2f16:
@@ -3153,12 +3157,12 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v4, 0, s0
; GFX12-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_pack_b32_f16 v4, v5, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0
-; GFX12-FAKE16-NEXT: global_store_b32 v[1:2], v4, off
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v4, v5, v7
; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v3
+; GFX12-FAKE16-NEXT: global_store_b32 v[1:2], v4, off
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%floor = tail call <2 x half> @llvm.floor.v2f16(<2 x half> %x)
@@ -3232,16 +3236,16 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX6-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc
; GFX6-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
; GFX6-NEXT: v_mov_b32_e32 v14, 0x204
+; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v13, v13, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
; GFX6-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v14
-; GFX6-NEXT: s_mov_b32 s6, 0
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v13, 0, vcc
-; GFX6-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v14
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v13, 0, vcc
+; GFX6-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v14
; GFX6-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v3, v11, 0, vcc
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[4:7], 0 addr64
@@ -3251,39 +3255,39 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX7-LABEL: safe_math_fract_v2f64:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v6, 0x204
; GFX7-NEXT: v_fract_f64_e32 v[10:11], v[0:1]
-; GFX7-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v6
; GFX7-NEXT: v_fract_f64_e32 v[12:13], v[2:3]
-; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v6
; GFX7-NEXT: v_floor_f64_e32 v[8:9], v[2:3]
; GFX7-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s8, s10
-; GFX7-NEXT: s_mov_b32 s9, s10
+; GFX7-NEXT: v_mov_b32_e32 v14, 0x204
+; GFX7-NEXT: s_mov_b32 s6, 0
+; GFX7-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v14
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b32 s4, s6
+; GFX7-NEXT: s_mov_b32 s5, s6
; GFX7-NEXT: v_cndmask_b32_e64 v0, v10, 0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v1, v11, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v12, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v13, 0, s[4:5]
-; GFX7-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[8:11], 0 addr64
+; GFX7-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v14
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v12, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v13, 0, vcc
+; GFX7-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: safe_math_fract_v2f64:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v6, 0x204
; GFX8-NEXT: v_fract_f64_e32 v[10:11], v[0:1]
-; GFX8-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v6
; GFX8-NEXT: v_fract_f64_e32 v[12:13], v[2:3]
-; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v6
; GFX8-NEXT: v_floor_f64_e32 v[8:9], v[2:3]
; GFX8-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v14, 0x204
+; GFX8-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v14
; GFX8-NEXT: v_cndmask_b32_e64 v0, v10, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v11, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v12, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v13, 0, s[4:5]
+; GFX8-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v14
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v12, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v13, 0, vcc
; GFX8-NEXT: global_store_dwordx4 v[4:5], v[6:9], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -3292,15 +3296,16 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f64_e32 v[10:11], v[0:1]
-; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[0:1], 0x204
; GFX11-NEXT: v_fract_f64_e32 v[12:13], v[2:3]
-; GFX11-NEXT: v_cmp_class_f64_e64 s1, v[2:3], 0x204
; GFX11-NEXT: v_floor_f64_e32 v[8:9], v[2:3]
; GFX11-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
+; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[0:1], 0x204
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v10, 0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v11, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v12, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v13, 0, s1
+; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 0x204
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v12, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v13, 0, s0
; GFX11-NEXT: global_store_b128 v[4:5], v[6:9], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -3312,16 +3317,18 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fract_f64_e32 v[10:11], v[0:1]
-; GFX12-NEXT: v_cmp_class_f64_e64 s0, v[0:1], 0x204
; GFX12-NEXT: v_fract_f64_e32 v[12:13], v[2:3]
-; GFX12-NEXT: v_cmp_class_f64_e64 s1, v[2:3], 0x204
; GFX12-NEXT: v_floor_f64_e32 v[8:9], v[2:3]
; GFX12-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
+; GFX12-NEXT: v_cmp_class_f64_e64 s0, v[0:1], 0x204
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cndmask_b32_e64 v0, v10, 0, s0
; GFX12-NEXT: v_cndmask_b32_e64 v1, v11, 0, s0
-; GFX12-NEXT: v_cndmask_b32_e64 v2, v12, 0, s1
-; GFX12-NEXT: v_cndmask_b32_e64 v3, v13, 0, s1
+; GFX12-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 0x204
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: v_cndmask_b32_e64 v2, v12, 0, s0
+; GFX12-NEXT: v_cndmask_b32_e64 v3, v13, 0, s0
; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4440,14 +4447,14 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_floor_f32_e32 v3, v0
-; GFX6-NEXT: s_mov_b32 s8, 0x7f800000
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_sub_f32_e32 v3, v0, v3
-; GFX6-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s8
+; GFX6-NEXT: s_mov_b32 s8, 0x7f800000
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s6
; GFX6-NEXT: v_min_f32_e32 v3, 0x3f7fffff, v3
+; GFX6-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s8
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX6-NEXT: buffer_store_byte v4, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
@@ -4459,13 +4466,13 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; GFX7-LABEL: safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_mov_b32 s8, 0x7f800000
; GFX7-NEXT: s_mov_b32 s6, 0
-; GFX7-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s8
+; GFX7-NEXT: s_mov_b32 s8, 0x7f800000
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b32 s4, s6
; GFX7-NEXT: s_mov_b32 s5, s6
; GFX7-NEXT: v_fract_f32_e32 v3, v0
+; GFX7-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s8
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-NEXT: buffer_store_byte v0, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
@@ -4476,8 +4483,8 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX8-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX8-NEXT: v_fract_f32_e32 v3, v0
+; GFX8-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: global_store_byte v[1:2], v0, off
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/freeze.ll b/llvm/test/CodeGen/AMDGPU/freeze.ll
index 51559f9e213f0..51aa40d59ce00 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze.ll
@@ -16059,8 +16059,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX6-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-SDAG-NEXT: v_and_b32_e32 v0, 3, v0
@@ -16100,8 +16100,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 3, v0
@@ -16137,8 +16137,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX8-GFX803-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX8-GFX803-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX8-GFX803-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX8-GFX803-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-GFX803-SDAG-NEXT: v_lshlrev_b16_e32 v1, 1, v1
+; GFX8-GFX803-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-GFX803-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-GFX803-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GFX803-SDAG-NEXT: v_and_b32_e32 v0, 3, v0
@@ -16171,8 +16171,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX8-GFX900-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX8-GFX900-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX8-GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX8-GFX900-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-GFX900-SDAG-NEXT: v_lshlrev_b16_e32 v1, 1, v1
+; GFX8-GFX900-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-GFX900-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GFX900-SDAG-NEXT: v_and_b32_e32 v0, 3, v0
@@ -16206,8 +16206,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 3, v0
; GFX10-SDAG-NEXT: global_store_byte v[2:3], v0, off
@@ -16221,10 +16221,10 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT: v_lshlrev_b16 v1, 1, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-GISEL-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 3, v0
; GFX10-GISEL-NEXT: global_store_byte v[2:3], v0, off
@@ -16238,8 +16238,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 3
; GFX11-SDAG-TRUE16-NEXT: global_store_b8 v[2:3], v0, off
@@ -16253,8 +16253,8 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 3, v0
; GFX11-SDAG-FAKE16-NEXT: global_store_b8 v[2:3], v0, off
@@ -16268,10 +16268,10 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b16 v1, 1, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-GISEL-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 3, v0
; GFX11-GISEL-NEXT: global_store_b8 v[2:3], v0, off
@@ -16478,11 +16478,11 @@ define void @freeze_v3i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX10-SDAG-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 2, v4
; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 7, v0
@@ -16497,14 +16497,14 @@ define void @freeze_v3i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX10-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-GISEL-NEXT: v_lshlrev_b16 v1, 2, v4
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 7, v0
@@ -16519,12 +16519,12 @@ define void @freeze_v3i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.h, 2, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 7
; GFX11-SDAG-TRUE16-NEXT: global_store_b8 v[2:3], v0, off
@@ -16538,11 +16538,11 @@ define void @freeze_v3i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v1, 2, v4
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 7, v0
@@ -16557,14 +16557,14 @@ define void @freeze_v3i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_lshlrev_b16 v1, 2, v4
; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 7, v0
@@ -16593,8 +16593,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX6-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v4, 2, v4
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
@@ -16620,8 +16620,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX6-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX6-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX6-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
@@ -16652,8 +16652,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v4, 2, v4
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
@@ -16679,8 +16679,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
@@ -16707,8 +16707,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX8-GFX803-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-GFX803-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX8-GFX803-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX8-GFX803-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX8-GFX803-SDAG-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8-GFX803-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX8-GFX803-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-GFX803-SDAG-NEXT: v_lshlrev_b16_e32 v4, 2, v4
; GFX8-GFX803-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
@@ -16731,8 +16731,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX8-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
@@ -16759,8 +16759,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX8-GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-GFX900-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX8-GFX900-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX8-GFX900-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX8-GFX900-SDAG-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8-GFX900-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX8-GFX900-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-GFX900-SDAG-NEXT: v_lshlrev_b16_e32 v4, 2, v4
; GFX8-GFX900-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
@@ -16783,8 +16783,8 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
@@ -16808,13 +16808,13 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX10-SDAG-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX10-SDAG-NEXT: v_lshlrev_b16 v4, 2, v4
+; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 3, v1
@@ -16831,17 +16831,17 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX10-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
-; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-GISEL-NEXT: v_lshlrev_b16 v4, 2, v4
+; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 1, v5
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-GISEL-NEXT: v_lshlrev_b16 v1, 3, v1
@@ -16858,16 +16858,16 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.h, 2, v4.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.h, 2, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.h, 3, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 15
@@ -16882,13 +16882,13 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v4, 2, v4
+; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v1, 3, v1
@@ -16905,17 +16905,17 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
-; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-GISEL-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX11-GISEL-NEXT: v_lshlrev_b16 v4, 2, v4
+; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 1, v5
; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX11-GISEL-NEXT: v_lshlrev_b16 v1, 3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll b/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
index 342359c68fa93..6d00d4006d652 100644
--- a/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
@@ -126,8 +126,8 @@ define float @v_sqrt_f32_fneg(float %x) {
; GISEL-IEEE-LABEL: v_sqrt_f32_fneg:
; GISEL-IEEE: ; %bb.0:
; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-IEEE-NEXT: v_mul_f32_e64 v2, -v0, v2
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc
@@ -172,8 +172,8 @@ define float @v_sqrt_f32_fneg(float %x) {
; GISEL-DAZ-LABEL: v_sqrt_f32_fneg:
; GISEL-DAZ: ; %bb.0:
; GISEL-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-DAZ-NEXT: v_mul_f32_e64 v2, -v0, v2
; GISEL-DAZ-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
; GISEL-DAZ-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc
@@ -200,8 +200,8 @@ define float @v_sqrt_f32_fabs(float %x) {
; SDAG-IEEE-LABEL: v_sqrt_f32_fabs:
; SDAG-IEEE: ; %bb.0:
; SDAG-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-IEEE-NEXT: s_mov_b32 s4, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s5, 0x4f800000
+; SDAG-IEEE-NEXT: s_mov_b32 s4, 0xf800000
; SDAG-IEEE-NEXT: v_mul_f32_e64 v1, |v0|, s5
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
@@ -224,8 +224,8 @@ define float @v_sqrt_f32_fabs(float %x) {
; GISEL-IEEE-LABEL: v_sqrt_f32_fabs:
; GISEL-IEEE: ; %bb.0:
; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-IEEE-NEXT: v_mul_f32_e64 v2, |v0|, v2
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
@@ -248,8 +248,8 @@ define float @v_sqrt_f32_fabs(float %x) {
; SDAG-DAZ-LABEL: v_sqrt_f32_fabs:
; SDAG-DAZ: ; %bb.0:
; SDAG-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-DAZ-NEXT: s_mov_b32 s4, 0xf800000
; SDAG-DAZ-NEXT: s_mov_b32 s5, 0x4f800000
+; SDAG-DAZ-NEXT: s_mov_b32 s4, 0xf800000
; SDAG-DAZ-NEXT: v_mul_f32_e64 v1, |v0|, s5
; SDAG-DAZ-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; SDAG-DAZ-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
@@ -271,8 +271,8 @@ define float @v_sqrt_f32_fabs(float %x) {
; GISEL-DAZ-LABEL: v_sqrt_f32_fabs:
; GISEL-DAZ: ; %bb.0:
; GISEL-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-DAZ-NEXT: v_mul_f32_e64 v2, |v0|, v2
; GISEL-DAZ-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GISEL-DAZ-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
@@ -299,8 +299,8 @@ define float @v_sqrt_f32_fneg_fabs(float %x) {
; SDAG-IEEE-LABEL: v_sqrt_f32_fneg_fabs:
; SDAG-IEEE: ; %bb.0:
; SDAG-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x8f800000
; SDAG-IEEE-NEXT: s_mov_b32 s5, 0xcf800000
+; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x8f800000
; SDAG-IEEE-NEXT: v_mul_f32_e64 v1, |v0|, s5
; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v0, -|v0|, v1, vcc
@@ -323,8 +323,8 @@ define float @v_sqrt_f32_fneg_fabs(float %x) {
; GISEL-IEEE-LABEL: v_sqrt_f32_fneg_fabs:
; GISEL-IEEE: ; %bb.0:
; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-IEEE-NEXT: v_mul_f32_e64 v2, -|v0|, v2
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v0, -|v0|, v2, vcc
@@ -347,8 +347,8 @@ define float @v_sqrt_f32_fneg_fabs(float %x) {
; SDAG-DAZ-LABEL: v_sqrt_f32_fneg_fabs:
; SDAG-DAZ: ; %bb.0:
; SDAG-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-DAZ-NEXT: s_mov_b32 s4, 0x8f800000
; SDAG-DAZ-NEXT: s_mov_b32 s5, 0xcf800000
+; SDAG-DAZ-NEXT: s_mov_b32 s4, 0x8f800000
; SDAG-DAZ-NEXT: v_mul_f32_e64 v1, |v0|, s5
; SDAG-DAZ-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
; SDAG-DAZ-NEXT: v_cndmask_b32_e64 v0, -|v0|, v1, vcc
@@ -370,8 +370,8 @@ define float @v_sqrt_f32_fneg_fabs(float %x) {
; GISEL-DAZ-LABEL: v_sqrt_f32_fneg_fabs:
; GISEL-DAZ: ; %bb.0:
; GISEL-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x4f800000
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
; GISEL-DAZ-NEXT: v_mul_f32_e64 v2, -|v0|, v2
; GISEL-DAZ-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
; GISEL-DAZ-NEXT: v_cndmask_b32_e64 v0, -|v0|, v2, vcc
@@ -680,8 +680,8 @@ define float @v_sqrt_f32_nnan(float %x) {
define amdgpu_ps i32 @s_sqrt_f32(float inreg %x) {
; SDAG-IEEE-LABEL: s_sqrt_f32:
; SDAG-IEEE: ; %bb.0:
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, s0, v1
; SDAG-IEEE-NEXT: v_mov_b32_e32 v2, s0
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0
@@ -784,8 +784,8 @@ define amdgpu_ps i32 @s_sqrt_f32(float inreg %x) {
define amdgpu_ps i32 @s_sqrt_f32_ninf(float inreg %x) {
; SDAG-IEEE-LABEL: s_sqrt_f32_ninf:
; SDAG-IEEE: ; %bb.0:
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, s0, v1
; SDAG-IEEE-NEXT: v_mov_b32_e32 v2, s0
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0
@@ -2071,8 +2071,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2(<2 x float> %x) {
; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x800000
; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[4:5]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v0, v0
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2
@@ -2089,8 +2089,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2(<2 x float> %x) {
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x800000
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v3
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -2117,8 +2117,8 @@ define <2 x float> @v_sqrt_v2f32_ulp1_fabs(<2 x float> %x) {
; SDAG-IEEE-LABEL: v_sqrt_v2f32_ulp1_fabs:
; SDAG-IEEE: ; %bb.0:
; SDAG-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-IEEE-NEXT: s_mov_b32 s6, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s7, 0x4f800000
+; SDAG-IEEE-NEXT: s_mov_b32 s6, 0xf800000
; SDAG-IEEE-NEXT: v_mul_f32_e64 v2, |v0|, s7
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s6
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
@@ -2132,8 +2132,8 @@ define <2 x float> @v_sqrt_v2f32_ulp1_fabs(<2 x float> %x) {
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v2
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]
; SDAG-IEEE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2
-; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; SDAG-IEEE-NEXT: v_mul_f32_e64 v4, |v1|, s7
+; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s6
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v1, |v1|, v4, vcc
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v4, v1
@@ -2157,8 +2157,8 @@ define <2 x float> @v_sqrt_v2f32_ulp1_fabs(<2 x float> %x) {
; GISEL-IEEE-LABEL: v_sqrt_v2f32_ulp1_fabs:
; GISEL-IEEE: ; %bb.0:
; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, 0x4f800000
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0xf800000
; GISEL-IEEE-NEXT: v_mul_f32_e64 v4, |v0|, v3
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v0, |v0|, v4, vcc
@@ -2213,8 +2213,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_fabs(<2 x float> %x) {
; SDAG-IEEE-NEXT: s_mov_b32 s6, 0x800000
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[4:5]
-; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, s6
; SDAG-IEEE-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, s6
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[6:7]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v0, v0
; SDAG-IEEE-NEXT: v_ldexp_f32_e64 v1, |v1|, v2
@@ -2231,8 +2231,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_fabs(<2 x float> %x) {
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x800000
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v2
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[6:7]
; GISEL-IEEE-NEXT: v_ldexp_f32_e64 v0, |v0|, v3
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -2620,8 +2620,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_noncontractable_rcp(<2 x float> %x) {
; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x800000
; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 32, s[4:5]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v0, v0
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2
@@ -2653,8 +2653,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_noncontractable_rcp(<2 x float> %x) {
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x800000
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v3
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -2702,8 +2702,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_rcp(<2 x float> %x) {
; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x800000
; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, vcc
-; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, s[4:5]
; SDAG-IEEE-NEXT: v_rsq_f32_e32 v0, v0
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2
@@ -2720,8 +2720,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_rcp(<2 x float> %x) {
; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x800000
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, 0, 24, vcc
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v3
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, s[4:5]
; GISEL-IEEE-NEXT: v_rsq_f32_e32 v0, v0
; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2
@@ -2750,8 +2750,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_fdiv(<2 x float> %x, <2 x flo
; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x800000
; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
-; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v4
+; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v0, v0
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v4
@@ -2793,8 +2793,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_fdiv(<2 x float> %x, <2 x flo
; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x800000
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v5
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v4, 5, v4
@@ -2885,8 +2885,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_fdiv_arcp(<2 x float> %x, <2
; SDAG-IEEE-NEXT: s_mov_b32 s4, 0x800000
; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
-; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v4
+; SDAG-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 32, s[4:5]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v0, v0
; SDAG-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v4
@@ -2920,8 +2920,8 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_fdiv_arcp(<2 x float> %x, <2
; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x800000
; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v5
; GISEL-IEEE-NEXT: v_lshlrev_b32_e32 v4, 5, v4
@@ -3944,8 +3944,8 @@ define amdgpu_kernel void @elim_redun_check_neg0(ptr addrspace(1) %out, float %i
; SDAG-IEEE: ; %bb.0: ; %entry
; SDAG-IEEE-NEXT: s_load_dword s0, s[4:5], 0xb
; SDAG-IEEE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s7, 0xf000
; SDAG-IEEE-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, s0, v1
@@ -4079,8 +4079,8 @@ define amdgpu_kernel void @elim_redun_check_pos0(ptr addrspace(1) %out, float %i
; SDAG-IEEE: ; %bb.0: ; %entry
; SDAG-IEEE-NEXT: s_load_dword s0, s[4:5], 0xb
; SDAG-IEEE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s7, 0xf000
; SDAG-IEEE-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, s0, v1
@@ -4212,8 +4212,8 @@ define amdgpu_kernel void @elim_redun_check_ult(ptr addrspace(1) %out, float %in
; SDAG-IEEE: ; %bb.0: ; %entry
; SDAG-IEEE-NEXT: s_load_dword s0, s[4:5], 0xb
; SDAG-IEEE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s7, 0xf000
; SDAG-IEEE-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, s0, v1
@@ -4346,8 +4346,8 @@ define amdgpu_kernel void @elim_redun_check_v2(ptr addrspace(1) %out, <2 x float
; SDAG-IEEE-LABEL: elim_redun_check_v2:
; SDAG-IEEE: ; %bb.0: ; %entry
; SDAG-IEEE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s7, 0xf000
; SDAG-IEEE-NEXT: s_mov_b32 s6, -1
; SDAG-IEEE-NEXT: s_waitcnt lgkmcnt(0)
@@ -4368,8 +4368,8 @@ define amdgpu_kernel void @elim_redun_check_v2(ptr addrspace(1) %out, <2 x float
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v3
; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; SDAG-IEEE-NEXT: v_mul_f32_e32 v4, 0x37800000, v3
-; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; SDAG-IEEE-NEXT: v_mov_b32_e32 v5, s10
+; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], s10, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v0, v5, v1, s[0:1]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v5, v0
@@ -4550,8 +4550,8 @@ define amdgpu_kernel void @elim_redun_check_v2_ult(ptr addrspace(1) %out, <2 x f
; SDAG-IEEE-LABEL: elim_redun_check_v2_ult:
; SDAG-IEEE: ; %bb.0: ; %entry
; SDAG-IEEE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; SDAG-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; SDAG-IEEE-NEXT: s_mov_b32 s7, 0xf000
; SDAG-IEEE-NEXT: s_mov_b32 s6, -1
; SDAG-IEEE-NEXT: s_waitcnt lgkmcnt(0)
@@ -4572,8 +4572,8 @@ define amdgpu_kernel void @elim_redun_check_v2_ult(ptr addrspace(1) %out, <2 x f
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v3
; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; SDAG-IEEE-NEXT: v_mul_f32_e32 v4, 0x37800000, v3
-; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; SDAG-IEEE-NEXT: v_mov_b32_e32 v5, s10
+; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], s10, v0
; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v0, v5, v1, s[0:1]
; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v5, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll b/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
index a9e0ea0a003e7..dccfa7150b34b 100644
--- a/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
@@ -26,10 +26,10 @@ define double @v_sqrt_f64(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -54,10 +54,10 @@ define double @v_sqrt_f64(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -82,10 +82,10 @@ define double @v_sqrt_f64(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -110,10 +110,10 @@ define double @v_sqrt_f64(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -142,10 +142,10 @@ define double @v_sqrt_f64_fneg(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -170,10 +170,10 @@ define double @v_sqrt_f64_fneg(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -198,10 +198,10 @@ define double @v_sqrt_f64_fneg(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -226,10 +226,10 @@ define double @v_sqrt_f64_fneg(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -259,10 +259,10 @@ define double @v_sqrt_f64_fabs(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -287,10 +287,10 @@ define double @v_sqrt_f64_fabs(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -315,10 +315,10 @@ define double @v_sqrt_f64_fabs(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -343,10 +343,10 @@ define double @v_sqrt_f64_fabs(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -376,10 +376,10 @@ define double @v_sqrt_f64_fneg_fabs(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -404,10 +404,10 @@ define double @v_sqrt_f64_fneg_fabs(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -432,10 +432,10 @@ define double @v_sqrt_f64_fneg_fabs(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -460,10 +460,10 @@ define double @v_sqrt_f64_fneg_fabs(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -718,10 +718,10 @@ define double @v_sqrt_f64_nnan(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -746,10 +746,10 @@ define double @v_sqrt_f64_nnan(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -774,10 +774,10 @@ define double @v_sqrt_f64_nnan(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -802,10 +802,10 @@ define double @v_sqrt_f64_nnan(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -891,10 +891,10 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64(double inreg %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: v_readfirstlane_b32 s0, v0
@@ -920,10 +920,10 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64(double inreg %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
@@ -1067,9 +1067,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX6-SDAG-LABEL: s_sqrt_f64_afn:
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v6, 0x260
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v6
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v7, s1
; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
; GFX6-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 0.5
@@ -1077,9 +1074,12 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], -v[2:3], v[2:3], s[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, s0
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-SDAG-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-SDAG-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-SDAG-NEXT: ; return to shader part epilog
@@ -1087,9 +1087,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX8-SDAG-LABEL: s_sqrt_f64_afn:
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v6, 0x260
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v6
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v7, s1
; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
; GFX8-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 0.5
@@ -1097,9 +1094,12 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], -v[2:3], v[2:3], s[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-SDAG-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-SDAG-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-SDAG-NEXT: ; return to shader part epilog
@@ -1107,9 +1107,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX6-GISEL-LABEL: s_sqrt_f64_afn:
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v6, 0x260
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v6
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v7, s0
; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[0:1], 0.5
@@ -1117,9 +1114,12 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[0:1], s[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, s1
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-GISEL-NEXT: ; return to shader part epilog
@@ -1127,9 +1127,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX8-GISEL-LABEL: s_sqrt_f64_afn:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v6, 0x260
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v6
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v7, s0
; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[0:1], 0.5
@@ -1137,9 +1134,12 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn(double inreg %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[0:1], s[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog
@@ -1159,7 +1159,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
; GFX6-SDAG-NEXT: v_cmp_eq_f64_e64 vcc, s[0:1], 0
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v6, s1
; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
; GFX6-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 0.5
@@ -1167,9 +1166,10 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], -v[2:3], v[2:3], s[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-SDAG-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-SDAG-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-SDAG-NEXT: ; return to shader part epilog
@@ -1178,7 +1178,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
; GFX8-SDAG-NEXT: v_cmp_eq_f64_e64 vcc, s[0:1], 0
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v6, s1
; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
; GFX8-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 0.5
@@ -1186,9 +1185,10 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], -v[2:3], v[2:3], s[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-SDAG-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-SDAG-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-SDAG-NEXT: ; return to shader part epilog
@@ -1197,7 +1197,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
; GFX6-GISEL-NEXT: v_cmp_eq_f64_e64 vcc, s[0:1], 0
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v6, s0
; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[0:1], 0.5
@@ -1205,9 +1204,10 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[0:1], s[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-GISEL-NEXT: ; return to shader part epilog
@@ -1216,7 +1216,6 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
; GFX8-GISEL-NEXT: v_cmp_eq_f64_e64 vcc, s[0:1], 0
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v6, s0
; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[0:1], 0.5
@@ -1224,9 +1223,10 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_afn_nnan_ninf(double inreg %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[0:1], s[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog
@@ -1262,10 +1262,10 @@ define double @v_sqrt_f64_nsz(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1290,10 +1290,10 @@ define double @v_sqrt_f64_nsz(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1318,10 +1318,10 @@ define double @v_sqrt_f64_nsz(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1346,10 +1346,10 @@ define double @v_sqrt_f64_nsz(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1586,8 +1586,6 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -1595,6 +1593,8 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1603,8 +1603,6 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -1612,6 +1610,8 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1620,8 +1620,6 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -1629,6 +1627,8 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1637,8 +1637,6 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -1646,6 +1644,8 @@ define double @v_sqrt_f64_afn(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1658,8 +1658,6 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -1667,6 +1665,8 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1675,8 +1675,6 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -1684,6 +1682,8 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1692,8 +1692,6 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -1701,6 +1699,8 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1709,8 +1709,6 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -1718,6 +1716,8 @@ define double @v_sqrt_f64_afn_nsz(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1731,9 +1731,6 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v16, 0x260
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v16
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v16
; GFX6-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; GFX6-SDAG-NEXT: v_mul_f64 v[10:11], v[2:3], v[6:7]
@@ -1747,11 +1744,14 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_sqrt_v2f64_afn:
@@ -1759,9 +1759,6 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v16, 0x260
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v16
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v16
; GFX8-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; GFX8-SDAG-NEXT: v_mul_f64 v[10:11], v[2:3], v[6:7]
@@ -1775,11 +1772,14 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: v_sqrt_v2f64_afn:
@@ -1787,9 +1787,6 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v16, 0x260
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v16
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v16
; GFX6-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; GFX6-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
@@ -1803,11 +1800,14 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: v_sqrt_v2f64_afn:
@@ -1815,9 +1815,6 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v16, 0x260
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v16
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v16
; GFX8-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
@@ -1831,11 +1828,14 @@ define <2 x double> @v_sqrt_v2f64_afn(<2 x double> %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call afn <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
ret <2 x double> %result
@@ -1846,8 +1846,6 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -1855,6 +1853,8 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1863,8 +1863,6 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -1872,6 +1870,8 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1880,8 +1880,6 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -1889,6 +1887,8 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1897,8 +1897,6 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -1906,6 +1904,8 @@ define double @v_sqrt_f64_afn_nnan(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1993,10 +1993,10 @@ define double @v_sqrt_f64_fabs_afn_ninf(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], |v[0:1]|
-; GFX6-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX6-SDAG-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_sqrt_f64_fabs_afn_ninf:
@@ -2010,10 +2010,10 @@ define double @v_sqrt_f64_fabs_afn_ninf(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], |v[0:1]|
-; GFX8-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; GFX8-SDAG-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: v_sqrt_f64_fabs_afn_ninf:
@@ -2027,10 +2027,10 @@ define double @v_sqrt_f64_fabs_afn_ninf(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], |v[0:1]|
-; GFX6-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX6-GISEL-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: v_sqrt_f64_fabs_afn_ninf:
@@ -2044,10 +2044,10 @@ define double @v_sqrt_f64_fabs_afn_ninf(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], |v[0:1]|
-; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; GFX8-GISEL-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %x)
%result = call afn ninf double @llvm.sqrt.f64(double %fabs)
@@ -2129,7 +2129,6 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
; GFX6-SDAG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
-; GFX6-SDAG-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[2:3]
; GFX6-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; GFX6-SDAG-NEXT: v_mul_f64 v[10:11], v[2:3], v[6:7]
@@ -2146,8 +2145,9 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX6-SDAG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[2:3]
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_sqrt_v2f64_afn_nnan_ninf:
@@ -2156,7 +2156,6 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
; GFX8-SDAG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
-; GFX8-SDAG-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[2:3]
; GFX8-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; GFX8-SDAG-NEXT: v_mul_f64 v[10:11], v[2:3], v[6:7]
@@ -2173,8 +2172,9 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX8-SDAG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[2:3]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: v_sqrt_v2f64_afn_nnan_ninf:
@@ -2183,7 +2183,6 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
; GFX6-GISEL-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
-; GFX6-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[2:3]
; GFX6-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; GFX6-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
@@ -2200,8 +2199,9 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX6-GISEL-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[2:3]
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: v_sqrt_v2f64_afn_nnan_ninf:
@@ -2210,7 +2210,6 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
; GFX8-GISEL-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
-; GFX8-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[2:3]
; GFX8-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
@@ -2227,8 +2226,9 @@ define <2 x double> @v_sqrt_v2f64_afn_nnan_ninf(<2 x double> %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX8-GISEL-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[2:3]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call afn nnan ninf <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
ret <2 x double> %result
@@ -2323,10 +2323,10 @@ define double @v_sqrt_f64__enough_unsafe_attrs(double %x) #3 {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -2351,10 +2351,10 @@ define double @v_sqrt_f64__enough_unsafe_attrs(double %x) #3 {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -2379,10 +2379,10 @@ define double @v_sqrt_f64__enough_unsafe_attrs(double %x) #3 {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2407,10 +2407,10 @@ define double @v_sqrt_f64__enough_unsafe_attrs(double %x) #3 {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2439,10 +2439,10 @@ define double @v_sqrt_f64__unsafe_attr(double %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -2467,10 +2467,10 @@ define double @v_sqrt_f64__unsafe_attr(double %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -2495,10 +2495,10 @@ define double @v_sqrt_f64__unsafe_attr(double %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2523,10 +2523,10 @@ define double @v_sqrt_f64__unsafe_attr(double %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2541,44 +2541,44 @@ define <2 x double> @v_sqrt_v2f64(<2 x double> %x) {
; GFX6-SDAG-NEXT: s_mov_b32 s4, 0
; GFX6-SDAG-NEXT: s_brev_b32 s5, 8
; GFX6-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX6-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[2:3]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0x100
+; GFX6-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[2:3]
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; GFX6-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v5
; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; GFX6-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v5
; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX6-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
-; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
+; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX6-SDAG-NEXT: v_mul_f64 v[10:11], v[2:3], v[6:7]
; GFX6-SDAG-NEXT: v_mul_f64 v[6:7], v[6:7], 0.5
-; GFX6-SDAG-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 0.5
+; GFX6-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
+; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 0.5
-; GFX6-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
-; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; GFX6-SDAG-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 0.5
; GFX6-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
-; GFX6-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
+; GFX6-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
; GFX6-SDAG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
-; GFX6-SDAG-NEXT: v_fma_f64 v[8:9], v[12:13], v[4:5], v[8:9]
-; GFX6-SDAG-NEXT: v_fma_f64 v[10:11], v[14:15], v[6:7], v[10:11]
; GFX6-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
+; GFX6-SDAG-NEXT: v_fma_f64 v[10:11], v[14:15], v[6:7], v[10:11]
+; GFX6-SDAG-NEXT: v_fma_f64 v[8:9], v[12:13], v[4:5], v[8:9]
; GFX6-SDAG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
+; GFX6-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
+; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v9, 0x260
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; GFX6-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; GFX6-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX6-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_sqrt_v2f64:
@@ -2587,44 +2587,44 @@ define <2 x double> @v_sqrt_v2f64(<2 x double> %x) {
; GFX8-SDAG-NEXT: s_mov_b32 s4, 0
; GFX8-SDAG-NEXT: s_brev_b32 s5, 8
; GFX8-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX8-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[2:3]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0x100
+; GFX8-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; GFX8-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v5
; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; GFX8-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v5
; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX8-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
-; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
+; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX8-SDAG-NEXT: v_mul_f64 v[10:11], v[2:3], v[6:7]
; GFX8-SDAG-NEXT: v_mul_f64 v[6:7], v[6:7], 0.5
-; GFX8-SDAG-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 0.5
+; GFX8-SDAG-NEXT: v_mul_f64 v[8:9], v[0:1], v[4:5]
+; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 0.5
-; GFX8-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
-; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; GFX8-SDAG-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 0.5
; GFX8-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
-; GFX8-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
+; GFX8-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
; GFX8-SDAG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
-; GFX8-SDAG-NEXT: v_fma_f64 v[8:9], v[12:13], v[4:5], v[8:9]
-; GFX8-SDAG-NEXT: v_fma_f64 v[10:11], v[14:15], v[6:7], v[10:11]
; GFX8-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
+; GFX8-SDAG-NEXT: v_fma_f64 v[10:11], v[14:15], v[6:7], v[10:11]
+; GFX8-SDAG-NEXT: v_fma_f64 v[8:9], v[12:13], v[4:5], v[8:9]
; GFX8-SDAG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[2:3]
+; GFX8-SDAG-NEXT: v_fma_f64 v[12:13], -v[8:9], v[8:9], v[0:1]
+; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v9, 0x260
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; GFX8-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; GFX8-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX8-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: v_sqrt_v2f64:
@@ -2634,44 +2634,44 @@ define <2 x double> @v_sqrt_v2f64(<2 x double> %x) {
; GFX6-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; GFX6-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
; GFX6-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; GFX6-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX6-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
-; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
+; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX6-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
; GFX6-GISEL-NEXT: v_mul_f64 v[6:7], v[2:3], v[6:7]
-; GFX6-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
+; GFX6-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
+; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[14:15], -v[10:11], v[6:7], 0.5
-; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
-; GFX6-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; GFX6-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
; GFX6-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; GFX6-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; GFX6-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX6-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
-; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
-; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX6-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
+; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
+; GFX6-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; GFX6-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX6-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: v_sqrt_v2f64:
@@ -2681,44 +2681,44 @@ define <2 x double> @v_sqrt_v2f64(<2 x double> %x) {
; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; GFX8-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; GFX8-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; GFX8-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
-; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
+; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; GFX8-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
; GFX8-GISEL-NEXT: v_mul_f64 v[6:7], v[2:3], v[6:7]
-; GFX8-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
+; GFX8-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
+; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[14:15], -v[10:11], v[6:7], 0.5
-; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
-; GFX8-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; GFX8-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
; GFX8-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; GFX8-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; GFX8-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX8-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
-; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
-; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX8-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
+; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
+; GFX8-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; GFX8-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; GFX8-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
ret <2 x double> %result
@@ -2769,24 +2769,24 @@ define <3 x double> @v_sqrt_v3f64(<3 x double> %x) {
; GFX6-SDAG-NEXT: v_fma_f64 v[10:11], -v[14:15], v[14:15], v[2:3]
; GFX6-SDAG-NEXT: v_fma_f64 v[18:19], -v[16:17], v[16:17], v[4:5]
; GFX6-SDAG-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[14:15]
-; GFX6-SDAG-NEXT: v_fma_f64 v[10:11], v[18:19], v[12:13], v[16:17]
; GFX6-SDAG-NEXT: v_mov_b32_e32 v14, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
+; GFX6-SDAG-NEXT: v_fma_f64 v[10:11], v[18:19], v[12:13], v[16:17]
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v12, 0, v14, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[4:5]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[6:7]
; GFX6-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v12
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v15
-; GFX6-SDAG-NEXT: v_ldexp_f64 v[8:9], v[8:9], v13
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v15
-; GFX6-SDAG-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e64 s[6:7], v[4:5], v15
+; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v12, 0, v14, s[4:5]
+; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[6:7]
+; GFX6-SDAG-NEXT: v_ldexp_f64 v[8:9], v[8:9], v12
+; GFX6-SDAG-NEXT: v_mov_b32_e32 v12, 0x260
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v12
+; GFX6-SDAG-NEXT: v_ldexp_f64 v[10:11], v[10:11], v13
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, v4, s[6:7]
-; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[6:7]
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v12
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[4:5], v12
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: v_sqrt_v3f64:
@@ -2833,24 +2833,24 @@ define <3 x double> @v_sqrt_v3f64(<3 x double> %x) {
; GFX8-SDAG-NEXT: v_fma_f64 v[10:11], -v[14:15], v[14:15], v[2:3]
; GFX8-SDAG-NEXT: v_fma_f64 v[18:19], -v[16:17], v[16:17], v[4:5]
; GFX8-SDAG-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[14:15]
-; GFX8-SDAG-NEXT: v_fma_f64 v[10:11], v[18:19], v[12:13], v[16:17]
; GFX8-SDAG-NEXT: v_mov_b32_e32 v14, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
+; GFX8-SDAG-NEXT: v_fma_f64 v[10:11], v[18:19], v[12:13], v[16:17]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v12, 0, v14, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[6:7]
; GFX8-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v12
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v15
-; GFX8-SDAG-NEXT: v_ldexp_f64 v[8:9], v[8:9], v13
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v15
-; GFX8-SDAG-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e64 s[6:7], v[4:5], v15
+; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v12, 0, v14, s[4:5]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[6:7]
+; GFX8-SDAG-NEXT: v_ldexp_f64 v[8:9], v[8:9], v12
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v12, 0x260
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v12
+; GFX8-SDAG-NEXT: v_ldexp_f64 v[10:11], v[10:11], v13
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, v4, s[6:7]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[6:7]
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v12
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[4:5], v12
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: v_sqrt_v3f64:
@@ -2859,18 +2859,18 @@ define <3 x double> @v_sqrt_v3f64(<3 x double> %x) {
; GFX6-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX6-GISEL-NEXT: v_bfrev_b32_e32 v7, 8
; GFX6-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[6:7]
-; GFX6-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX6-GISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], v[4:5], v[6:7]
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX6-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
+; GFX6-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; GFX6-GISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], v[4:5], v[6:7]
; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[6:7]
; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[8:9], v[0:1]
+; GFX6-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[10:11], v[2:3]
; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[12:13], v[4:5]
; GFX6-GISEL-NEXT: v_mul_f64 v[6:7], v[8:9], 0.5
@@ -2899,24 +2899,24 @@ define <3 x double> @v_sqrt_v3f64(<3 x double> %x) {
; GFX6-GISEL-NEXT: v_fma_f64 v[8:9], -v[10:11], v[10:11], v[2:3]
; GFX6-GISEL-NEXT: v_fma_f64 v[18:19], -v[12:13], v[12:13], v[4:5]
; GFX6-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[10:11]
-; GFX6-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[16:17], v[12:13]
; GFX6-GISEL-NEXT: v_mov_b32_e32 v14, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v15, 0x260
+; GFX6-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[16:17], v[12:13]
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v14, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[6:7]
; GFX6-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v12
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v15
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v13
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v15
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e64 s[6:7], v[4:5], v15
+; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, v14, s[4:5]
+; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[6:7]
+; GFX6-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v12
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v12, 0x260
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v12
+; GFX6-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v13
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v4, v10, v4, s[6:7]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[6:7]
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v12
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[4:5], v12
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: v_sqrt_v3f64:
@@ -2925,18 +2925,18 @@ define <3 x double> @v_sqrt_v3f64(<3 x double> %x) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v7, 8
; GFX8-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX8-GISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], v[4:5], v[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX8-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
+; GFX8-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; GFX8-GISEL-NEXT: v_cmp_lt_f64_e64 s[6:7], v[4:5], v[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[6:7]
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[8:9], v[0:1]
+; GFX8-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[10:11], v[2:3]
; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[12:13], v[4:5]
; GFX8-GISEL-NEXT: v_mul_f64 v[6:7], v[8:9], 0.5
@@ -2965,24 +2965,24 @@ define <3 x double> @v_sqrt_v3f64(<3 x double> %x) {
; GFX8-GISEL-NEXT: v_fma_f64 v[8:9], -v[10:11], v[10:11], v[2:3]
; GFX8-GISEL-NEXT: v_fma_f64 v[18:19], -v[12:13], v[12:13], v[4:5]
; GFX8-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[10:11]
-; GFX8-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[16:17], v[12:13]
; GFX8-GISEL-NEXT: v_mov_b32_e32 v14, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v15, 0x260
+; GFX8-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[16:17], v[12:13]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v14, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[6:7]
; GFX8-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v12
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v15
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v13
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v15
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e64 s[6:7], v[4:5], v15
+; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, v14, s[4:5]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v13, 0, v14, s[6:7]
+; GFX8-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v12
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v12, 0x260
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v12
+; GFX8-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v13
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, v10, v4, s[6:7]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[6:7]
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v12
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[4:5], v12
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.sqrt.v3f64(<3 x double> %x)
ret <3 x double> %result
diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
index 3f2468da2232e..af3caa59e3f55 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
@@ -38,59 +38,59 @@ body: |
; GFX11-NEXT: renamable $sgpr17 = S_ADDK_I32 killed renamable $sgpr17, 128, implicit-def dead $scc
; GFX11-NEXT: S_CMP_LT_U32 renamable $sgpr17, renamable $sgpr15, implicit-def $scc
; GFX11-NEXT: renamable $sgpr17 = S_CSELECT_B32 killed renamable $sgpr17, 0, implicit killed $scc
- ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 64, $vgpr5, implicit $exec
- ; GFX11-NEXT: renamable $sgpr18_sgpr19 = V_CMP_GT_U32_e64 $sgpr15, $vgpr5, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR .VaSdst_0
+ ; GFX11-NEXT: renamable $vgpr8 = V_ADD_U32_e32 64, $vgpr5, implicit $exec
; GFX11-NEXT: renamable $vgpr6 = V_ADD_U32_e32 $sgpr8, $vgpr5, implicit $exec
- ; GFX11-NEXT: renamable $vgpr8 = V_ADD_U32_e32 $sgpr9, killed $vgpr5, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 $sgpr9, $vgpr5, implicit $exec
+ ; GFX11-NEXT: renamable $sgpr18_sgpr19 = V_CMP_GT_U32_e64 $sgpr15, killed $vgpr5, implicit $exec
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR .VaSdst_0
; GFX11-NEXT: renamable $sgpr16 = nsw S_ADD_I32 killed renamable $sgpr16, -1, implicit-def dead $scc
- ; GFX11-NEXT: renamable $sgpr20_sgpr21 = V_CMP_GT_U32_e64 $sgpr15, $vgpr7, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr9 = V_ADD_U32_e32 $sgpr9, $vgpr8, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr5 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr6, $sgpr18_sgpr19, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr6 = V_CNDMASK_B32_e64 0, $sgpr10, 0, killed $vgpr7, killed $sgpr18_sgpr19, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 $sgpr8, $vgpr8, implicit $exec
+ ; GFX11-NEXT: renamable $sgpr18_sgpr19 = V_CMP_GT_U32_e64 $sgpr15, killed $vgpr8, implicit $exec
; GFX11-NEXT: S_WAITCNT_DEPCTR .VaSdst_0
+ ; GFX11-NEXT: renamable $vgpr9 = V_CNDMASK_B32_e64 0, $sgpr10, 0, killed $vgpr9, $sgpr18_sgpr19, implicit $exec
; GFX11-NEXT: S_CMP_LG_U32 renamable $sgpr16, 0, implicit-def $scc
- ; GFX11-NEXT: renamable $vgpr5 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr6, $sgpr18_sgpr19, implicit $exec
- ; GFX11-NEXT: renamable $vgpr6 = V_ADD_U32_e32 $sgpr8, $vgpr7, implicit $exec
- ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 $sgpr9, killed $vgpr7, implicit $exec
- ; GFX11-NEXT: renamable $vgpr8 = V_CNDMASK_B32_e64 0, $sgpr10, 0, killed $vgpr8, killed $sgpr18_sgpr19, implicit $exec
- ; GFX11-NEXT: renamable $vgpr6 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr6, $sgpr20_sgpr21, implicit $exec
- ; GFX11-NEXT: renamable $vgpr7 = V_CNDMASK_B32_e64 0, $sgpr10, 0, killed $vgpr7, killed $sgpr20_sgpr21, implicit $exec
- ; GFX11-NEXT: renamable $vgpr9 = V_ADD_U32_e32 $sgpr11, $vgpr8, implicit $exec
- ; GFX11-NEXT: renamable $vgpr10 = V_ADD_U32_e32 $sgpr12, $vgpr8, implicit $exec
- ; GFX11-NEXT: renamable $vgpr11 = V_ADD_U32_e32 $sgpr13, $vgpr8, implicit $exec
- ; GFX11-NEXT: renamable $vgpr8 = V_ADD_U32_e32 $sgpr14, killed $vgpr8, implicit $exec
- ; GFX11-NEXT: renamable $vgpr12 = V_ADD_U32_e32 $sgpr11, $vgpr7, implicit $exec
- ; GFX11-NEXT: renamable $vgpr13 = V_ADD_U32_e32 $sgpr12, $vgpr7, implicit $exec
- ; GFX11-NEXT: renamable $vgpr14 = V_ADD_U32_e32 $sgpr13, $vgpr7, implicit $exec
- ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 $sgpr14, killed $vgpr7, implicit $exec
- ; GFX11-NEXT: BUNDLE implicit-def $vgpr5, implicit-def $vgpr6, implicit killed $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec, implicit killed $vgpr6 :: (dereferenceable invariant load (s16), align 1, addrspace 8) {
+ ; GFX11-NEXT: renamable $vgpr8 = V_ADD_U32_e32 $sgpr11, $vgpr6, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr10 = V_ADD_U32_e32 $sgpr12, $vgpr6, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr7 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr7, killed $sgpr18_sgpr19, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr11 = V_ADD_U32_e32 $sgpr13, $vgpr6, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr6 = V_ADD_U32_e32 $sgpr14, killed $vgpr6, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr12 = V_ADD_U32_e32 $sgpr11, $vgpr9, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr13 = V_ADD_U32_e32 $sgpr12, $vgpr9, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr14 = V_ADD_U32_e32 $sgpr13, $vgpr9, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr9 = V_ADD_U32_e32 $sgpr14, killed $vgpr9, implicit $exec
+ ; GFX11-NEXT: BUNDLE implicit-def $vgpr5, implicit-def $vgpr7, implicit killed $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec, implicit killed $vgpr7 :: (dereferenceable invariant load (s16), align 1, addrspace 8) {
; GFX11-NEXT: S_CLAUSE 1
; GFX11-NEXT: renamable $vgpr5 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr5, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
- ; GFX11-NEXT: renamable $vgpr6 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr6, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
+ ; GFX11-NEXT: renamable $vgpr7 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: }
- ; GFX11-NEXT: BUNDLE implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr8, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr7, implicit killed $vgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7, implicit $exec, implicit killed $vgpr10, implicit killed $vgpr11, implicit killed $vgpr8, implicit killed $vgpr12, implicit killed $vgpr13, implicit killed $vgpr14, implicit killed $vgpr7 :: (dereferenceable invariant load (s16), align 1, addrspace 8) {
+ ; GFX11-NEXT: BUNDLE implicit-def $vgpr8, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr6, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr9, implicit killed $vgpr8, implicit $sgpr4_sgpr5_sgpr6_sgpr7, implicit $exec, implicit killed $vgpr10, implicit killed $vgpr11, implicit killed $vgpr6, implicit killed $vgpr12, implicit killed $vgpr13, implicit killed $vgpr14, implicit killed $vgpr9 :: (dereferenceable invariant load (s16), align 1, addrspace 8) {
; GFX11-NEXT: S_CLAUSE 7
- ; GFX11-NEXT: renamable $vgpr9 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr9, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
+ ; GFX11-NEXT: renamable $vgpr8 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr8, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: renamable $vgpr10 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr10, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: renamable $vgpr11 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr11, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
- ; GFX11-NEXT: renamable $vgpr8 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr8, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
+ ; GFX11-NEXT: renamable $vgpr6 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr6, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: renamable $vgpr12 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr12, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: renamable $vgpr13 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr13, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: renamable $vgpr14 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr14, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
- ; GFX11-NEXT: renamable $vgpr7 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr7, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
+ ; GFX11-NEXT: renamable $vgpr9 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr9, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8)
; GFX11-NEXT: }
; GFX11-NEXT: S_WAITCNT .Vmcnt_8
- ; GFX11-NEXT: renamable $vgpr5 = V_PERM_B32_e64 killed $vgpr6, killed $vgpr5, 84148480, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr5 = V_PERM_B32_e64 killed $vgpr7, killed $vgpr5, 84148480, implicit $exec
; GFX11-NEXT: S_WAITCNT .Vmcnt_3
- ; GFX11-NEXT: renamable $vgpr6 = V_PERM_B32_e64 killed $vgpr12, killed $vgpr9, 84148480, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr7 = V_PERM_B32_e64 killed $vgpr12, killed $vgpr8, 84148480, implicit $exec
; GFX11-NEXT: S_WAITCNT .Vmcnt_2
- ; GFX11-NEXT: renamable $vgpr9 = V_PERM_B32_e64 killed $vgpr13, killed $vgpr10, 84148480, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr8 = V_PERM_B32_e64 killed $vgpr13, killed $vgpr10, 84148480, implicit $exec
; GFX11-NEXT: S_WAITCNT .Vmcnt_1
; GFX11-NEXT: renamable $vgpr10 = V_PERM_B32_e64 killed $vgpr14, killed $vgpr11, 84148480, implicit $exec
; GFX11-NEXT: S_WAITCNT .Vmcnt_0
- ; GFX11-NEXT: renamable $vgpr7 = V_PERM_B32_e64 killed $vgpr7, killed $vgpr8, 84148480, implicit $exec
- ; GFX11-NEXT: renamable $vgpr1 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr6, 8, killed $vgpr1, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: renamable $vgpr2 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr9, 8, killed $vgpr2, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr6 = V_PERM_B32_e64 killed $vgpr9, killed $vgpr6, 84148480, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr1 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr7, 8, killed $vgpr1, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr2 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr8, 8, killed $vgpr2, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: renamable $vgpr3 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr10, 8, killed $vgpr3, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: renamable $vgpr4 = nofpexcept V_DOT2_F32_F16 8, killed $vgpr5, 8, killed $vgpr7, 8, killed $vgpr4, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: renamable $vgpr4 = nofpexcept V_DOT2_F32_F16 8, killed $vgpr5, 8, killed $vgpr6, 8, killed $vgpr4, -1, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index dbf99aa1c8577..9085b767c52bb 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -22760,8 +22760,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -22881,8 +22881,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -23157,8 +23157,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -23280,8 +23280,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -23556,8 +23556,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:-2048 glc
@@ -23679,8 +23679,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -23915,9 +23915,9 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -23958,8 +23958,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -24076,8 +24076,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -24296,9 +24296,9 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -24339,8 +24339,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -24459,8 +24459,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -24680,9 +24680,9 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -24723,8 +24723,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -24843,8 +24843,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -25121,8 +25121,8 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -25247,8 +25247,8 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -25476,9 +25476,9 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -25519,8 +25519,8 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -25642,8 +25642,8 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -25911,8 +25911,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -26032,8 +26032,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -26260,9 +26260,9 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -26303,8 +26303,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -26421,8 +26421,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -26689,8 +26689,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -26810,8 +26810,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -27038,9 +27038,9 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -27081,8 +27081,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -27199,8 +27199,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -27467,8 +27467,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -27588,8 +27588,8 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -27816,9 +27816,9 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -27859,8 +27859,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -27977,8 +27977,8 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 93443914d3f97..5ac981c06aa25 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -16084,8 +16084,8 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -16205,8 +16205,8 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -16591,8 +16591,8 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -16714,8 +16714,8 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17100,8 +17100,8 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:-2048 glc
@@ -17223,8 +17223,8 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17429,12 +17429,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17564,9 +17563,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17607,8 +17606,8 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -17725,8 +17724,8 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -17915,12 +17914,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18050,9 +18048,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18093,8 +18091,8 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -18213,8 +18211,8 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18404,12 +18402,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18539,9 +18536,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18582,8 +18579,8 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -18702,8 +18699,8 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -19091,8 +19088,8 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -19217,8 +19214,8 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19416,12 +19413,11 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -19552,9 +19548,9 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19595,8 +19591,8 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -19718,8 +19714,8 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index b8217cf862b3a..f4e4d5629760a 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -16084,8 +16084,8 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -16205,8 +16205,8 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -16591,8 +16591,8 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -16714,8 +16714,8 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17100,8 +17100,8 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:-2048 glc
@@ -17223,8 +17223,8 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17429,12 +17429,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17564,9 +17563,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17607,8 +17606,8 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -17725,8 +17724,8 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -17915,12 +17914,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18050,9 +18048,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18093,8 +18091,8 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -18213,8 +18211,8 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18404,12 +18402,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18539,9 +18536,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18582,8 +18579,8 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -18702,8 +18699,8 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -19091,8 +19088,8 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -19217,8 +19214,8 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19416,12 +19413,11 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -19552,9 +19548,9 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19595,8 +19591,8 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -19718,8 +19714,8 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index 4ab68e8822676..df58f5d595e8f 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -16442,8 +16442,8 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off glc
@@ -16563,8 +16563,8 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v3, 16
@@ -16949,8 +16949,8 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -17072,8 +17072,8 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17458,8 +17458,8 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:-2048 glc
@@ -17581,8 +17581,8 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -17787,12 +17787,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -17922,9 +17921,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -17965,8 +17964,8 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
@@ -18083,8 +18082,8 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18273,12 +18272,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18408,9 +18406,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18451,8 +18449,8 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -18571,8 +18569,8 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -18762,12 +18760,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -18897,9 +18894,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -18940,8 +18937,8 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -19060,8 +19057,8 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
@@ -19449,8 +19446,8 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX10-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v3, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v3, v[0:1], v[5:6], off offset:2044 glc
@@ -19575,8 +19572,8 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v5, v5, v0, 16
@@ -19774,12 +19771,11 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -19910,9 +19906,9 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -19953,8 +19949,8 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX10-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v7, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc
@@ -20076,8 +20072,8 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v2, v6, v2, 16
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
index 9e4c6e6935596..178e32bb3e104 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
@@ -1125,9 +1125,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4096(ptr addrspace
; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x1000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1]
+; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x1000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc
; GFX11-NEXT: global_load_u8 v0, v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1211,9 +1212,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4097(ptr addrsp
; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xfffff000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1]
+; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xfffff000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc
; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1391,9 +1393,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF(ptr addrs
; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x7ff000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1]
+; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x7ff000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc
; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1438,9 +1441,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF(ptr addrs
; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xff800000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1]
+; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xff800000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc
; GFX11-NEXT: global_load_u8 v0, v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
index fb5674310442d..e40c57cbddca2 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
@@ -195,8 +195,8 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX7-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -237,21 +237,20 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -295,16 +294,16 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
@@ -481,8 +480,8 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_alignbit_b32 v0, v2, v0, 16
@@ -536,28 +535,26 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -571,14 +568,14 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
@@ -609,30 +606,28 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
@@ -658,15 +653,15 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
@@ -866,10 +861,10 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX7-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX7-NEXT: v_alignbit_b32 v1, v3, v2, 16
@@ -928,37 +923,34 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
@@ -975,41 +967,40 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v9, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1023,42 +1014,39 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
; GFX12-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -1082,33 +1070,33 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
@@ -1519,8 +1507,8 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX7-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -1561,21 +1549,20 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1619,16 +1606,16 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
@@ -1807,8 +1794,8 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_alignbit_b32 v0, v2, v0, 16
@@ -1862,28 +1849,26 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1897,14 +1882,14 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
@@ -1935,30 +1920,28 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
@@ -1984,15 +1967,15 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
@@ -2195,10 +2178,10 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX7-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GFX7-NEXT: v_alignbit_b32 v1, v3, v2, 16
@@ -2257,37 +2240,34 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
@@ -2304,41 +2284,40 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v9, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2352,42 +2331,39 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
; GFX12-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -2411,33 +2387,33 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index 1961ba53c1661..e423286b90b40 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -4451,19 +4451,19 @@ define amdgpu_kernel void @insert_neg_offset_vgpr(ptr addrspace(1) %in, ptr addr
; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 10, v12
; SI-MOVREL-NEXT: v_cndmask_b32_e64 v10, 11, 33, vcc
; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 9, v12
+; SI-MOVREL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb
; SI-MOVREL-NEXT: v_cndmask_b32_e64 v9, 10, 33, vcc
; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12
-; SI-MOVREL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb
; SI-MOVREL-NEXT: v_cndmask_b32_e64 v8, 9, 33, vcc
; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 15, v12
; SI-MOVREL-NEXT: v_cndmask_b32_e64 v15, 16, 33, vcc
; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 14, v12
; SI-MOVREL-NEXT: v_cndmask_b32_e64 v14, 15, 33, vcc
; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 13, v12
-; SI-MOVREL-NEXT: v_cndmask_b32_e64 v13, 14, 33, vcc
-; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 12, v12
; SI-MOVREL-NEXT: s_mov_b32 s3, 0xf000
; SI-MOVREL-NEXT: s_mov_b32 s2, -1
+; SI-MOVREL-NEXT: v_cndmask_b32_e64 v13, 14, 33, vcc
+; SI-MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 12, v12
; SI-MOVREL-NEXT: v_cndmask_b32_e64 v12, 13, 33, vcc
; SI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; SI-MOVREL-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
@@ -4486,9 +4486,9 @@ define amdgpu_kernel void @insert_neg_offset_vgpr(ptr addrspace(1) %in, ptr addr
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 7, v12
; VI-NEXT: v_cndmask_b32_e64 v7, 8, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 6, v12
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; VI-NEXT: v_cndmask_b32_e64 v6, 7, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 5, v12
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; VI-NEXT: v_cndmask_b32_e64 v5, 6, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 4, v12
; VI-NEXT: v_cndmask_b32_e64 v4, 5, 33, vcc
@@ -4499,20 +4499,20 @@ define amdgpu_kernel void @insert_neg_offset_vgpr(ptr addrspace(1) %in, ptr addr
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 9, v12
; VI-NEXT: v_cndmask_b32_e64 v9, 10, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12
-; VI-NEXT: v_cndmask_b32_e64 v8, 9, 33, vcc
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 15, v12
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s0, 48
+; VI-NEXT: v_cndmask_b32_e64 v8, 9, 33, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 15, v12
+; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: v_cndmask_b32_e64 v15, 16, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 14, v12
-; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v17, s3
; VI-NEXT: v_cndmask_b32_e64 v14, 15, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 13, v12
-; VI-NEXT: v_mov_b32_e32 v17, s3
-; VI-NEXT: v_cndmask_b32_e64 v13, 14, 33, vcc
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 12, v12
; VI-NEXT: v_mov_b32_e32 v16, s2
; VI-NEXT: s_add_u32 s2, s0, 32
+; VI-NEXT: v_cndmask_b32_e64 v13, 14, 33, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 12, v12
; VI-NEXT: v_cndmask_b32_e64 v12, 13, 33, vcc
; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
@@ -4556,18 +4556,18 @@ define amdgpu_kernel void @insert_neg_offset_vgpr(ptr addrspace(1) %in, ptr addr
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 10, v12
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v10, 11, 33, vcc
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 9, v12
+; GFX9-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v9, 10, 33, vcc
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12
-; GFX9-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v8, 9, 33, vcc
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 15, v12
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v15, 16, 33, vcc
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 14, v12
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v14, 15, 33, vcc
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 13, v12
+; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v16, 0
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v13, 14, 33, vcc
; GFX9-IDXMODE-NEXT: v_cmp_eq_u32_e32 vcc, 12, v12
-; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v16, 0
; GFX9-IDXMODE-NEXT: v_cndmask_b32_e64 v12, 13, 33, vcc
; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-IDXMODE-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index c25bbf9c0c0ce..c22404f344c0c 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -7852,13 +7852,13 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v7, v2, v7
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v3, v6
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v4
-; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v14, 1
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v2, v6
+; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v14, 1
; GFX1200-GISEL-NEXT: v_add3_u32 v1, v5, v1, v10
; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v8, vcc_lo
-; GFX1200-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v15, 1
; GFX1200-GISEL-NEXT: v_add3_u32 v3, v7, v3, v11
+; GFX1200-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v15, 1
; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v9, vcc_lo
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v8, v0, v4
diff --git a/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll b/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
index 23ebfb817096f..023e1b360ca36 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
@@ -412,16 +412,16 @@ define i64 @fneg_select_i64_1(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
@@ -434,16 +434,16 @@ define i64 @fneg_select_i64_2(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
@@ -456,16 +456,16 @@ define i64 @fneg_1_fabs_2_select_i64(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_1_fabs_2_select_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%abs.b = and i64 %b, u0x7fffffffffffffff
@@ -479,16 +479,16 @@ define i64 @fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fabs_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i64 %a, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
@@ -501,16 +501,16 @@ define i64 @fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fabs_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i64 %a, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
@@ -523,16 +523,16 @@ define i64 @fneg_fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
@@ -545,16 +545,16 @@ define i64 @fneg_fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
index d6ab190e90b7d..8bcaf9398f7e8 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
@@ -89,8 +89,8 @@ define bfloat @sitofp_i128_to_bf16(i128 %x) {
; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GCN-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
@@ -218,8 +218,8 @@ define bfloat @uitofp_i128_to_bf16(i128 %x) {
; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; GCN-NEXT: v_lshlrev_b64 v[0:1], v13, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GCN-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index a5869e44f491b..ceb227152bb43 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -85,8 +85,8 @@ define float @sitofp_i128_to_f32(i128 %x) {
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; SDAG-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
@@ -214,9 +214,9 @@ define float @sitofp_i128_to_f32(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v11, v12, v16, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
; GISEL-NEXT: v_and_b32_e32 v2, v9, v2
@@ -341,8 +341,8 @@ define float @uitofp_i128_to_f32(i128 %x) {
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v13, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
@@ -459,9 +459,9 @@ define float @uitofp_i128_to_f32(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v14, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
; GISEL-NEXT: v_and_b32_e32 v2, v8, v2
@@ -601,8 +601,8 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
; SDAG-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
; SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v6, v9, v6, s[4:5]
@@ -611,11 +611,11 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_or_b32_e32 v5, v5, v7
; SDAG-NEXT: v_or_b32_e32 v4, v4, v6
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; SDAG-NEXT: v_mov_b32_e32 v6, v10
; SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; SDAG-NEXT: v_mov_b32_e32 v5, v1
; SDAG-NEXT: v_mov_b32_e32 v4, v0
+; SDAG-NEXT: v_mov_b32_e32 v6, v10
; SDAG-NEXT: v_mov_b32_e32 v7, v11
; SDAG-NEXT: .LBB2_7: ; %Flow1
; SDAG-NEXT: s_or_b64 exec, exec, s[12:13]
@@ -733,9 +733,9 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_add_u32_e32 v15, 55, v9
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v12, vcc
; GISEL-NEXT: v_sub_u32_e32 v12, 64, v15
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, v0, v2, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, v1, v3, s[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v15, -1
@@ -747,9 +747,9 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
; GISEL-NEXT: v_cndmask_b32_e32 v9, v12, v16, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v12, v13, v17, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; GISEL-NEXT: v_cndmask_b32_e64 v9, v9, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v12, v12, -1, s[4:5]
; GISEL-NEXT: v_and_b32_e32 v0, v0, v4
@@ -890,8 +890,8 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_cndmask_b32_e64 v5, v5, v1, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v4, v0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
@@ -900,11 +900,11 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_or_b32_e32 v1, v1, v3
; SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; SDAG-NEXT: v_mov_b32_e32 v2, v9
; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SDAG-NEXT: v_or_b32_e32 v4, v4, v0
; SDAG-NEXT: v_mov_b32_e32 v0, v4
; SDAG-NEXT: v_mov_b32_e32 v1, v5
+; SDAG-NEXT: v_mov_b32_e32 v2, v9
; SDAG-NEXT: v_mov_b32_e32 v3, v10
; SDAG-NEXT: .LBB3_7: ; %Flow1
; SDAG-NEXT: s_or_b64 exec, exec, s[12:13]
@@ -1009,10 +1009,10 @@ define double @uitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_add_u32_e32 v15, 55, v8
; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v12, vcc
; GISEL-NEXT: v_sub_u32_e32 v12, 64, v15
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, v4, v0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v9, v5, v1, s[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[4:5], v15, -1
@@ -1024,9 +1024,9 @@ define double @uitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
; GISEL-NEXT: v_cndmask_b32_e32 v8, v12, v16, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v12, v13, v17, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; GISEL-NEXT: v_cndmask_b32_e64 v8, v8, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v12, v12, -1, s[4:5]
; GISEL-NEXT: v_and_b32_e32 v2, v4, v2
@@ -1177,8 +1177,8 @@ define half @sitofp_i128_to_f16(i128 %x) {
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; SDAG-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
@@ -1307,9 +1307,9 @@ define half @sitofp_i128_to_f16(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v11, v12, v16, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
; GISEL-NEXT: v_and_b32_e32 v2, v9, v2
@@ -1435,8 +1435,8 @@ define half @uitofp_i128_to_f16(i128 %x) {
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v13, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
@@ -1554,9 +1554,9 @@ define half @uitofp_i128_to_f16(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v14, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
; GISEL-NEXT: v_and_b32_e32 v2, v8, v2
diff --git a/llvm/test/CodeGen/AMDGPU/literal64.ll b/llvm/test/CodeGen/AMDGPU/literal64.ll
index defe16e729c3b..64eff175b12cd 100644
--- a/llvm/test/CodeGen/AMDGPU/literal64.ll
+++ b/llvm/test/CodeGen/AMDGPU/literal64.ll
@@ -289,20 +289,20 @@ define amdgpu_ps <2 x float> @v_cndmask(double %a) {
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GCN-SDAG-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
-; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x40632000
+; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x40632000
; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x33333333, 0, vcc_lo
; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x40690333, v1, vcc_lo
+; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x40690333, v2, vcc_lo
; GCN-SDAG-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: v_cndmask:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x40690333
; GCN-GISEL-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x40690333
; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, 0x33333333, 0, vcc_lo
-; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GCN-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0x40632000, vcc_lo
+; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GCN-GISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0x40632000, vcc_lo
; GCN-GISEL-NEXT: ; return to shader part epilog
%cmp = fcmp oeq double %a, 0.0
%sel = select i1 %cmp, double 153.0, double 200.1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
index a1de9877cf51a..2311f87425e8c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
@@ -525,9 +525,10 @@ define void @global_store_v4i32_zext_vgpr_offset_neg128(ptr addrspace(1) %sbase,
; GFX1250-ISEL: ; %bb.0:
; GFX1250-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX1250-ISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-ISEL-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v11, v6
+; GFX1250-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1250-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1250-ISEL-NEXT: global_store_b128 v[0:1], v[8:11], off offset:-128
; GFX1250-ISEL-NEXT: s_set_pc_i64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
index 9d8608b4c7ddb..8f3306b24cbdb 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
@@ -140,37 +140,37 @@ entry:
define amdgpu_cs void @vgpr_inverse_ballot(i64 %input, ptr addrspace(1) %out) {
; GISEL_W64-LABEL: vgpr_inverse_ballot:
; GISEL_W64: ; %bb.0: ; %entry
+; GISEL_W64-NEXT: v_mov_b32_e32 v5, 0
; GISEL_W64-NEXT: v_readfirstlane_b32 s0, v0
; GISEL_W64-NEXT: v_readfirstlane_b32 s1, v1
-; GISEL_W64-NEXT: v_mov_b32_e32 v5, 0
; GISEL_W64-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
; GISEL_W64-NEXT: global_store_b64 v[2:3], v[4:5], off
; GISEL_W64-NEXT: s_endpgm
;
; SDAG_W64-LABEL: vgpr_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
+; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: v_readfirstlane_b32 s0, v0
; SDAG_W64-NEXT: v_readfirstlane_b32 s1, v1
-; SDAG_W64-NEXT: s_mov_b32 s2, 0
-; SDAG_W64-NEXT: v_mov_b32_e32 v1, s2
; SDAG_W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; SDAG_W64-NEXT: v_mov_b32_e32 v1, s2
; SDAG_W64-NEXT: global_store_b64 v[2:3], v[0:1], off
; SDAG_W64-NEXT: s_endpgm
;
; GISEL_W32-LABEL: vgpr_inverse_ballot:
; GISEL_W32: ; %bb.0: ; %entry
-; GISEL_W32-NEXT: v_readfirstlane_b32 s0, v0
; GISEL_W32-NEXT: v_mov_b32_e32 v1, 0
+; GISEL_W32-NEXT: v_readfirstlane_b32 s0, v0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GISEL_W32-NEXT: global_store_b64 v[2:3], v[0:1], off
; GISEL_W32-NEXT: s_endpgm
;
; SDAG_W32-LABEL: vgpr_inverse_ballot:
; SDAG_W32: ; %bb.0: ; %entry
-; SDAG_W32-NEXT: v_readfirstlane_b32 s1, v0
; SDAG_W32-NEXT: s_mov_b32 s0, 0
-; SDAG_W32-NEXT: v_mov_b32_e32 v1, s0
+; SDAG_W32-NEXT: v_readfirstlane_b32 s1, v0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
+; SDAG_W32-NEXT: v_mov_b32_e32 v1, s0
; SDAG_W32-NEXT: global_store_b64 v[2:3], v[0:1], off
; SDAG_W32-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index eddd57c8da852..a3af24038eab5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -1576,54 +1576,55 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) {
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164DAGISEL-NEXT: v_add_nc_u32_e32 v8, 32, v8
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164DAGISEL-NEXT: v_mul_lo_u32 v8, 4, v8
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164DAGISEL-NEXT: ds_swizzle_b32 v7, v5 offset:swizzle(BROADCAST,32,15)
; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: ds_permute_b32 v6, v8, v4
-; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(1)
+; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: ds_permute_b32 v6, v8, v4
; GFX1164DAGISEL-NEXT: ds_permute_b32 v7, v8, v5
; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164DAGISEL-NEXT: v_readlane_b32 s3, v5, 63
; GFX1164DAGISEL-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
@@ -1667,54 +1668,55 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) {
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164GISEL-NEXT: v_add_nc_u32_e32 v8, 32, v8
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164GISEL-NEXT: v_mul_lo_u32 v8, 4, v8
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164GISEL-NEXT: ds_swizzle_b32 v7, v5 offset:swizzle(BROADCAST,32,15)
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: ds_permute_b32 v6, v8, v4
-; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(1)
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: ds_permute_b32 v6, v8, v4
; GFX1164GISEL-NEXT: ds_permute_b32 v7, v8, v5
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164GISEL-NEXT: v_readlane_b32 s3, v5, 63
; GFX1164GISEL-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index 71b33f9ddffa2..a61c8dd90be21 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -1637,54 +1637,55 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) {
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164DAGISEL-NEXT: v_add_nc_u32_e32 v8, 32, v8
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164DAGISEL-NEXT: v_mul_lo_u32 v8, 4, v8
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164DAGISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164DAGISEL-NEXT: ds_swizzle_b32 v7, v5 offset:swizzle(BROADCAST,32,15)
; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: ds_permute_b32 v6, v8, v4
-; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(1)
+; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: ds_permute_b32 v6, v8, v4
; GFX1164DAGISEL-NEXT: ds_permute_b32 v7, v8, v5
; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164DAGISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164DAGISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164DAGISEL-NEXT: v_readlane_b32 s3, v5, 63
; GFX1164DAGISEL-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164DAGISEL-NEXT: s_sub_u32 s0, 0, s2
@@ -1731,54 +1732,55 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) {
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164GISEL-NEXT: v_add_nc_u32_e32 v8, 32, v8
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164GISEL-NEXT: v_mul_lo_u32 v8, 4, v8
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, v4
-; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_mov_b32_dpp v6, v6 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, v5
+; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: v_mov_b32_dpp v7, v7 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164GISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: ds_swizzle_b32 v6, v4 offset:swizzle(BROADCAST,32,15)
; GFX1164GISEL-NEXT: ds_swizzle_b32 v7, v5 offset:swizzle(BROADCAST,32,15)
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: ds_permute_b32 v6, v8, v4
-; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(1)
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: ds_permute_b32 v6, v8, v4
; GFX1164GISEL-NEXT: ds_permute_b32 v7, v8, v5
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(1)
; GFX1164GISEL-NEXT: v_add_co_u32 v4, vcc, v4, v6
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v7, vcc
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readlane_b32 s2, v4, 63
; GFX1164GISEL-NEXT: v_readlane_b32 s3, v5, 63
; GFX1164GISEL-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164GISEL-NEXT: s_sub_u32 s0, 0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
index 53f404c94128d..7da75fd335f80 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
@@ -246,20 +246,20 @@ define double @v_exp_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64:
@@ -364,20 +364,20 @@ define double @v_exp_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.exp.f64(double %in)
ret double %result
@@ -572,12 +572,12 @@ define <2 x double> @v_exp_v2f64(<2 x double> %in) #0 {
; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v4
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[14:15]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[2:3], v[16:17]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[16:17]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_exp_v2f64:
@@ -725,25 +725,25 @@ define <2 x double> @v_exp_v2f64(<2 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v6
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[8:9]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], v[0:1], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v6, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v0, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, v0, v7, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v4, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_v2f64:
@@ -891,25 +891,25 @@ define <2 x double> @v_exp_v2f64(<2 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v6
; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], v[0:1], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v6, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v0, v5, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, v0, v7, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v4, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.exp.v2f64(<2 x double> %in)
ret <2 x double> %result
@@ -1145,12 +1145,12 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], v[50:51]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[22:23], v[12:13], 1.0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v22, v17, v9, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], v[48:49]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v9, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[12:13], v16
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v22, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[10:11]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[6:7]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v8, vcc
@@ -1159,8 +1159,8 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[18:19], v[8:9], 1.0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v16
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v13, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v16
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[10:11]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc
@@ -1288,22 +1288,22 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3fe62e42
; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0x3b39803f
; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3c7abc9e
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x6a5dcb37
; VI-GISEL-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; VI-GISEL-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
; VI-GISEL-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
+; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e5ade15
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[8:9], v[12:13], v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[12:13], v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[6:7], v[12:13], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[8:9], v[18:19], v[14:15]
; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[18:19], v[16:17]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[6:7], v[18:19], v[12:13]
-; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0x6a5dcb37
-; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e5ade15
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[18:19], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[18:19], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[18:19], v[20:21]
+; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e928af3
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[20:21], v[18:19]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[20:21], v[18:19]
+; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[20:21], v[18:19]
; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3ec71dee
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
@@ -1348,37 +1348,37 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[16:17], v[24:25], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[18:19], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[22:23], 1.0
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[22:23], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[18:19], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[10:11]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v19, v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
-; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[14:15], v20
-; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[16:17], v18
-; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v19
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[10:11]
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[12:13]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[12:13]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[4:5], v[12:13]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[4:5], v[10:11]
+; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[14:15], v20
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v19, v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[16:17], v18
; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v19
+; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0xc090cc00
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[12:13]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v14, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v7, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v15, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, v16, v9, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v8, s[12:13]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[12:13]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_v3f64:
@@ -1500,22 +1500,22 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0x3fe62e42
; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0x3b39803f
; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x3c7abc9e
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e5ade15
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], -v[8:9], v[12:13], v[0:1]
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[12:13], v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], -v[6:7], v[12:13], v[4:5]
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], -v[8:9], v[18:19], v[14:15]
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[18:19], v[16:17]
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], -v[6:7], v[18:19], v[12:13]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0x6a5dcb37
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e5ade15
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[18:19], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[18:19], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[18:19], v[20:21]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e928af3
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[20:21], v[18:19]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[20:21], v[18:19]
+; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[20:21], v[18:19]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3ec71dee
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
@@ -1560,37 +1560,37 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[16:17], v[24:25], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[18:19], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[22:23], 1.0
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[22:23], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[18:19], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[10:11]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v19, v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[14:15], v20
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[16:17], v18
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v19
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[10:11]
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[12:13]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[12:13]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[4:5], v[10:11]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[14:15], v20
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v19, v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[16:17], v18
; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v19
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[12:13]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v14, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v7, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v15, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, v16, v9, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v8, s[12:13]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[12:13]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.exp.v2f64(<3 x double> %in)
ret <3 x double> %result
@@ -1696,8 +1696,8 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_ldexp_f64 v[9:10], v[10:11], v12
; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[28:29], v[2:3]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v20, s[4:5]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[26:27], v[2:3]
; SI-SDAG-NEXT: v_cndmask_b32_e32 v12, v19, v10, vcc
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[26:27], v[2:3]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v12, s[4:5]
; SI-SDAG-NEXT: v_mul_f64 v[12:13], v[6:7], s[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[10:11], v[14:15], s[10:11], v[4:5]
@@ -1884,12 +1884,12 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v18, v11, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[26:27]
; SI-GISEL-NEXT: v_ldexp_f64 v[16:17], v[16:17], v52
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[28:29]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[8:9]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v53, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v19, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[26:27]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[22:23], v[12:13], 1.0
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[28:29]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v17, v18, v17, s[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v16, vcc
@@ -2060,20 +2060,19 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[8:9], v[16:17], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[18:19], -v[14:15], v[26:27], v[18:19]
; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[12:13], v[26:27], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], -v[10:11], v[26:27], v[22:23]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[8:9], v[26:27], v[24:25]
; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e5ade15
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], -v[10:11], v[26:27], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[8:9], v[26:27], v[24:25]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3e928af3
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[20:21], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[16:17], v[20:21], v[26:27]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[22:23], v[20:21], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3ec71dee
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[12:13]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[16:17], v[30:31], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[22:23], v[32:33], v[26:27]
@@ -2123,46 +2122,47 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[26:27], v[18:19], v[28:29], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[30:31], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[22:23], v[32:33], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[14:15]
; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[28:29], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v31, v[14:15]
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[20:21], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x40900000
-; VI-GISEL-NEXT: v_mov_b32_e32 v28, 0
-; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[18:19], v31
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[28:29], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[22:23], v[30:31], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[12:13]
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
+; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[18:19], v32
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v28, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[16:17], v22
+; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[14:15], v10
; VI-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[16:17], v12
-; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[22:23], v13
+; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[20:21], v18
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
-; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[14:15], v18
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[6:7], v[26:27]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[0:1], v[26:27]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], v[2:3], v[26:27]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[2:3], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[14:15], v[4:5], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[16:17], v[6:7], v[28:29]
-; VI-GISEL-NEXT: v_mov_b32_e32 v30, 0x7ff00000
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v12, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v8, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v14, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v30, v11, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v9, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v30, v13, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v11, v30, v15, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v10, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[14:15]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[16:17]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[14:15]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v11, s[16:17]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v13, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v11, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v14, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_v4f64:
@@ -2318,20 +2318,19 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[8:9], v[16:17], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], -v[14:15], v[26:27], v[18:19]
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[12:13], v[26:27], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], -v[10:11], v[26:27], v[22:23]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[8:9], v[26:27], v[24:25]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], -v[10:11], v[26:27], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[8:9], v[26:27], v[24:25]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3e928af3
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[20:21], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[16:17], v[20:21], v[26:27]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[10:11]
; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[22:23], v[20:21], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3ec71dee
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[12:13]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[10:11]
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[16:17], v[30:31], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[22:23], v[32:33], v[26:27]
@@ -2381,46 +2380,47 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[26:27], v[18:19], v[28:29], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[30:31], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[22:23], v[32:33], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[14:15]
; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[28:29], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v31, v[14:15]
-; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x40900000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v28, 0
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[18:19], v31
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[28:29], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[22:23], v[30:31], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[12:13]
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[18:19], v32
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v28, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[16:17], v22
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[14:15], v10
; GFX900-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[16:17], v12
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[22:23], v13
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[20:21], v18
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[14:15], v18
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[6:7], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[0:1], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], v[2:3], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[2:3], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[14:15], v[4:5], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[16:17], v[6:7], v[28:29]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v30, 0x7ff00000
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v12, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v8, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v14, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v30, v11, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v9, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v30, v13, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v11, v30, v15, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v10, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[14:15]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[16:17]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v9, s[14:15]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v11, s[16:17]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v14, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x double> @llvm.exp.v2f64(<4 x double> %in)
ret <4 x double> %result
@@ -2672,22 +2672,22 @@ define amdgpu_ps <2 x i32> @s_exp_f64(double inreg %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[2:3], v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[2:3]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp_f64:
@@ -2794,22 +2794,22 @@ define amdgpu_ps <2 x i32> @s_exp_f64(double inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[2:3], v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[2:3]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call double @llvm.exp.f64(double %in)
%cast = bitcast double %result to <2 x i32>
@@ -2991,36 +2991,36 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v16, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fe00000
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], v[16:17]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], 1.0
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[8:9], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[10:11]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[16:17]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v2
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v10, v7, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v10, v3, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], v[16:17]
; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v13
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[0:1], s[2:3], v[8:9]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v11, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v12, vcc
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[8:9]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v11
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[0:1]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -3104,16 +3104,16 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[6:7]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[0:1], v[4:5]
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[6:7]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
+; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[8:9], vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
; VI-SDAG-NEXT: v_readfirstlane_b32 s3, v1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; VI-SDAG-NEXT: v_readfirstlane_b32 s0, v1
; VI-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; VI-SDAG-NEXT: ; return to shader part epilog
@@ -3139,7 +3139,7 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e5ade15
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v3, v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[8:9], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[10:11]
; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0x623fde64
@@ -3178,29 +3178,29 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[6:7], v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[2:3], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp_v2f64:
@@ -3282,16 +3282,16 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[6:7]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[0:1], v[4:5]
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[6:7]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
+; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[8:9], vcc
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s3, v1
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s0, v1
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-SDAG-NEXT: ; return to shader part epilog
@@ -3317,7 +3317,7 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e5ade15
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v3, v[0:1]
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[8:9], v[10:11]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[10:11]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0x623fde64
@@ -3356,29 +3356,29 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[6:7], v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <2 x double> @llvm.exp.v2f64(<2 x double> %in)
%cast = bitcast <2 x double> %result to <4 x i32>
@@ -3467,9 +3467,9 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_add_f64 v[15:16], v[0:1], v[4:5]
; SI-SDAG-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc
; SI-SDAG-NEXT: v_add_f64 v[3:4], v[15:16], -v[4:5]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, s[10:11]
; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[13:14], s[14:15], v[7:8]
; SI-SDAG-NEXT: v_mov_b32_e32 v16, s1
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, s[10:11]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[6:7]
; SI-SDAG-NEXT: v_mov_b32_e32 v15, s0
@@ -3497,10 +3497,10 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_ldexp_f64 v[5:6], v[5:6], v11
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[15:16], v[7:8], s[30:31]
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[9:10]
-; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0
; SI-SDAG-NEXT: v_cndmask_b32_e64 v11, v19, v6, s[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[15:16], v[7:8], 1.0
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0
; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0xc090cc00
; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[3:4]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[15:16], v[6:7], 1.0
@@ -3539,120 +3539,120 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x432fffff
; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xfefa39ef
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; SI-GISEL-NEXT: v_mul_f64 v[6:7], s[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mul_f64 v[12:13], s[2:3], v[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v7
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v13
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xfefa39ef
; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe62e42
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[6:7], v[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], s[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x3b39803f
-; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3c7abc9e
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[14:15], -v[4:5]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], -v[2:3], v[16:17], v[12:13]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; SI-GISEL-NEXT: v_add_f64 v[16:17], v[12:13], v[4:5]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[10:11], s[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x3b39803f
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3c7abc9e
+; SI-GISEL-NEXT: v_add_f64 v[16:17], v[16:17], -v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[12:13]|, v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[14:15], v[6:7]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e5ade15
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0xfca7ab0c
; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e928af3
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[14:15], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[6:7], v[16:17], v[18:19]
; SI-GISEL-NEXT: v_mul_f64 v[0:1], s[4:5], v[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v22, 0x623fde64
; SI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3ec71dee
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[6:7], v[20:21], v[22:23]
; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v24, 0x7c89e6b0
; SI-GISEL-NEXT: v_mov_b32_e32 v25, 0x3efa0199
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[6:7], v[20:21], v[24:25]
; SI-GISEL-NEXT: v_add_f64 v[26:27], v[0:1], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v28, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v29, 0x3f2a01a0
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[6:7], v[20:21], v[28:29]
; SI-GISEL-NEXT: v_add_f64 v[4:5], v[26:27], -v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v26, 0x1852b7b0
; SI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f56c16c
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[20:21], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[20:21], v[26:27]
; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f811111
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[8:9], v[20:21]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[8:9]
; SI-GISEL-NEXT: v_mov_b32_e32 v30, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v31, 0x3fc55555
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[30:31]
; SI-GISEL-NEXT: v_mov_b32_e32 v32, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v33, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], -v[6:7], v[10:11], s[2:3]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[12:13], v[10:11], s[2:3]
; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[0:1], v[10:11], s[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], -v[6:7], v[16:17], v[12:13]
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[0:1], v[16:17], v[10:11]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[14:15], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[10:11], v[14:15], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[10:11], v[14:15], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[10:11], v[14:15], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[10:11], v[14:15], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[12:13], v[14:15], v[6:7]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[0:1], v[14:15], v[10:11]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[16:17], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[26:27]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[10:11], v[14:15], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[8:9]
; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v18
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[30:31]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[12:13], v[16:17], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[10:11], v[14:15], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[14:15], 1.0
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[10:11], v[16:17], v[20:21]
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v17, v[6:7]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[10:11], v[12:13], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
-; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v17
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[10:11], v[6:7], v[30:31]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v18, v16, v5, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[10:11], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[10:11], v[4:5], v[30:31]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v17, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v18, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[10:11], v[4:5], v[32:33]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v3, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v3, vcc
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[10:11], v[4:5], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v4, v[0:1]
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[10:11], v[2:3], 1.0
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v12
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v13, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[14:15]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v13
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v9
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[6:7]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v12
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -3848,43 +3848,43 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[18:19], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[12:13], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[14:15]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v16
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v6
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[14:15]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
-; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[6:7]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[2:3], v[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[4:5], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[4:5]
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v14
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[0:1]
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v12
+; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v13
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp_v3f64:
@@ -4078,43 +4078,43 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[18:19], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[12:13], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[14:15]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v16
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v6
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[14:15]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[2:3], v[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[4:5]
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v14
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[0:1]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v12
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v13
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v4
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <3 x double> @llvm.exp.v3f64(<3 x double> %in)
%cast = bitcast <3 x double> %result to <6 x i32>
@@ -4256,17 +4256,17 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[9:10], v[7:8], s[24:25]
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[13:14]
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[9:10], v[7:8], s[26:27]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[15:16]
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[9:10], v[7:8], s[28:29]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[8:9]
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[9:10], v[7:8], s[28:29]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[15:16]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v12, 0, v3, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[3:4], v[4:5], v11
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[9:10], v[7:8], s[30:31]
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[13:14]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[6:7], v[15:16]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v11, v19, v4, s[10:11]
; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[9:10], v[7:8], 1.0
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v7, v[0:1]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[6:7], v[15:16]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[9:10], v[4:5], 1.0
; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[15:16]
; SI-SDAG-NEXT: s_and_b64 vcc, s[6:7], vcc
@@ -4313,18 +4313,18 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-GISEL-NEXT: v_add_f64 v[6:7], v[10:11], v[4:5]
-; SI-GISEL-NEXT: v_mul_f64 v[14:15], s[4:5], v[0:1]
-; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[10:11]|, v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfefa39ef
+; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
+; SI-GISEL-NEXT: v_mul_f64 v[14:15], s[4:5], v[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v5, v10, vcc
; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v15
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_add_f64 v[16:17], v[14:15], v[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3fe62e42
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v6, v11, vcc
-; SI-GISEL-NEXT: v_add_f64 v[5:6], v[16:17], -v[4:5]
+; SI-GISEL-NEXT: v_add_f64 v[6:7], v[14:15], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfefa39ef
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3fe62e42
; SI-GISEL-NEXT: v_fma_f64 v[16:17], -v[2:3], v[12:13], s[0:1]
+; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[14:15]|, v[8:9]
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x3b39803f
; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3c7abc9e
@@ -4406,52 +4406,52 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[36:37], v[18:19], v[8:9]
; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[30:31]
; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[36:37], v[18:19], v[34:35]
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[36:37], v[18:19], 1.0
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[14:15]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v20, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v5, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v21, v11, v5, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[6:7], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[36:37], v[2:3], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v22, v11, v5, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v21, 0, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v22, v11, v7, vcc
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[14:15]
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[36:37], v[2:3], 1.0
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[12:13], v[16:17], v[8:9]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v20, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v10, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v21, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[4:5]
; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v21, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v22, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v22, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[12:13], v[6:7], v[34:35]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v2, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v16, v11, v3, vcc
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[12:13], v[6:7], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[0:1]
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[12:13], v[2:3], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[4:5]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v8
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v15, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[12:13], v[2:3], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v14, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v16, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v16, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v9
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v8
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[4:5]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v10
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v9
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v14
-; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v10
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v15
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -4559,11 +4559,11 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_fma_f64 v[14:15], v[18:19], v[14:15], 1.0
; VI-SDAG-NEXT: v_mov_b32_e32 v18, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v19, 0x40900000
-; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
-; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
+; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; VI-SDAG-NEXT: v_fma_f64 v[2:3], v[12:13], v[10:11], 1.0
; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v11, v[0:1]
; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[16:17]
@@ -4571,11 +4571,11 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[6:7], v[8:9]
-; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[0:1], v[8:9]
-; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v11
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[8:9]
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v11
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[8:9]
; VI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[14:15], v10
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[0:1], v[8:9]
; VI-SDAG-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[6:7], vcc
@@ -4625,13 +4625,14 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], s[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[8:9], s[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[8:9], s[6:7]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], -v[2:3], v[16:17], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[16:17], v[14:15]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[16:17], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e928af3
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v7, v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[10:11], v[18:19], v[16:17]
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[12:13], v[18:19], v[16:17]
; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[14:15], v[18:19], v[16:17]
@@ -4687,55 +4688,54 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[10:11], v[20:21], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[22:23], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[24:25], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[16:17], 1.0
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v24, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v25, 0x7ff00000
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[16:17], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[14:15], v[22:23], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[16:17], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[6:7]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v24
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[14:15], v[22:23], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[4:5]
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[12:13], v26
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[2:3], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[6:7], v[18:19]
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[16:17], 1.0
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v24
+; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[12:13], v14
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v6
; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v25, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v25, v3, s[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[20:21]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[20:21]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v25, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, v25, v5, s[12:13]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[20:21]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[6:7], v[20:21]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v5
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[12:13]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
-; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v4
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp_v4f64:
@@ -4841,11 +4841,11 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_fma_f64 v[14:15], v[18:19], v[14:15], 1.0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v18, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v19, 0x40900000
-; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
-; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
+; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; GFX900-SDAG-NEXT: v_fma_f64 v[2:3], v[12:13], v[10:11], 1.0
; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v11, v[0:1]
; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[16:17]
@@ -4853,11 +4853,11 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[6:7], v[8:9]
-; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[0:1], v[8:9]
-; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v11
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[8:9]
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v11
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[8:9]
; GFX900-SDAG-NEXT: v_ldexp_f64 v[6:7], v[14:15], v10
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[0:1], v[8:9]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[6:7], vcc
@@ -4907,13 +4907,14 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], s[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[8:9], s[4:5]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[8:9], s[6:7]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[4:5]
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], -v[2:3], v[16:17], v[10:11]
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[16:17], v[14:15]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[16:17], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e928af3
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v7, v[0:1]
; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[10:11], v[18:19], v[16:17]
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[12:13], v[18:19], v[16:17]
; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[14:15], v[18:19], v[16:17]
@@ -4969,55 +4970,54 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[10:11], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[22:23], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[24:25], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[16:17], 1.0
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v24, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v25, 0x7ff00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[16:17], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[14:15], v[22:23], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[16:17], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[6:7]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v24
+; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[14:15], v[22:23], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[4:5]
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[12:13], v26
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[2:3], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[6:7], v[18:19]
+; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[16:17], 1.0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[12:13], v14
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v6
; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v25, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v25, v3, s[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[20:21]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[20:21]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v25, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, v25, v5, s[12:13]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[20:21]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[6:7], v[20:21]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[12:13]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v6
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v4
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <4 x double> @llvm.exp.v4f64(<4 x double> %in)
%cast = bitcast <4 x double> %result to <8 x i32>
@@ -5264,20 +5264,20 @@ define double @v_exp_fabs_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_fabs_f64:
@@ -5382,20 +5382,20 @@ define double @v_exp_fabs_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%result = call double @llvm.exp.f64(double %fabs)
@@ -5642,20 +5642,20 @@ define double @v_exp_fneg_fabs_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -|v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -|v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -|v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_fneg_fabs_f64:
@@ -5760,20 +5760,20 @@ define double @v_exp_fneg_fabs_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -|v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -|v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -|v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%fneg.fabs = fneg double %fabs
@@ -6021,20 +6021,20 @@ define double @v_exp_fneg_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_fneg_f64:
@@ -6139,20 +6139,20 @@ define double @v_exp_fneg_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fneg = fneg double %in
%result = call double @llvm.exp.f64(double %fneg)
@@ -6355,6 +6355,7 @@ define double @v_exp_f64_fast(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -6382,13 +6383,12 @@ define double @v_exp_f64_fast(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_fast:
@@ -6461,6 +6461,7 @@ define double @v_exp_f64_fast(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -6488,13 +6489,12 @@ define double @v_exp_f64_fast(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call fast double @llvm.exp.f64(double %in)
ret double %result
@@ -6740,20 +6740,20 @@ define double @v_exp_f64_afn(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_afn:
@@ -6858,20 +6858,20 @@ define double @v_exp_f64_afn(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call afn double @llvm.exp.f64(double %in)
ret double %result
@@ -7073,6 +7073,7 @@ define double @v_exp_f64_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -7100,13 +7101,12 @@ define double @v_exp_f64_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_ninf:
@@ -7179,6 +7179,7 @@ define double @v_exp_f64_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -7206,13 +7207,12 @@ define double @v_exp_f64_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call ninf double @llvm.exp.f64(double %in)
ret double %result
@@ -7458,20 +7458,20 @@ define double @v_exp_f64_nnan(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_nnan:
@@ -7576,20 +7576,20 @@ define double @v_exp_f64_nnan(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call nnan double @llvm.exp.f64(double %in)
ret double %result
@@ -7835,20 +7835,20 @@ define double @v_fabs_exp_f64_afn(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_exp_f64_afn:
@@ -7953,20 +7953,20 @@ define double @v_fabs_exp_f64_afn(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%result = call afn double @llvm.exp.f64(double %fabs)
@@ -8169,6 +8169,7 @@ define double @v_exp_f64_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -8196,13 +8197,12 @@ define double @v_exp_f64_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_nnan_ninf:
@@ -8275,6 +8275,7 @@ define double @v_exp_f64_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -8302,13 +8303,12 @@ define double @v_exp_f64_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call nnan ninf double @llvm.exp.f64(double %in)
ret double %result
@@ -8588,20 +8588,20 @@ define double @v_exp_f64_from_fpext_f16(half %src) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_f16:
@@ -8710,20 +8710,20 @@ define double @v_exp_f64_from_fpext_f16(half %src) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %src to double
%result = call double @llvm.exp.f64(double %fpext)
@@ -8974,20 +8974,20 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_f32:
@@ -9094,20 +9094,20 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext float %src to double
%result = call double @llvm.exp.f64(double %fpext)
@@ -9372,20 +9372,20 @@ define double @v_exp_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_math_f16:
@@ -9496,20 +9496,20 @@ define double @v_exp_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to double
@@ -9757,20 +9757,20 @@ define double @v_exp_f64_contract(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_contract:
@@ -9875,20 +9875,20 @@ define double @v_exp_f64_contract(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call contract double @llvm.exp.f64(double %in)
ret double %result
@@ -10090,6 +10090,7 @@ define double @v_exp_f64_contract_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -10117,13 +10118,12 @@ define double @v_exp_f64_contract_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f64_contract_nnan_ninf:
@@ -10196,6 +10196,7 @@ define double @v_exp_f64_contract_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
@@ -10223,13 +10224,12 @@ define double @v_exp_f64_contract_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call contract nnan ninf double @llvm.exp.f64(double %in)
ret double %result
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
index 91e4c0f1d7f7a..a9d517b540d89 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
@@ -3520,8 +3520,8 @@ define float @v_fabs_exp_f32_afn(float %in) {
; GCN-SDAG-LABEL: v_fabs_exp_f32_afn:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; GCN-SDAG-NEXT: s_mov_b32 s5, 0x42800000
+; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; GCN-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5
; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
@@ -3534,8 +3534,8 @@ define float @v_fabs_exp_f32_afn(float %in) {
; GCN-GISEL-LABEL: v_fabs_exp_f32_afn:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GCN-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2
; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
@@ -3548,8 +3548,8 @@ define float @v_fabs_exp_f32_afn(float %in) {
; SI-SDAG-LABEL: v_fabs_exp_f32_afn:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: s_mov_b32 s5, 0x42800000
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
@@ -3562,8 +3562,8 @@ define float @v_fabs_exp_f32_afn(float %in) {
; SI-GISEL-LABEL: v_fabs_exp_f32_afn:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
index 796a5010d3886..5236bacfe8d12 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
@@ -270,20 +270,20 @@ define double @v_exp10_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64:
@@ -400,20 +400,20 @@ define double @v_exp10_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.exp10.f64(double %in)
ret double %result
@@ -624,12 +624,12 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v4
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[14:15]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[2:3], v[16:17]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[16:17]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_exp10_v2f64:
@@ -793,25 +793,25 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v6
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[8:9]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], v[0:1], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v6, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v0, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, v0, v7, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v4, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_v2f64:
@@ -975,25 +975,25 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v6
; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], v[0:1], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v6, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v0, v5, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, v0, v7, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v4, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.exp10.v2f64(<2 x double> %in)
ret <2 x double> %result
@@ -1075,7 +1075,6 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[58:59], v[0:1]
; SI-SDAG-NEXT: v_add_f64 v[0:1], v[15:16], -v[6:7]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[13:14]|, s[10:11]
-; SI-SDAG-NEXT: v_mov_b32_e32 v21, 0x7ff00000
; SI-SDAG-NEXT: v_cndmask_b32_e64 v14, v1, v14, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v13, v0, v13, s[6:7]
; SI-SDAG-NEXT: v_mul_f64 v[0:1], v[4:5], s[8:9]
@@ -1092,11 +1091,12 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[6:7], s[14:15], v[0:1]
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[15:16], s[18:19], v[17:18]
; SI-SDAG-NEXT: v_mul_f64 v[17:18], v[0:1], s[16:17]
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v12, v21, v12, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v21, 0x7ff00000
; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[0:1], s[18:19], v[17:18]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[15:16], s[20:21], v[8:9]
-; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v12, v21, v12, vcc
; SI-SDAG-NEXT: v_fma_f64 v[19:20], v[15:16], v[0:1], s[22:23]
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[17:18], s[20:21], v[8:9]
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v11, vcc
; SI-SDAG-NEXT: v_fma_f64 v[10:11], v[15:16], v[19:20], s[24:25]
@@ -1146,125 +1146,125 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0
; SI-GISEL-NEXT: v_and_b32_e32 v8, 0x80000000, v7
; SI-GISEL-NEXT: v_or_b32_e32 v13, 0x43300000, v8
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[6:7], v[12:13]
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[6:7], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, -1
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x432fffff
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[8:9], -v[12:13]
; SI-GISEL-NEXT: v_mul_f64 v[16:17], v[2:3], v[10:11]
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[14:15], -v[12:13]
-; SI-GISEL-NEXT: v_and_b32_e32 v13, 0x80000000, v17
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, -1
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x432fffff
-; SI-GISEL-NEXT: v_or_b32_e32 v13, 0x43300000, v13
-; SI-GISEL-NEXT: v_add_f64 v[18:19], v[16:17], v[12:13]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, v[8:9]
-; SI-GISEL-NEXT: v_add_f64 v[18:19], v[18:19], -v[12:13]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[16:17]|, v[8:9]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, v[14:15]
; SI-GISEL-NEXT: v_mul_f64 v[10:11], v[4:5], v[10:11]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, v18, v16, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v19, v17, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v6, vcc
+; SI-GISEL-NEXT: v_and_b32_e32 v6, 0x80000000, v17
+; SI-GISEL-NEXT: v_or_b32_e32 v13, 0x43300000, v6
+; SI-GISEL-NEXT: v_add_f64 v[18:19], v[16:17], v[12:13]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v7, vcc
+; SI-GISEL-NEXT: v_add_f64 v[6:7], v[18:19], -v[12:13]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[16:17]|, v[14:15]
+; SI-GISEL-NEXT: v_and_b32_e32 v13, 0x80000000, v11
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fd34413
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], -v[14:15], v[16:17], v[0:1]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[0:1]
+; SI-GISEL-NEXT: v_or_b32_e32 v13, 0x43300000, v13
; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0xa994fd21
; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0xbc49dc1d
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], -v[14:15], v[20:21], v[18:19]
-; SI-GISEL-NEXT: v_and_b32_e32 v13, 0x80000000, v11
+; SI-GISEL-NEXT: v_add_f64 v[24:25], v[10:11], v[12:13]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], -v[8:9], v[20:21], v[18:19]
; SI-GISEL-NEXT: v_mov_b32_e32 v22, 0x494ea3e9
; SI-GISEL-NEXT: v_mov_b32_e32 v23, 0xbcaf48ad
-; SI-GISEL-NEXT: v_or_b32_e32 v13, 0x43300000, v13
+; SI-GISEL-NEXT: v_add_f64 v[12:13], v[24:25], -v[12:13]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[10:11]|, v[14:15]
; SI-GISEL-NEXT: v_mul_f64 v[26:27], v[18:19], v[22:23]
-; SI-GISEL-NEXT: v_add_f64 v[24:25], v[10:11], v[12:13]
+; SI-GISEL-NEXT: v_fma_f64 v[32:33], -v[6:7], v[16:17], v[2:3]
; SI-GISEL-NEXT: v_mov_b32_e32 v28, 0xbbb55516
; SI-GISEL-NEXT: v_mov_b32_e32 v29, 0x40026bb1
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc
; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], v[26:27]
-; SI-GISEL-NEXT: v_add_f64 v[12:13], v[24:25], -v[12:13]
+; SI-GISEL-NEXT: v_fma_f64 v[32:33], -v[6:7], v[20:21], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[16:17], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v24, 0x6a5dcb37
; SI-GISEL-NEXT: v_mov_b32_e32 v25, 0x3e5ade15
; SI-GISEL-NEXT: v_mov_b32_e32 v26, 0xfca7ab0c
; SI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3e928af3
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[10:11]|, v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[24:25], v[26:27]
-; SI-GISEL-NEXT: v_mov_b32_e32 v32, 0x623fde64
-; SI-GISEL-NEXT: v_mov_b32_e32 v33, 0x3ec71dee
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, v12, v10, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v13, v11, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[30:31], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[30:31], -v[6:7], v[16:17], v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], -v[8:9], v[16:17], v[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[30:31], -v[6:7], v[20:21], v[30:31]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], -v[8:9], v[20:21], v[16:17]
-; SI-GISEL-NEXT: v_mul_f64 v[48:49], v[30:31], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[18:19], v[24:25], v[26:27]
+; SI-GISEL-NEXT: v_mul_f64 v[48:49], v[32:33], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[20:21], v[16:17]
+; SI-GISEL-NEXT: v_mov_b32_e32 v30, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v31, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[14:15], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[32:33], v[32:33], v[28:29], v[48:49]
; SI-GISEL-NEXT: v_mul_f64 v[22:23], v[16:17], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[30:31], v[30:31], v[28:29], v[48:49]
-; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x7c89e6b0
-; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[28:29], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[28:29], v[30:31], v[24:25], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[28:29], v[32:33], v[24:25], v[26:27]
; SI-GISEL-NEXT: v_mov_b32_e32 v34, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v35, 0x3f2a01a0
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[34:35]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[34:35]
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[24:25], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[30:31], v[28:29], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[32:33], v[28:29], v[30:31]
; SI-GISEL-NEXT: v_mov_b32_e32 v36, 0x1852b7b0
; SI-GISEL-NEXT: v_mov_b32_e32 v37, 0x3f56c16c
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[36:37]
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[24:25], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[30:31], v[26:27], v[12:13]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[24:25], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[32:33], v[26:27], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v38, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v39, 0x3f811111
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[38:39]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[24:25], v[12:13]
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[30:31], v[26:27], v[34:35]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[24:25], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[32:33], v[26:27], v[34:35]
; SI-GISEL-NEXT: v_mov_b32_e32 v50, 0x555502a1
; SI-GISEL-NEXT: v_mov_b32_e32 v51, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[50:51]
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[30:31], v[24:25], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[50:51]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[32:33], v[24:25], v[36:37]
; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fc55555
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[20:21]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[14:15]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[30:31], v[24:25], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[20:21]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[32:33], v[24:25], v[38:39]
; SI-GISEL-NEXT: v_mov_b32_e32 v48, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v49, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[34:35]
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], v[48:49]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[30:31], v[14:15], v[50:51]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[36:37]
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[30:31], v[14:15], v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[38:39]
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[18:19], v[10:11], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[30:31], v[14:15], v[48:49]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[14:15], v[34:35]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], v[48:49]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[32:33], v[8:9], v[50:51]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[14:15], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[32:33], v[8:9], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[14:15], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[18:19], v[12:13], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[32:33], v[8:9], v[48:49]
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[50:51]
-; SI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v26
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[14:15], v[50:51]
+; SI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[12:13], v26
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[30:31], v[14:15], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[32:33], v[8:9], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
; SI-GISEL-NEXT: v_mov_b32_e32 v22, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v23, 0xc090cc00
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[14:15], v[20:21]
; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0x7ff00000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[30:31], v[14:15], 1.0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v20, v11, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[32:33], v[8:9], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v20, v13, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[48:49]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[14:15], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[16:17], v[14:15], v[48:49]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v6
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[18:19]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v20, v7, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[16:17], v[12:13], 1.0
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[10:11]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v6, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v20, v7, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[16:17], v[14:15], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[22:23]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[16:17], v[6:7], 1.0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v11, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[18:19]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v20, v7, vcc
@@ -1420,89 +1420,89 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; VI-GISEL-NEXT: v_mul_f64 v[22:23], v[18:19], v[20:21]
; VI-GISEL-NEXT: v_mul_f64 v[20:21], v[12:13], v[20:21]
; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3e5ade15
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x6a5dcb37
-; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e5ade15
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x623fde64
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3ec71dee
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x7c89e6b0
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3efa0199
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x14761f6e
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f2a01a0
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x1852b7b0
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f56c16c
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x11122322
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f811111
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x555502a1
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fa55555
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0x55555511
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fc55555
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 11
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fe00000
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[22:23], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e928af3
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[22:23], v[16:17]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[22:23], v[16:17]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[22:23], v[16:17]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_mov_b32_e32 v22, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[18:19], v[24:25], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[22:23], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[12:13], v[16:17], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[10:11]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v17, v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
-; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[14:15], v20
-; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[18:19], v16
-; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v17
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[10:11]
+; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[14:15], v20
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[12:13]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[12:13]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[4:5], v[12:13]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[4:5], v[10:11]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v17, v[8:9]
+; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[18:19], v16
; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v17
+; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0xc090cc00
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[12:13]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v14, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, v16, v15, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v8, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[12:13]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[12:13]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_v3f64:
@@ -1652,89 +1652,89 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_mul_f64 v[22:23], v[18:19], v[20:21]
; GFX900-GISEL-NEXT: v_mul_f64 v[20:21], v[12:13], v[20:21]
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3e5ade15
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x6a5dcb37
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e5ade15
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x623fde64
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3ec71dee
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x7c89e6b0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3efa0199
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x14761f6e
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f2a01a0
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x1852b7b0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f56c16c
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x11122322
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3f811111
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x555502a1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fa55555
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0x55555511
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fc55555
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 11
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fe00000
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[20:21]
-; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[22:23], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e928af3
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[22:23], v[16:17]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[22:23], v[16:17]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[22:23], v[16:17]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[18:19], v[24:25], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[18:19], v[24:25], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[22:23], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[12:13], v[16:17], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[10:11]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v17, v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[14:15], v20
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[18:19], v16
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v17
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[10:11]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[14:15], v20
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[12:13]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[12:13]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[4:5], v[10:11]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v17, v[8:9]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[18:19], v16
; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v17
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[12:13]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v14, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, v16, v15, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v8, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[12:13]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[12:13]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.exp10.v2f64(<3 x double> %in)
ret <3 x double> %result
@@ -1807,9 +1807,9 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s24, 0x14761f6e
; SI-SDAG-NEXT: s_mov_b32 s25, 0x3f2a01a0
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[24:25]
-; SI-SDAG-NEXT: s_mov_b32 s26, 0x1852b7b0
-; SI-SDAG-NEXT: s_mov_b32 s27, 0x3f56c16c
-; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[26:27]
+; SI-SDAG-NEXT: s_mov_b32 s28, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s29, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[28:29]
; SI-SDAG-NEXT: s_mov_b32 s42, 0x11122322
; SI-SDAG-NEXT: s_mov_b32 s43, 0x3f811111
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[42:43]
@@ -1822,25 +1822,25 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s56, 11
; SI-SDAG-NEXT: s_mov_b32 s57, 0x3fe00000
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[56:57]
-; SI-SDAG-NEXT: s_mov_b32 s28, 0
+; SI-SDAG-NEXT: s_mov_b32 s40, 0
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
-; SI-SDAG-NEXT: s_mov_b32 s29, 0x40900000
+; SI-SDAG-NEXT: s_mov_b32 s41, 0x40900000
; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[10:11], s[16:17], v[2:3]
-; SI-SDAG-NEXT: s_mov_b32 s40, 0
+; SI-SDAG-NEXT: s_mov_b32 s26, 0
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[10:11], s[14:15], v[20:21]
-; SI-SDAG-NEXT: s_mov_b32 s41, 0xc090cc00
+; SI-SDAG-NEXT: s_mov_b32 s27, 0xc090cc00
; SI-SDAG-NEXT: v_mul_f64 v[22:23], v[20:21], s[20:21]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[28:29], v[0:1]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[40:41], v[0:1]
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[20:21], s[22:23], v[22:23]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[40:41], v[0:1]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[26:27], v[0:1]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], s[10:11], v[16:17]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[28:29], v[2:3]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[40:41], v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[12:13]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[40:41], v[2:3]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[26:27], v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[18:19]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[24:25]
-; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[26:27]
+; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[28:29]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[42:43]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[44:45]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[20:21], v[0:1], s[46:47]
@@ -1860,7 +1860,7 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[12:13]
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[18:19]
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[24:25]
-; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[26:27]
+; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[28:29]
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[42:43]
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[44:45]
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], s[46:47]
@@ -1868,13 +1868,13 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], 1.0
; SI-SDAG-NEXT: v_fma_f64 v[22:23], v[0:1], v[22:23], 1.0
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], s[10:11], v[16:17]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[28:29], v[4:5]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[40:41], v[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[12:13]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[40:41], v[4:5]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[26:27], v[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[18:19]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v4, v[12:13]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[24:25]
-; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[26:27]
+; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[28:29]
; SI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[22:23], v4
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[42:43]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[44:45]
@@ -1898,13 +1898,13 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[14:15]
; SI-SDAG-NEXT: s_and_b64 vcc, s[12:13], s[10:11]
; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[28:29], v[6:7]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[40:41], v[6:7]
; SI-SDAG-NEXT: v_ldexp_f64 v[8:9], v[16:17], v8
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[40:41], v[6:7]
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[26:27], v[6:7]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[14:15]
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[4:5]
; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2053,11 +2053,11 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[22:23]
; SI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[12:13], v32
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[30:31]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v33, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v17, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[22:23]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[18:19], v[20:21], 1.0
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[30:31]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v13, v16, v13, s[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
@@ -2224,137 +2224,137 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0x400a934f
; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[0:1], v[10:11]
; VI-GISEL-NEXT: v_mul_f64 v[12:13], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_mul_f64 v[14:15], v[4:5], v[10:11]
+; VI-GISEL-NEXT: v_mul_f64 v[16:17], v[4:5], v[10:11]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], v[10:11]
-; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x509f79ff
-; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fd34413
-; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0xa994fd21
-; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0xbc49dc1d
-; VI-GISEL-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
-; VI-GISEL-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; VI-GISEL-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; VI-GISEL-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0x509f79ff
+; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3fd34413
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0xbcaf48ad
-; VI-GISEL-NEXT: v_mov_b32_e32 v30, 0xbbb55516
-; VI-GISEL-NEXT: v_mov_b32_e32 v31, 0x40026bb1
-; VI-GISEL-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[0:1]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], -v[12:13], v[16:17], v[2:3]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[14:15], v[16:17], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[16:17], v[6:7]
-; VI-GISEL-NEXT: v_fma_f64 v[18:19], -v[8:9], v[20:21], v[18:19]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], -v[12:13], v[20:21], v[22:23]
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[14:15], v[20:21], v[24:25]
-; VI-GISEL-NEXT: v_fma_f64 v[20:21], -v[10:11], v[20:21], v[16:17]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[14:15]
-; VI-GISEL-NEXT: v_mul_f64 v[28:29], v[18:19], v[26:27]
-; VI-GISEL-NEXT: v_mul_f64 v[32:33], v[22:23], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[18:19], v[30:31], v[28:29]
-; VI-GISEL-NEXT: v_mul_f64 v[28:29], v[24:25], v[26:27]
-; VI-GISEL-NEXT: v_mul_f64 v[26:27], v[20:21], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[30:31], v[32:33]
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[14:15], v[12:13]
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[12:13], v[16:17]
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0xa994fd21
+; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0xbc49dc1d
+; VI-GISEL-NEXT: v_mov_b32_e32 v32, 0xbbb55516
+; VI-GISEL-NEXT: v_mov_b32_e32 v33, 0x40026bb1
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], -v[8:9], v[18:19], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], -v[14:15], v[18:19], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[12:13], v[18:19], v[4:5]
+; VI-GISEL-NEXT: v_fma_f64 v[18:19], -v[10:11], v[18:19], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], -v[8:9], v[16:17], v[20:21]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], -v[14:15], v[16:17], v[22:23]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], -v[12:13], v[16:17], v[24:25]
+; VI-GISEL-NEXT: v_fma_f64 v[30:31], -v[10:11], v[16:17], v[18:19]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[12:13]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[10:11]
+; VI-GISEL-NEXT: v_mul_f64 v[28:29], v[20:21], v[26:27]
+; VI-GISEL-NEXT: v_mul_f64 v[18:19], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[20:21], v[32:33], v[28:29]
+; VI-GISEL-NEXT: v_mul_f64 v[20:21], v[24:25], v[26:27]
+; VI-GISEL-NEXT: v_mul_f64 v[26:27], v[30:31], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[32:33], v[18:19]
; VI-GISEL-NEXT: v_mov_b32_e32 v22, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3e5ade15
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[24:25], v[30:31], v[28:29]
-; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[20:21], v[30:31], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[32:33], v[20:21]
+; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[30:31], v[32:33], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3e928af3
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[22:23], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[22:23], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x623fde64
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3ec71dee
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x7c89e6b0
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3efa0199
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x14761f6e
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f2a01a0
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x1852b7b0
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f56c16c
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x11122322
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f811111
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x555502a1
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fa55555
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0x55555511
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fc55555
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; VI-GISEL-NEXT: v_fma_f64 v[26:27], v[16:17], v[28:29], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[30:31], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[24:25], v[32:33], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[20:21], v[32:33], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[26:27], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x40900000
-; VI-GISEL-NEXT: v_fma_f64 v[24:25], v[24:25], v[30:31], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v31, v[8:9]
-; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[20:21], v[22:23], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[12:13]
+; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[20:21], v[30:31], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[22:23], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[14:15]
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[26:27]
+; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[16:17], v32
+; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
; VI-GISEL-NEXT: v_mov_b32_e32 v28, 0
-; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[16:17], v31
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[10:11]
+; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[18:19], v22
+; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v12
+; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[20:21], v13
; VI-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[18:19], v20
-; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[24:25], v14
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
-; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[6:7], v[26:27]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[0:1], v[26:27]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], v[2:3], v[26:27]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[2:3], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[14:15], v[4:5], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[16:17], v[6:7], v[28:29]
-; VI-GISEL-NEXT: v_mov_b32_e32 v30, 0x7ff00000
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v14, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v10, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v8, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v30, v13, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v11, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, v30, v15, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v9, v30, v9, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v12, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[14:15]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[16:17]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v10, s[14:15]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[16:17]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v14, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v15, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v11, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_v4f64:
@@ -2506,137 +2506,137 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0x400a934f
; GFX900-GISEL-NEXT: v_mul_f64 v[8:9], v[0:1], v[10:11]
; GFX900-GISEL-NEXT: v_mul_f64 v[12:13], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_mul_f64 v[14:15], v[4:5], v[10:11]
+; GFX900-GISEL-NEXT: v_mul_f64 v[16:17], v[4:5], v[10:11]
; GFX900-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], v[10:11]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x509f79ff
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fd34413
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0xa994fd21
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0xbc49dc1d
-; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
-; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0x509f79ff
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x3fd34413
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0xbcaf48ad
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v30, 0xbbb55516
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v31, 0x40026bb1
-; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[0:1]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], -v[12:13], v[16:17], v[2:3]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[14:15], v[16:17], v[4:5]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[10:11], v[16:17], v[6:7]
-; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], -v[8:9], v[20:21], v[18:19]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], -v[12:13], v[20:21], v[22:23]
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[14:15], v[20:21], v[24:25]
-; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], -v[10:11], v[20:21], v[16:17]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[14:15]
-; GFX900-GISEL-NEXT: v_mul_f64 v[28:29], v[18:19], v[26:27]
-; GFX900-GISEL-NEXT: v_mul_f64 v[32:33], v[22:23], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[18:19], v[30:31], v[28:29]
-; GFX900-GISEL-NEXT: v_mul_f64 v[28:29], v[24:25], v[26:27]
-; GFX900-GISEL-NEXT: v_mul_f64 v[26:27], v[20:21], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[30:31], v[32:33]
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[14:15], v[12:13]
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[12:13], v[16:17]
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0xa994fd21
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0xbc49dc1d
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v32, 0xbbb55516
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v33, 0x40026bb1
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], -v[8:9], v[18:19], v[0:1]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], -v[14:15], v[18:19], v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[12:13], v[18:19], v[4:5]
+; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], -v[10:11], v[18:19], v[6:7]
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], -v[8:9], v[16:17], v[20:21]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], -v[14:15], v[16:17], v[22:23]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], -v[12:13], v[16:17], v[24:25]
+; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], -v[10:11], v[16:17], v[18:19]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[12:13]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[10:11]
+; GFX900-GISEL-NEXT: v_mul_f64 v[28:29], v[20:21], v[26:27]
+; GFX900-GISEL-NEXT: v_mul_f64 v[18:19], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[20:21], v[32:33], v[28:29]
+; GFX900-GISEL-NEXT: v_mul_f64 v[20:21], v[24:25], v[26:27]
+; GFX900-GISEL-NEXT: v_mul_f64 v[26:27], v[30:31], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[32:33], v[18:19]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v22, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v23, 0x3e5ade15
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[24:25], v[30:31], v[28:29]
-; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[20:21], v[30:31], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[32:33], v[20:21]
+; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[30:31], v[32:33], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3e928af3
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[22:23], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[22:23], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x623fde64
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3ec71dee
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x7c89e6b0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3efa0199
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x14761f6e
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f2a01a0
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x1852b7b0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f56c16c
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x11122322
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f811111
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x555502a1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fa55555
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0x55555511
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fc55555
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[16:17], v[28:29], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[18:19], v[30:31], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[24:25], v[32:33], v[26:27]
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[32:33], v[20:21], v[32:33], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], v[26:27]
; GFX900-GISEL-NEXT: v_fma_f64 v[26:27], v[16:17], v[28:29], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[30:31], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[24:25], v[32:33], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[20:21], v[32:33], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[24:25], v[22:23], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[26:27], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x40900000
-; GFX900-GISEL-NEXT: v_fma_f64 v[24:25], v[24:25], v[30:31], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v31, v[8:9]
-; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[20:21], v[22:23], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[12:13]
+; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[20:21], v[30:31], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[22:23], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[14:15]
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[26:27]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[16:17], v32
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v28, 0
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[16:17], v31
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[10:11]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[18:19], v22
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v12
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[20:21], v13
; GFX900-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[18:19], v20
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[24:25], v14
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[6:7], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[0:1], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], v[2:3], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[2:3], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[14:15], v[4:5], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[16:17], v[6:7], v[28:29]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v30, 0x7ff00000
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v14, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v10, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v8, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v30, v13, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v11, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v10, v30, v15, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, v30, v9, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v12, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[14:15]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[16:17]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v10, s[14:15]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[16:17]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v14, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v15, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x double> @llvm.exp10.v2f64(<4 x double> %in)
ret <4 x double> %result
@@ -2912,22 +2912,22 @@ define amdgpu_ps <2 x i32> @s_exp10_f64(double inreg %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[2:3], v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[2:3]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp10_f64:
@@ -3046,22 +3046,22 @@ define amdgpu_ps <2 x i32> @s_exp10_f64(double inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[2:3], v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[2:3]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call double @llvm.exp10.f64(double %in)
%cast = bitcast double %result to <2 x i32>
@@ -3259,36 +3259,36 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v16, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fe00000
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], v[16:17]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], 1.0
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[8:9], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[10:11]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[16:17]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v2
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v10, v7, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v10, v3, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], v[16:17]
; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v13
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[0:1], s[2:3], v[8:9]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v11, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v12, vcc
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[8:9]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v11
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[0:1]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -3380,16 +3380,16 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[6:7]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[0:1], v[4:5]
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[6:7]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
+; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[8:9], vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
; VI-SDAG-NEXT: v_readfirstlane_b32 s3, v1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; VI-SDAG-NEXT: v_readfirstlane_b32 s0, v1
; VI-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; VI-SDAG-NEXT: ; return to shader part epilog
@@ -3415,7 +3415,7 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0xbcaf48ad
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v3, v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], v[10:11]
@@ -3462,29 +3462,29 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[6:7], v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[2:3], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp10_v2f64:
@@ -3574,16 +3574,16 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[6:7]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[0:1], v[4:5]
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[6:7]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
+; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[8:9], vcc
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s3, v1
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s0, v1
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-SDAG-NEXT: ; return to shader part epilog
@@ -3609,7 +3609,7 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0xbcaf48ad
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v3, v[0:1]
; GFX900-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], v[10:11]
@@ -3656,29 +3656,29 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[6:7], v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <2 x double> @llvm.exp10.v2f64(<2 x double> %in)
%cast = bitcast <2 x double> %result to <4 x i32>
@@ -3773,8 +3773,8 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mov_b32_e32 v19, 0x7ff00000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc
; SI-SDAG-NEXT: v_add_f64 v[3:4], v[17:18], -v[4:5]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, s[6:7]
; SI-SDAG-NEXT: v_mul_f64 v[15:16], v[13:14], s[12:13]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[6:7]
; SI-SDAG-NEXT: v_mov_b32_e32 v4, s1
@@ -3807,10 +3807,10 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_ldexp_f64 v[5:6], v[5:6], v9
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[3:4], v[7:8], s[34:35]
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[11:12]
-; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0
; SI-SDAG-NEXT: v_cndmask_b32_e64 v9, v19, v6, s[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[3:4], v[7:8], 1.0
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0
; SI-SDAG-NEXT: v_mov_b32_e32 v16, 0xc090cc00
; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[15:16]
; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[3:4], v[6:7], 1.0
@@ -3849,130 +3849,130 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x432fffff
; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x509f79ff
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; SI-GISEL-NEXT: v_mul_f64 v[6:7], s[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mul_f64 v[12:13], s[2:3], v[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v7
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v13
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[6:7], v[4:5]
+; SI-GISEL-NEXT: v_add_f64 v[16:17], v[12:13], v[4:5]
; SI-GISEL-NEXT: v_mul_f64 v[0:1], s[4:5], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fd34413
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[14:15], -v[4:5]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, v[8:9]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; SI-GISEL-NEXT: v_add_f64 v[16:17], v[16:17], -v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[12:13]|, v[8:9]
; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], s[0:1]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[10:11], s[0:1]
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0xa994fd21
-; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0xbc49dc1d
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
-; SI-GISEL-NEXT: v_add_f64 v[14:15], v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], -v[2:3], v[16:17], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0xa994fd21
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0xbc49dc1d
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
+; SI-GISEL-NEXT: v_add_f64 v[16:17], v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[14:15], v[6:7]
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x494ea3e9
; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0xbcaf48ad
-; SI-GISEL-NEXT: v_add_f64 v[4:5], v[14:15], -v[4:5]
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[16:17], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[8:9]
-; SI-GISEL-NEXT: v_mul_f64 v[14:15], v[12:13], v[18:19]
+; SI-GISEL-NEXT: v_mul_f64 v[16:17], v[6:7], v[18:19]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xbbb55516
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40026bb1
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[4:5], v[14:15]
-; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[4:5], v[16:17]
+; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3e5ade15
; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
-; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[12:13], v[14:15], v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[6:7], v[10:11], s[2:3]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[6:7], v[16:17], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[12:13], v[10:11], s[2:3]
; SI-GISEL-NEXT: v_mov_b32_e32 v24, 0x623fde64
; SI-GISEL-NEXT: v_mov_b32_e32 v25, 0x3ec71dee
; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[0:1], v[10:11], s[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[12:13], v[22:23], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[6:7], v[16:17], v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[6:7], v[22:23], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[12:13], v[14:15], v[8:9]
; SI-GISEL-NEXT: v_mov_b32_e32 v28, 0x7c89e6b0
; SI-GISEL-NEXT: v_mov_b32_e32 v29, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[0:1], v[16:17], v[10:11]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[22:23], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[0:1], v[14:15], v[10:11]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[22:23], v[28:29]
; SI-GISEL-NEXT: v_mul_f64 v[26:27], v[8:9], v[18:19]
; SI-GISEL-NEXT: v_mov_b32_e32 v22, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3f2a01a0
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[22:23]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[4:5], v[26:27]
; SI-GISEL-NEXT: v_mov_b32_e32 v26, 0x1852b7b0
; SI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3f56c16c
; SI-GISEL-NEXT: v_mul_f64 v[18:19], v[10:11], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[12:13], v[16:17], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], v[26:27]
; SI-GISEL-NEXT: v_mov_b32_e32 v30, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v31, 0x3f811111
; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[10:11], v[4:5], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[16:17], v[30:31]
-; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x555502a1
-; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[16:17]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[6:7], v[14:15], v[30:31]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[6:7], v[10:11], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3fc55555
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[6:7], v[10:11], v[18:19]
; SI-GISEL-NEXT: v_mov_b32_e32 v32, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v33, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[14:15], v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[4:5], v[14:15], v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[4:5], v[14:15], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[4:5], v[14:15], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[4:5], v[14:15], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[4:5], v[14:15], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[6:7], v[10:11], v[32:33]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[12:13]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[6:7], v[10:11], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[16:17], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[4:5], v[16:17], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[4:5], v[16:17], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[4:5], v[16:17], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[4:5], v[16:17], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[26:27]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[16:17]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[18:19]
-; SI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v20
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[8:9], v[12:13], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[14:15], v[30:31]
-; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0
-; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v15, v[6:7]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[16:17]
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[12:13]
-; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x7ff00000
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[4:5], v[16:17], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[14:15]
+; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v20
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[8:9], v[10:11], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[8:9], v[10:11], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x40900000
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[16:17], v[30:31]
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v6, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v20, v16, v7, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[18:19]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v15
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[12:13]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v17, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v20, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v12
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[10:11]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[32:33]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v16, v14, v3, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v3, vcc
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[0:1]
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v10
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v12, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v15, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v16, vcc
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[12:13]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v11
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[10:11]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v13
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v14, v1, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v14
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -4136,9 +4136,9 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_mul_f64 v[12:13], v[6:7], v[12:13]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[18:19], v[14:15]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[16:17]
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[18:19], v[12:13]
; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[18:19], v[12:13]
; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[14:15], v[12:13]
@@ -4188,43 +4188,43 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[18:19], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[12:13], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[14:15]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v16
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v6
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[14:15]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
-; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[6:7]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[2:3], v[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[4:5], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[4:5]
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v14
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[0:1]
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v12
+; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v13
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp10_v3f64:
@@ -4386,9 +4386,9 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mul_f64 v[12:13], v[6:7], v[12:13]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[18:19], v[14:15]
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[16:17]
-; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[18:19], v[12:13]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[18:19], v[12:13]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[14:15], v[12:13]
@@ -4438,43 +4438,43 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[18:19], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[2:3]
; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[12:13], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[14:15]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v16
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v6
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[14:15]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[2:3], v[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[4:5]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v14
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v13, v[0:1]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v12
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v13
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v4
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <3 x double> @llvm.exp10.v3f64(<3 x double> %in)
%cast = bitcast <3 x double> %result to <6 x i32>
@@ -4622,13 +4622,13 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[14:15], s[22:23]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v12, v[12:13]
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[24:25]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[26:27]
; SI-SDAG-NEXT: v_ldexp_f64 v[7:8], v[7:8], v12
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[28:29]
-; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0
-; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[30:31]
; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0xc090cc00
+; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[30:31]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[34:35]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v12, v21, v8, s[10:11]
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[4:5], v[9:10], s[36:37]
@@ -4685,20 +4685,20 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-GISEL-NEXT: v_add_f64 v[6:7], v[10:11], v[4:5]
-; SI-GISEL-NEXT: v_mul_f64 v[14:15], s[4:5], v[0:1]
-; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[10:11]|, v[8:9]
-; SI-GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
+; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
+; SI-GISEL-NEXT: v_mul_f64 v[14:15], s[4:5], v[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v5, v10, vcc
; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v15
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_add_f64 v[16:17], v[14:15], v[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v6, v11, vcc
-; SI-GISEL-NEXT: v_add_f64 v[5:6], v[16:17], -v[4:5]
+; SI-GISEL-NEXT: v_add_f64 v[6:7], v[14:15], v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[14:15]|, v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x509f79ff
+; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
+; SI-GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, v5, v14, vcc
; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3fd34413
; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
; SI-GISEL-NEXT: v_fma_f64 v[16:17], -v[2:3], v[12:13], s[0:1]
@@ -4789,7 +4789,6 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v24
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[20:21]
-; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[36:37]
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[16:17], v[12:13], 1.0
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[22:23], v[34:35]
@@ -4799,43 +4798,44 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[16:17]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], v[18:19]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v5, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v19, v11, v5, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[16:17]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[12:13], v[20:21]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v22, v11, v5, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v19, 0, v8, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v22, v11, v9, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[12:13], v[20:21]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v18, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[4:5]
; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v18, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v19, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v22, vcc
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[16:17]
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[4:5]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], v[36:37]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v22, vcc
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[16:17]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v12
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v2, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v18, v11, v3, vcc
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[8:9], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[2:3], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[4:5]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v12
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v15, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[2:3], 1.0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v14, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v18, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v18, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[16:17]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v10
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v13
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[4:5]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v13
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v10
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v14
-; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v15
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v9
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -4966,12 +4966,12 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v18, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v19, 0x40900000
; VI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[10:11], v21
-; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
-; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
-; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
; VI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[12:13], v6
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; VI-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[8:9]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
@@ -5004,30 +5004,31 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x979a371
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x400a934f
; VI-GISEL-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
-; VI-GISEL-NEXT: v_mul_f64 v[6:7], s[4:5], v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1]
+; VI-GISEL-NEXT: v_mul_f64 v[6:7], s[4:5], v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x509f79ff
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fd34413
; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0xa994fd21
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0xbc49dc1d
; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; VI-GISEL-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; VI-GISEL-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; VI-GISEL-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0xbcaf48ad
; VI-GISEL-NEXT: v_fma_f64 v[10:11], -v[2:3], v[8:9], s[0:1]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[8:9], s[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], s[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[8:9], s[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[8:9], s[6:7]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], -v[2:3], v[12:13], v[10:11]
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[12:13], v[16:17]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], v[14:15]
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[12:13], v[16:17]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[12:13], v[8:9]
; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0xbbb55516
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0x40026bb1
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v7, v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[20:21], v[10:11], v[18:19]
; VI-GISEL-NEXT: v_mul_f64 v[22:23], v[14:15], v[18:19]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[20:21]
@@ -5097,53 +5098,52 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[16:17], v[24:25], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v24, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v25, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
-; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[16:17], v[22:23], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[12:13], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[6:7]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v24
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[14:15], v26
-; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v16
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[2:3], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[6:7], v[18:19]
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[4:5]
+; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[16:17], v[22:23], 1.0
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v24
+; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[14:15], v12
; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v6
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
+; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v25, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v25, v3, s[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[20:21]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[20:21]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v25, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, v25, v5, s[12:13]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[20:21]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[6:7], v[20:21]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v5
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[12:13]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
-; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v4
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp10_v4f64:
@@ -5272,12 +5272,12 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v18, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v19, 0x40900000
; GFX900-SDAG-NEXT: v_ldexp_f64 v[0:1], v[10:11], v21
-; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
-; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
-; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v14
; GFX900-SDAG-NEXT: v_ldexp_f64 v[6:7], v[12:13], v6
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[8:9]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
@@ -5310,30 +5310,31 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x979a371
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x400a934f
; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
-; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], s[4:5], v[0:1]
; GFX900-GISEL-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1]
+; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], s[4:5], v[0:1]
; GFX900-GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x509f79ff
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fd34413
; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0xa994fd21
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0xbc49dc1d
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0xbcaf48ad
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], -v[2:3], v[8:9], s[0:1]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[8:9], s[4:5]
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], s[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[8:9], s[4:5]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[8:9], s[6:7]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[4:5]
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], -v[2:3], v[12:13], v[10:11]
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[12:13], v[16:17]
; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], v[14:15]
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], -v[6:7], v[12:13], v[16:17]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], -v[0:1], v[12:13], v[8:9]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0xbbb55516
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0x40026bb1
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v7, v[0:1]
; GFX900-GISEL-NEXT: v_mul_f64 v[20:21], v[10:11], v[18:19]
; GFX900-GISEL-NEXT: v_mul_f64 v[22:23], v[14:15], v[18:19]
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[20:21]
@@ -5403,53 +5404,52 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[16:17], v[24:25], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v24, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v25, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
-; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[16:17], v[22:23], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[12:13], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[6:7]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v24
+; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[14:15], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[14:15], v26
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v16
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[2:3], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v8
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[6:7], v[18:19]
+; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v12, v[4:5]
+; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[16:17], v[22:23], 1.0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[14:15], v12
; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v6
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[8:9], v7
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v25, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v25, v3, s[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[20:21]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[20:21]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v25, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, v25, v5, s[12:13]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[20:21]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[6:7], v[20:21]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[10:11]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[12:13]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v6
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v4
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <4 x double> @llvm.exp10.v4f64(<4 x double> %in)
%cast = bitcast <4 x double> %result to <8 x i32>
@@ -5720,20 +5720,20 @@ define double @v_exp10_fabs_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_fabs_f64:
@@ -5850,20 +5850,20 @@ define double @v_exp10_fabs_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%result = call double @llvm.exp10.f64(double %fabs)
@@ -6134,20 +6134,20 @@ define double @v_exp10_fneg_fabs_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -|v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -|v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -|v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_fneg_fabs_f64:
@@ -6264,20 +6264,20 @@ define double @v_exp10_fneg_fabs_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -|v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -|v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -|v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%fneg.fabs = fneg double %fabs
@@ -6549,20 +6549,20 @@ define double @v_exp10_fneg_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_fneg_f64:
@@ -6679,20 +6679,20 @@ define double @v_exp10_fneg_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fneg = fneg double %in
%result = call double @llvm.exp10.f64(double %fneg)
@@ -6913,6 +6913,7 @@ define double @v_exp10_f64_fast(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -6946,13 +6947,12 @@ define double @v_exp10_f64_fast(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_fast:
@@ -7031,6 +7031,7 @@ define double @v_exp10_f64_fast(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -7064,13 +7065,12 @@ define double @v_exp10_f64_fast(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call fast double @llvm.exp10.f64(double %in)
ret double %result
@@ -7340,20 +7340,20 @@ define double @v_exp10_f64_afn(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_afn:
@@ -7470,20 +7470,20 @@ define double @v_exp10_f64_afn(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call afn double @llvm.exp10.f64(double %in)
ret double %result
@@ -7703,6 +7703,7 @@ define double @v_exp10_f64_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -7736,13 +7737,12 @@ define double @v_exp10_f64_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_ninf:
@@ -7821,6 +7821,7 @@ define double @v_exp10_f64_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -7854,13 +7855,12 @@ define double @v_exp10_f64_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call ninf double @llvm.exp10.f64(double %in)
ret double %result
@@ -8130,20 +8130,20 @@ define double @v_exp10_f64_nnan(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_nnan:
@@ -8260,20 +8260,20 @@ define double @v_exp10_f64_nnan(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call nnan double @llvm.exp10.f64(double %in)
ret double %result
@@ -8543,20 +8543,20 @@ define double @v_fabs_exp10_f64_afn(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_exp10_f64_afn:
@@ -8673,20 +8673,20 @@ define double @v_fabs_exp10_f64_afn(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%result = call afn double @llvm.exp10.f64(double %fabs)
@@ -8907,6 +8907,7 @@ define double @v_exp10_f64_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -8940,13 +8941,12 @@ define double @v_exp10_f64_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_nnan_ninf:
@@ -9025,6 +9025,7 @@ define double @v_exp10_f64_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -9058,13 +9059,12 @@ define double @v_exp10_f64_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call nnan ninf double @llvm.exp10.f64(double %in)
ret double %result
@@ -9368,20 +9368,20 @@ define double @v_exp10_f64_from_fpext_f16(half %src) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_f16:
@@ -9502,20 +9502,20 @@ define double @v_exp10_f64_from_fpext_f16(half %src) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %src to double
%result = call double @llvm.exp10.f64(double %fpext)
@@ -9790,20 +9790,20 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
@@ -9922,20 +9922,20 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext float %src to double
%result = call double @llvm.exp10.f64(double %fpext)
@@ -10224,20 +10224,20 @@ define double @v_exp10_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_math_f16:
@@ -10360,20 +10360,20 @@ define double @v_exp10_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to double
@@ -10645,20 +10645,20 @@ define double @v_exp10_f64_contract(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_contract:
@@ -10775,20 +10775,20 @@ define double @v_exp10_f64_contract(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call contract double @llvm.exp10.f64(double %in)
ret double %result
@@ -11008,6 +11008,7 @@ define double @v_exp10_f64_contract_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -11041,13 +11042,12 @@ define double @v_exp10_f64_contract_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f64_contract_nnan_ninf:
@@ -11126,6 +11126,7 @@ define double @v_exp10_f64_contract_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -11159,13 +11160,12 @@ define double @v_exp10_f64_contract_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call contract nnan ninf double @llvm.exp10.f64(double %in)
ret double %result
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
index 34799aed60793..3d8f3949e873e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
@@ -3564,8 +3564,8 @@ define float @v_fabs_exp10_f32_afn(float %in) {
; GCN-SDAG-LABEL: v_fabs_exp10_f32_afn:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818
; GCN-SDAG-NEXT: s_mov_b32 s5, 0x42000000
+; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818
; GCN-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5
; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
@@ -3581,8 +3581,8 @@ define float @v_fabs_exp10_f32_afn(float %in) {
; GCN-GISEL-LABEL: v_fabs_exp10_f32_afn:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc217b818
; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc217b818
; GCN-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2
; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
@@ -3598,8 +3598,8 @@ define float @v_fabs_exp10_f32_afn(float %in) {
; SI-SDAG-LABEL: v_fabs_exp10_f32_afn:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818
; SI-SDAG-NEXT: s_mov_b32 s5, 0x42000000
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818
; SI-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
@@ -3615,8 +3615,8 @@ define float @v_fabs_exp10_f32_afn(float %in) {
; SI-GISEL-LABEL: v_fabs_exp10_f32_afn:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc217b818
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc217b818
; SI-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
index cb513eb8cdeeb..ef49eabe8705a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
@@ -408,25 +408,25 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -453,25 +453,25 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v3
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -517,43 +517,43 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.h
+; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v0.h
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v4
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fabs_v2bf16:
@@ -638,43 +638,43 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.h
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v0.h
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v4
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fneg_fabs_v2bf16:
@@ -696,33 +696,32 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX1200-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -760,43 +759,43 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h
+; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v4
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fneg_v2bf16:
@@ -818,33 +817,32 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX1200-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -886,25 +884,25 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -931,25 +929,25 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
-; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v3
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
index 8587e5a510411..36d243c8c0513 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
@@ -238,20 +238,20 @@ define double @v_exp2_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64:
@@ -352,20 +352,20 @@ define double @v_exp2_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.exp2.f64(double %in)
ret double %result
@@ -472,74 +472,75 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; SI-GISEL-LABEL: v_exp2_v2f64:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; SI-GISEL-NEXT: v_or_b32_e32 v7, 0x43300000, v4
-; SI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], v[6:7]
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[6:7], v[0:1], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, -1
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x432fffff
-; SI-GISEL-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
-; SI-GISEL-NEXT: v_and_b32_e32 v7, 0x80000000, v3
+; SI-GISEL-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[8:9]
-; SI-GISEL-NEXT: v_or_b32_e32 v7, 0x43300000, v7
-; SI-GISEL-NEXT: v_add_f64 v[10:11], v[2:3], v[6:7]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc
-; SI-GISEL-NEXT: v_add_f64 v[6:7], v[10:11], -v[6:7]
-; SI-GISEL-NEXT: v_add_f64 v[10:11], v[0:1], -v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x3b39803f
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v5, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v6, v1, vcc
+; SI-GISEL-NEXT: v_add_f64 v[5:6], v[0:1], -v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3c7abc9e
+; SI-GISEL-NEXT: v_mul_f64 v[14:15], v[5:6], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0xfefa39ef
+; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fe62e42
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[5:6], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v3
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[14:15], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x3b39803f
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3c7abc9e
-; SI-GISEL-NEXT: v_mul_f64 v[12:13], v[10:11], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0xfefa39ef
-; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3fe62e42
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
-; SI-GISEL-NEXT: v_add_f64 v[12:13], v[2:3], -v[6:7]
-; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[12:13], v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[14:15], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e5ade15
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[14:15], -v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0xfca7ab0c
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[2:3], -v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e928af3
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[12:13], v[14:15]
+; SI-GISEL-NEXT: v_mul_f64 v[12:13], v[8:9], v[12:13]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v4, v[4:5]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[16:17], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e5ade15
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x623fde64
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3ec71dee
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x7c89e6b0
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3f2a01a0
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x1852b7b0
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3f56c16c
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3f811111
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x555502a1
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3fc55555
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], v[14:15]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
-; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[16:17], 1.0
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[16:17], 1.0
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0xc090cc00
@@ -547,21 +548,20 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; SI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[16:17]
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[8:9], v[12:13], 1.0
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[0:1], 1.0
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[4:5]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v4, v[6:7]
-; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[10:11], v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[10:11]
; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v4
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[6:7], v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[14:15]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[2:3], v[16:17]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[16:17]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_exp2_v2f64:
@@ -705,25 +705,25 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v4
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[10:11], v6
; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[8:9]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], v[0:1], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v6, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v0, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, v0, v7, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v4, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_v2f64:
@@ -867,25 +867,25 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0x7ff00000
; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v4
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[10:11], v6
; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], v[0:1], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v6, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v0, v5, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, v0, v7, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v4, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.exp2.v2f64(<2 x double> %in)
ret <2 x double> %result
@@ -958,15 +958,15 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[42:43], v[0:1]
; SI-SDAG-NEXT: v_add_f64 v[0:1], v[13:14], -v[6:7]
; SI-SDAG-NEXT: v_bfi_b32 v7, s46, v10, v5
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, s[8:9]
; SI-SDAG-NEXT: v_add_f64 v[14:15], v[4:5], v[6:7]
; SI-SDAG-NEXT: v_mov_b32_e32 v20, 0x7ff00000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v21, v20, v12, vcc
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, s[8:9]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v13, v1, v3, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v12, v0, v2, s[6:7]
; SI-SDAG-NEXT: v_add_f64 v[6:7], v[14:15], -v[6:7]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, s[8:9]
; SI-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], -v[12:13]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[4:5]|, s[8:9]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[6:7]
; SI-SDAG-NEXT: v_mul_f64 v[16:17], v[0:1], s[10:11]
@@ -1027,116 +1027,116 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v10, -1
; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x432fffff
; SI-GISEL-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
-; SI-GISEL-NEXT: v_and_b32_e32 v9, 0x80000000, v3
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[10:11]
-; SI-GISEL-NEXT: v_or_b32_e32 v9, 0x43300000, v9
-; SI-GISEL-NEXT: v_add_f64 v[18:19], v[2:3], v[8:9]
+; SI-GISEL-NEXT: v_and_b32_e32 v9, 0x80000000, v3
; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc
; SI-GISEL-NEXT: v_add_f64 v[12:13], v[0:1], -v[6:7]
-; SI-GISEL-NEXT: v_add_f64 v[18:19], v[18:19], -v[8:9]
-; SI-GISEL-NEXT: v_and_b32_e32 v9, 0x80000000, v5
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x3b39803f
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3c7abc9e
; SI-GISEL-NEXT: v_or_b32_e32 v9, 0x43300000, v9
; SI-GISEL-NEXT: v_mul_f64 v[16:17], v[12:13], v[14:15]
+; SI-GISEL-NEXT: v_add_f64 v[20:21], v[2:3], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0xfefa39ef
+; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3fe62e42
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[18:19], v[16:17]
+; SI-GISEL-NEXT: v_add_f64 v[16:17], v[20:21], -v[8:9]
+; SI-GISEL-NEXT: v_and_b32_e32 v9, 0x80000000, v5
+; SI-GISEL-NEXT: v_or_b32_e32 v9, 0x43300000, v9
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[10:11]
-; SI-GISEL-NEXT: v_add_f64 v[28:29], v[4:5], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0xfefa39ef
-; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fe62e42
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], v[16:17]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v16, v18, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, v19, v3, vcc
-; SI-GISEL-NEXT: v_add_f64 v[8:9], v[28:29], -v[8:9]
+; SI-GISEL-NEXT: v_add_f64 v[32:33], v[4:5], v[8:9]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v3, vcc
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[32:33], -v[8:9]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, v[10:11]
-; SI-GISEL-NEXT: v_add_f64 v[32:33], v[2:3], -v[16:17]
-; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e5ade15
-; SI-GISEL-NEXT: v_mov_b32_e32 v22, 0xfca7ab0c
-; SI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3e928af3
+; SI-GISEL-NEXT: v_add_f64 v[20:21], v[2:3], -v[16:17]
+; SI-GISEL-NEXT: v_mov_b32_e32 v22, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v23, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v24, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v25, 0x3e928af3
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v5, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[18:19], v[22:23]
-; SI-GISEL-NEXT: v_mul_f64 v[36:37], v[32:33], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[12:13], v[22:23], v[24:25]
+; SI-GISEL-NEXT: v_mul_f64 v[36:37], v[20:21], v[14:15]
; SI-GISEL-NEXT: v_add_f64 v[50:51], v[4:5], -v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v26, 0x623fde64
-; SI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3ec71dee
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[32:33], v[32:33], v[20:21], v[36:37]
+; SI-GISEL-NEXT: v_mov_b32_e32 v28, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v29, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[12:13], v[26:27], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[20:21], v[18:19], v[36:37]
; SI-GISEL-NEXT: v_mul_f64 v[14:15], v[50:51], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v30, 0x7c89e6b0
; SI-GISEL-NEXT: v_mov_b32_e32 v31, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[30:31]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[50:51], v[20:21], v[14:15]
-; SI-GISEL-NEXT: v_fma_f64 v[50:51], v[32:33], v[18:19], v[22:23]
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[12:13], v[26:27], v[30:31]
+; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[50:51], v[18:19], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[50:51], v[20:21], v[22:23], v[24:25]
; SI-GISEL-NEXT: v_mov_b32_e32 v34, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v35, 0x3f2a01a0
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[34:35]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[22:23]
-; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[32:33], v[50:51], v[26:27]
-; SI-GISEL-NEXT: v_mov_b32_e32 v28, 0x1852b7b0
-; SI-GISEL-NEXT: v_mov_b32_e32 v29, 0x3f56c16c
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[32:33], v[22:23], v[30:31]
-; SI-GISEL-NEXT: v_mov_b32_e32 v38, 0x11122322
-; SI-GISEL-NEXT: v_mov_b32_e32 v39, 0x3f811111
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[24:25], v[38:39]
-; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[32:33], v[22:23], v[34:35]
-; SI-GISEL-NEXT: v_mov_b32_e32 v24, 0x555502a1
-; SI-GISEL-NEXT: v_mov_b32_e32 v25, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[32:33], v[22:23], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[12:13], v[26:27], v[34:35]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[20:21], v[50:51], v[28:29]
+; SI-GISEL-NEXT: v_mov_b32_e32 v38, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v39, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[12:13], v[26:27], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[20:21], v[24:25], v[30:31]
+; SI-GISEL-NEXT: v_mov_b32_e32 v32, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v33, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[26:27], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[20:21], v[24:25], v[34:35]
+; SI-GISEL-NEXT: v_mov_b32_e32 v26, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[28:29]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[20:21], v[24:25], v[38:39]
; SI-GISEL-NEXT: v_mov_b32_e32 v48, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v49, 0x3fc55555
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[48:49]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[30:31]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[6:7]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[32:33], v[22:23], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[30:31]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v28, v[6:7]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[20:21], v[24:25], v[32:33]
; SI-GISEL-NEXT: v_mov_b32_e32 v36, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v37, 0x3fe00000
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], v[36:37]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[34:35]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[32:33], v[6:7], v[24:25]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[34:35]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[20:21], v[6:7], v[26:27]
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[32:33], v[6:7], v[48:49]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[20:21], v[6:7], v[48:49]
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[12:13], v[10:11], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[38:39]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[32:33], v[6:7], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[20:21], v[6:7], v[36:37]
; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v26
+; SI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[10:11], v28
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[12:13]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[24:25]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[32:33], v[6:7], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[20:21], v[6:7], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[16:17]
-; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0
-; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0xc090cc00
; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[48:49]
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[32:33], v[6:7], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[22:23], v[48:49]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[20:21], v[6:7], 1.0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], v[36:37]
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[14:15], v[22:23], v[36:37]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v16
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v16
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[12:13]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v17, v7, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[18:19], 1.0
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[20:21], 1.0
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[18:19]
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], 1.0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v11, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[12:13]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[20:21]
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[18:19]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1264,9 +1264,9 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; VI-GISEL-NEXT: v_mul_f64 v[16:17], v[18:19], v[14:15]
; VI-GISEL-NEXT: v_mul_f64 v[14:15], v[20:21], v[14:15]
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[18:19], v[22:23], v[16:17]
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[20:21], v[22:23], v[14:15]
; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e5ade15
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], v[20:21], v[22:23], v[14:15]
; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[10:11], v[18:19], v[20:21]
@@ -1319,34 +1319,34 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[22:23], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[18:19], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[8:9]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v19, v[12:13]
-; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[8:9]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[12:13]
; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[10:11], v20
; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[16:17], v18
-; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v19
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[14:15]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[14:15]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[4:5], v[14:15]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], v[2:3], v[10:11]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[4:5], v[10:11]
+; VI-GISEL-NEXT: v_mov_b32_e32 v11, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[10:11]
+; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[16:17], v14
; VI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v18
+; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v12, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, v16, v13, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v8, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[12:13]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[10:11]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v9, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v13, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[14:15]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_v3f64:
@@ -1472,9 +1472,9 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_mul_f64 v[16:17], v[18:19], v[14:15]
; GFX900-GISEL-NEXT: v_mul_f64 v[14:15], v[20:21], v[14:15]
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[18:19], v[22:23], v[16:17]
-; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[20:21], v[22:23], v[14:15]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_fma_f64 v[14:15], v[20:21], v[22:23], v[14:15]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0x3e928af3
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[10:11], v[18:19], v[20:21]
@@ -1527,34 +1527,34 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[22:23], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[18:19], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[8:9]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v19, v[12:13]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[8:9]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v18, v[12:13]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[10:11], v20
; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[16:17], v18
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v19
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[14:15]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[14:15]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[4:5], v[14:15]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], v[2:3], v[10:11]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[4:5], v[10:11]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v11, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[10:11]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[16:17], v14
; GFX900-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v18
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v12, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, v16, v13, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v8, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v5, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[12:13]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[10:11]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[14:15]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.exp2.v2f64(<3 x double> %in)
ret <3 x double> %result
@@ -1615,34 +1615,34 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], s[56:57]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[14:15], v[18:19], 1.0
-; SI-SDAG-NEXT: s_mov_b32 s58, 0
+; SI-SDAG-NEXT: v_bfi_b32 v11, s62, v17, v3
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s58, 0
+; SI-SDAG-NEXT: v_ldexp_f64 v[8:9], v[14:15], v8
; SI-SDAG-NEXT: s_mov_b32 s59, 0x40900000
; SI-SDAG-NEXT: s_mov_b32 s60, 0
; SI-SDAG-NEXT: s_mov_b32 s61, 0xc090cc00
+; SI-SDAG-NEXT: v_add_f64 v[14:15], v[2:3], v[10:11]
; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[58:59], v[0:1]
; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[60:61], v[0:1]
-; SI-SDAG-NEXT: v_bfi_b32 v11, s62, v17, v3
-; SI-SDAG-NEXT: v_ldexp_f64 v[8:9], v[14:15], v8
-; SI-SDAG-NEXT: v_add_f64 v[14:15], v[2:3], v[10:11]
+; SI-SDAG-NEXT: v_add_f64 v[14:15], v[14:15], -v[10:11]
; SI-SDAG-NEXT: s_and_b64 s[6:7], s[4:5], vcc
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, v8, s[6:7]
-; SI-SDAG-NEXT: v_add_f64 v[14:15], v[14:15], -v[10:11]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[2:3]|, s[14:15]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[16:17], s[58:59], v[2:3]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v15, v15, v3, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v14, v14, v2, s[6:7]
; SI-SDAG-NEXT: v_add_f64 v[18:19], v[2:3], -v[14:15]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[14:15]
; SI-SDAG-NEXT: v_mul_f64 v[20:21], v[18:19], s[18:19]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[60:61], v[2:3]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[16:17], s[58:59], v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[18:19], s[20:21], v[20:21]
-; SI-SDAG-NEXT: s_and_b64 s[6:7], s[10:11], s[16:17]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[60:61], v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], s[22:23], v[12:13]
-; SI-SDAG-NEXT: v_bfi_b32 v11, s62, v17, v5
+; SI-SDAG-NEXT: s_and_b64 s[6:7], s[10:11], s[16:17]
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[24:25]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[58:59], v[4:5]
+; SI-SDAG-NEXT: v_bfi_b32 v11, s62, v17, v5
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[26:27]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[58:59], v[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[28:29]
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[40:41]
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], v[20:21], s[42:43]
@@ -1681,26 +1681,26 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v14, s[12:13]
; SI-SDAG-NEXT: v_add_f64 v[10:11], v[17:18], -v[10:11]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[12:13], |v[6:7]|, s[14:15]
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[58:59], v[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[12:13]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[12:13]
; SI-SDAG-NEXT: v_add_f64 v[17:18], v[6:7], -v[10:11]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[10:11]
; SI-SDAG-NEXT: v_mul_f64 v[19:20], v[17:18], s[18:19]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[60:61], v[6:7]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[58:59], v[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[17:18], s[20:21], v[19:20]
-; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x7ff00000
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[60:61], v[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], s[22:23], v[12:13]
-; SI-SDAG-NEXT: s_and_b64 s[18:19], s[12:13], s[14:15]
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x7ff00000
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[24:25]
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v16, s[16:17]
+; SI-SDAG-NEXT: s_and_b64 s[18:19], s[12:13], s[14:15]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[26:27]
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v5, v7, v15, s[8:9]
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v16, s[16:17]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[28:29]
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[10:11]
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v5, v7, v15, s[8:9]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[40:41]
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[6:7]
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[10:11]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[42:43]
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[44:45]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[46:47]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[17:18], v[12:13], s[56:57]
@@ -1721,37 +1721,37 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0
; SI-GISEL-NEXT: v_or_b32_e32 v11, 0x43300000, v8
; SI-GISEL-NEXT: v_add_f64 v[8:9], v[0:1], v[10:11]
-; SI-GISEL-NEXT: v_mov_b32_e32 v18, -1
-; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x432fffff
+; SI-GISEL-NEXT: v_mov_b32_e32 v20, -1
+; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0x432fffff
; SI-GISEL-NEXT: v_add_f64 v[8:9], v[8:9], -v[10:11]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[18:19]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[20:21]
; SI-GISEL-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc
-; SI-GISEL-NEXT: v_add_f64 v[16:17], v[0:1], -v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x3b39803f
-; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3c7abc9e
+; SI-GISEL-NEXT: v_add_f64 v[14:15], v[0:1], -v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x3b39803f
+; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3c7abc9e
; SI-GISEL-NEXT: v_or_b32_e32 v11, 0x43300000, v11
-; SI-GISEL-NEXT: v_mul_f64 v[20:21], v[16:17], v[14:15]
+; SI-GISEL-NEXT: v_mul_f64 v[18:19], v[14:15], v[16:17]
; SI-GISEL-NEXT: v_add_f64 v[22:23], v[2:3], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfefa39ef
; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3fe62e42
-; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[16:17], v[12:13], v[20:21]
-; SI-GISEL-NEXT: v_add_f64 v[16:17], v[22:23], -v[10:11]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[14:15], v[12:13], v[18:19]
+; SI-GISEL-NEXT: v_add_f64 v[14:15], v[22:23], -v[10:11]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[20:21]
; SI-GISEL-NEXT: v_and_b32_e32 v11, 0x80000000, v5
; SI-GISEL-NEXT: v_or_b32_e32 v11, 0x43300000, v11
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v20, v16, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v21, v17, v3, vcc
-; SI-GISEL-NEXT: v_add_f64 v[16:17], v[4:5], v[10:11]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, v[18:19]
-; SI-GISEL-NEXT: v_add_f64 v[16:17], v[16:17], -v[10:11]
-; SI-GISEL-NEXT: v_add_f64 v[22:23], v[2:3], -v[20:21]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc
-; SI-GISEL-NEXT: v_add_f64 v[26:27], v[4:5], -v[16:17]
-; SI-GISEL-NEXT: v_mul_f64 v[28:29], v[22:23], v[14:15]
-; SI-GISEL-NEXT: v_mul_f64 v[30:31], v[26:27], v[14:15]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v18, v14, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v19, v15, v3, vcc
+; SI-GISEL-NEXT: v_add_f64 v[14:15], v[4:5], v[10:11]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, v[20:21]
+; SI-GISEL-NEXT: v_add_f64 v[14:15], v[14:15], -v[10:11]
+; SI-GISEL-NEXT: v_add_f64 v[22:23], v[2:3], -v[18:19]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, v14, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v15, v5, vcc
+; SI-GISEL-NEXT: v_add_f64 v[26:27], v[4:5], -v[14:15]
+; SI-GISEL-NEXT: v_mul_f64 v[28:29], v[22:23], v[16:17]
+; SI-GISEL-NEXT: v_mul_f64 v[30:31], v[26:27], v[16:17]
; SI-GISEL-NEXT: v_and_b32_e32 v11, 0x80000000, v7
; SI-GISEL-NEXT: v_or_b32_e32 v11, 0x43300000, v11
; SI-GISEL-NEXT: v_fma_f64 v[28:29], v[22:23], v[12:13], v[28:29]
@@ -1765,103 +1765,103 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; SI-GISEL-NEXT: v_fma_f64 v[26:27], v[24:25], v[30:31], v[32:33]
; SI-GISEL-NEXT: v_mov_b32_e32 v34, 0x623fde64
; SI-GISEL-NEXT: v_mov_b32_e32 v35, 0x3ec71dee
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[24:25], v[26:27], v[34:35]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[26:27], v[34:35]
; SI-GISEL-NEXT: v_mov_b32_e32 v26, 0x7c89e6b0
; SI-GISEL-NEXT: v_mov_b32_e32 v27, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[24:25], v[18:19], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], v[26:27]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v6, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v11, v7, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v36, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v37, 0x3f2a01a0
; SI-GISEL-NEXT: v_add_f64 v[38:39], v[6:7], -v[10:11]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[24:25], v[18:19], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], v[36:37]
; SI-GISEL-NEXT: v_mov_b32_e32 v48, 0x1852b7b0
; SI-GISEL-NEXT: v_mov_b32_e32 v49, 0x3f56c16c
-; SI-GISEL-NEXT: v_mul_f64 v[14:15], v[38:39], v[14:15]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[24:25], v[18:19], v[48:49]
+; SI-GISEL-NEXT: v_mul_f64 v[16:17], v[38:39], v[16:17]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], v[48:49]
; SI-GISEL-NEXT: v_mov_b32_e32 v50, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v51, 0x3f811111
-; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[38:39], v[12:13], v[14:15]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[18:19], v[50:51]
-; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x555502a1
-; SI-GISEL-NEXT: v_mov_b32_e32 v19, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[14:15], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[38:39], v[12:13], v[16:17]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[24:25], v[20:21], v[50:51]
+; SI-GISEL-NEXT: v_mov_b32_e32 v20, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v21, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[24:25], v[16:17], v[20:21]
; SI-GISEL-NEXT: v_mov_b32_e32 v38, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v39, 0x3fc55555
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[14:15], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[24:25], v[16:17], v[38:39]
; SI-GISEL-NEXT: v_mov_b32_e32 v52, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v53, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[14:15], v[52:53]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[24:25], v[16:17], v[52:53]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[14:15], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[24:25], v[16:17], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[10:11]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[24:25], v[14:15], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[24:25], v[16:17], 1.0
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[22:23], v[30:31], v[32:33]
-; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[14:15], v8
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[30:31], v[32:33]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[34:35]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[36:37]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[48:49]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[50:51]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[38:39]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], v[52:53]
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[28:29], v[14:15], 1.0
+; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[16:17], v8
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[30:31], v[32:33]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[34:35]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[48:49]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[50:51]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], v[52:53]
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], 1.0
+; SI-GISEL-NEXT: v_fma_f64 v[16:17], v[28:29], v[16:17], 1.0
; SI-GISEL-NEXT: v_fma_f64 v[28:29], v[12:13], v[30:31], v[32:33]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[20:21]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[24:25], v[34:35]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[24:25], v[34:35]
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[28:29], v[34:35]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[26:27]
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[26:27]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[36:37]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[36:37]
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[36:37]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[48:49]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[48:49]
; SI-GISEL-NEXT: v_mov_b32_e32 v30, 0
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[50:51]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[50:51]
; SI-GISEL-NEXT: v_mov_b32_e32 v31, 0x40900000
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[18:19]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[20:21]
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[30:31]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[38:39]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[38:39]
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[48:49]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], v[52:53]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], v[52:53]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v33, 0, v8, vcc
; SI-GISEL-NEXT: v_fma_f64 v[24:25], v[12:13], v[24:25], v[50:51]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], 1.0
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[16:17]
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[24:25], v[18:19]
-; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[22:23], v[20:21], 1.0
-; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[18:19], v[38:39]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, v16, v9, vcc
-; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[20:21], v8
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], 1.0
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[24:25], v[20:21]
+; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[22:23], v[18:19], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x7ff00000
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], v[38:39]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v14, v9, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[18:19], v8
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[30:31]
; SI-GISEL-NEXT: v_mov_b32_e32 v28, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; SI-GISEL-NEXT: v_fma_f64 v[18:19], v[12:13], v[18:19], v[52:53]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v20, 0, v8, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v21, v16, v9, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], v[52:53]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v18, 0, v8, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v19, v14, v9, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
-; SI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[14:15], v32
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[30:31]
+; SI-GISEL-NEXT: v_ldexp_f64 v[16:17], v[16:17], v32
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v33, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v17, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v15, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[18:19], 1.0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v15, v16, v15, s[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v14, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v15, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[20:21], 1.0
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[2:3], v[30:31]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v17, v14, v17, s[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v16, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v17, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], 1.0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v20, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v21, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v18, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v19, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[30:31]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
@@ -2010,6 +2010,7 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; VI-GISEL-NEXT: v_add_f64 v[20:21], v[2:3], -v[10:11]
; VI-GISEL-NEXT: v_add_f64 v[24:25], v[4:5], -v[12:13]
; VI-GISEL-NEXT: v_add_f64 v[26:27], v[6:7], -v[14:15]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[14:15]
; VI-GISEL-NEXT: v_mul_f64 v[22:23], v[16:17], v[18:19]
; VI-GISEL-NEXT: v_mul_f64 v[30:31], v[20:21], v[18:19]
; VI-GISEL-NEXT: v_mul_f64 v[32:33], v[26:27], v[18:19]
@@ -2077,48 +2078,47 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[26:27], v[16:17], v[28:29], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[30:31], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[30:31], v[22:23], v[32:33], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[26:27], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v26, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v27, 0x40900000
-; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v31, v[8:9]
-; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[24:25], v[20:21], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[10:11]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v21, v[12:13]
-; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[16:17], v31
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[14:15]
+; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[22:23], v[30:31], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[10:11]
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[26:27]
+; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
+; VI-GISEL-NEXT: v_ldexp_f64 v[10:11], v[16:17], v32
+; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[12:13]
+; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[18:19], v22
; VI-GISEL-NEXT: v_mov_b32_e32 v28, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[12:13], v[18:19], v20
-; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[22:23], v21
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
; VI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[6:7], v[26:27]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[0:1], v[26:27]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], v[2:3], v[26:27]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[2:3], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[14:15], v[4:5], v[28:29]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[16:17], v[6:7], v[28:29]
-; VI-GISEL-NEXT: v_mov_b32_e32 v30, 0x7ff00000
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v14, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v12, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v8, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v30, v11, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v13, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v11, v30, v15, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v9, v30, v9, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v10, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[14:15]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[16:17]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v11, s[14:15]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[16:17]
+; VI-GISEL-NEXT: v_ldexp_f64 v[14:15], v[20:21], v14
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[26:27]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v13, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v14, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_v4f64:
@@ -2264,6 +2264,7 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_add_f64 v[20:21], v[2:3], -v[10:11]
; GFX900-GISEL-NEXT: v_add_f64 v[24:25], v[4:5], -v[12:13]
; GFX900-GISEL-NEXT: v_add_f64 v[26:27], v[6:7], -v[14:15]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[14:15]
; GFX900-GISEL-NEXT: v_mul_f64 v[22:23], v[16:17], v[18:19]
; GFX900-GISEL-NEXT: v_mul_f64 v[30:31], v[20:21], v[18:19]
; GFX900-GISEL-NEXT: v_mul_f64 v[32:33], v[26:27], v[18:19]
@@ -2331,48 +2332,47 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[26:27], v[16:17], v[28:29], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[28:29], v[18:19], v[30:31], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[30:31], v[22:23], v[32:33], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v32, v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[16:17], v[26:27], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v26, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v27, 0x40900000
-; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v31, v[8:9]
-; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[24:25], v[20:21], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v20, v[10:11]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v21, v[12:13]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[16:17], v31
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[14:15]
+; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[18:19], v[28:29], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[22:23], v[30:31], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[10:11]
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[26:27]
+; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[10:11], v[16:17], v32
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[12:13]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[18:19], v22
; GFX900-GISEL-NEXT: v_mov_b32_e32 v28, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v29, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[12:13], v[18:19], v20
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[22:23], v21
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], v[6:7], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], v[0:1], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], v[2:3], v[26:27]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], v[0:1], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], v[2:3], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[14:15], v[4:5], v[28:29]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[16:17], v[6:7], v[28:29]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v30, 0x7ff00000
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v14, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v12, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v8, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v30, v11, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v13, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v11, v30, v15, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, v30, v9, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v10, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[14:15]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[16:17]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v8, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v11, s[14:15]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v9, s[16:17]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[14:15], v[20:21], v14
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[4:5], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[6:7], v[26:27]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v13, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[4:5], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[6:7], v[28:29]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v14, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x double> @llvm.exp2.v2f64(<4 x double> %in)
ret <4 x double> %result
@@ -2622,22 +2622,22 @@ define amdgpu_ps <2 x i32> @s_exp2_f64(double inreg %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[2:3], v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[2:3]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp2_f64:
@@ -2738,22 +2738,22 @@ define amdgpu_ps <2 x i32> @s_exp2_f64(double inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[2:3], v[4:5], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[2:3], v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[2:3]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call double @llvm.exp2.f64(double %in)
%cast = bitcast double %result to <2 x i32>
@@ -2942,36 +2942,36 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[4:5], v[12:13], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v17, 0x3fe00000
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[4:5], v[12:13], v[16:17]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[4:5], v[12:13], 1.0
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[0:1]
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[8:9], v[14:15]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], v[10:11]
; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], 1.0
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], v[16:17]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[4:5], v0
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[8:9], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], 1.0
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v10, v5, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, v10, v1, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[4:5], v[16:17]
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
-; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[0:1], s[2:3], v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], 1.0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v11, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v12, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v12, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[8:9]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[0:1]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v6
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v2
; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -3047,16 +3047,16 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[6:7]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[0:1], v[4:5]
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[6:7]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
+; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[8:9], vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
; VI-SDAG-NEXT: v_readfirstlane_b32 s3, v1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; VI-SDAG-NEXT: v_readfirstlane_b32 s0, v1
; VI-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; VI-SDAG-NEXT: ; return to shader part epilog
@@ -3072,6 +3072,7 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_add_f64 v[4:5], s[0:1], -v[0:1]
; VI-GISEL-NEXT: v_add_f64 v[6:7], s[2:3], -v[2:3]
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[4:5], v[8:9]
; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[10:11]
@@ -3118,30 +3119,29 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[2:3], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[4:5], v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[6:7], v8
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[2:3]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[4:5]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[8:9]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp2_v2f64:
@@ -3215,16 +3215,16 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[6:7]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[0:1], v[4:5]
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[6:7]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
+; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[8:9], vcc
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[6:7]
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s3, v1
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s0, v1
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX900-SDAG-NEXT: ; return to shader part epilog
@@ -3240,6 +3240,7 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_add_f64 v[4:5], s[0:1], -v[0:1]
; GFX900-GISEL-NEXT: v_add_f64 v[6:7], s[2:3], -v[2:3]
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[10:11], v[4:5], v[8:9]
; GFX900-GISEL-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[10:11]
@@ -3286,30 +3287,29 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x40900000
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[4:5], v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[6:7], v8
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[6:7]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[8:9]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <2 x double> @llvm.exp2.v2f64(<2 x double> %in)
%cast = bitcast <2 x double> %result to <4 x i32>
@@ -3404,11 +3404,11 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[17:18], v[2:3], s[8:9]
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[13:14], v[15:16], s[14:15]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], s[10:11], v[17:18]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, v19, v6, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v17, 0
; SI-SDAG-NEXT: v_mov_b32_e32 v18, 0xc090cc00
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[17:18]
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, v19, v6, vcc
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[13:14], v[15:16], s[16:17]
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[4:5], s[4:5], v[17:18]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[12:13], v[7:8]
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[13:14], v[15:16], s[18:19]
@@ -3538,8 +3538,9 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v32, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v33, 0x3fe00000
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[4:5], v[10:11], v[32:33]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[4:5], v[10:11], 1.0
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], 1.0
; SI-GISEL-NEXT: v_fma_f64 v[10:11], v[16:17], v[12:13], v[18:19]
; SI-GISEL-NEXT: v_fma_f64 v[12:13], v[6:7], v[12:13], v[18:19]
@@ -3564,37 +3565,36 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x40900000
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[12:13]
; SI-GISEL-NEXT: v_mov_b32_e32 v16, 0x7ff00000
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v17, v[8:9]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[10:11], v[14:15]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v18, v16, v5, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[10:11], v[14:15]
; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[10:11]
-; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v17
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v5, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[8:9], v[26:27]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[26:27]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v17, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v18, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[12:13]
; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[32:33]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v1, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v16, v1, vcc
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[4:5], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[10:11]
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], 1.0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v8, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v15, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[12:13]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v14
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v9
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[10:11]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v15
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v14
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v4
; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -3676,23 +3676,23 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v11, v[4:5]
; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[6:7], v14
+; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x40900000
-; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
; VI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v11
; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v9, 0xc090cc00
-; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[0:1], v[6:7]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[4:5], v[8:9]
-; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[0:1], v[8:9]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[6:7]
; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[2:3], v[8:9]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[0:1], v[6:7]
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[0:1], v[8:9]
; VI-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[8:9]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; VI-SDAG-NEXT: s_and_b64 vcc, s[14:15], vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[10:11]
+; VI-SDAG-NEXT: s_and_b64 vcc, s[14:15], vcc
; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[12:13], s[6:7]
@@ -3726,9 +3726,9 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[18:19], v[14:15]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[18:19], v[16:17]
-; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[12:13]
; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[12:13]
; VI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[14:15], v[12:13]
@@ -3778,42 +3778,42 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[18:19], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], 1.0
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[16:17], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[0:1], v[10:11], v[12:13], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v11, v[4:5]
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
-; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v16
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[14:15]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v11
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[14:15]
-; VI-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v11, v[4:5]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v14
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
+; VI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v11
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[8:9]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[4:5], v[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, v17, v5, s[6:7]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[2:3], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[8:9]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[6:7]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; VI-GISEL-NEXT: ; return to shader part epilog
;
@@ -3894,23 +3894,23 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v11, v[4:5]
; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[6:7], v14
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x40900000
-; GFX900-SDAG-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
; GFX900-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v11
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, 0xc090cc00
-; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[0:1], v[6:7]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[14:15], s[4:5], v[8:9]
-; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[0:1], v[8:9]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[6:7]
; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[2:3], v[8:9]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[0:1], v[6:7]
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[0:1], v[8:9]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff00000
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[8:9]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GFX900-SDAG-NEXT: s_and_b64 vcc, s[14:15], vcc
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[10:11]
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[14:15], vcc
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v1
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[12:13], s[6:7]
@@ -3944,9 +3944,9 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[18:19], v[14:15]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[18:19], v[16:17]
-; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[12:13]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[12:13]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[6:7], v[14:15], v[12:13]
@@ -3996,42 +3996,42 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[8:9], v[18:19], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], 1.0
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[0:1]
; GFX900-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[16:17], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v16, v[0:1]
; GFX900-GISEL-NEXT: v_fma_f64 v[0:1], v[10:11], v[12:13], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v11, v[4:5]
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v14, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v15, 0x40900000
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v16
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[14:15]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[14:15]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v11
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[6:7], s[2:3], v[14:15]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v17, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v11, v[4:5]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[6:7], v14
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[8:9], v10
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff00000
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0xc090cc00
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[8:9]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[4:5], v[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, v17, v5, s[6:7]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[6:7], s[2:3], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[8:9]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[8:9]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[8:9]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v5, s[6:7]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[8:9]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[8:9]
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <3 x double> @llvm.exp2.v3f64(<3 x double> %in)
@@ -4169,12 +4169,12 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[2:3], v[8:9], s[22:23]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v6, v[15:16]
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[2:3], v[8:9], s[24:25]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[19:20]
+; SI-SDAG-NEXT: v_mov_b32_e32 v13, 0
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[2:3], v[8:9], s[26:27]
; SI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[2:3], v[8:9], s[28:29]
-; SI-SDAG-NEXT: v_mov_b32_e32 v13, 0
; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0xc090cc00
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[19:20]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v15, v17, v5, s[10:11]
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], v[8:9], 1.0
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
@@ -4336,7 +4336,6 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[18:19], v[14:15], v[34:35]
; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v22, v[0:1]
; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[18:19], v[14:15], v[16:17]
-; SI-GISEL-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[18:19], v[14:15], v[30:31]
; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v22
; SI-GISEL-NEXT: v_fma_f64 v[14:15], v[18:19], v[14:15], v[36:37]
@@ -4349,42 +4348,43 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[16:17]
; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x7ff00000
; SI-GISEL-NEXT: v_cndmask_b32_e32 v19, 0, v4, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, v18, v5, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v20, v18, v5, vcc
+; SI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[10:11], v8
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[16:17]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[14:15], v[30:31]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, v18, v5, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v8, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v20, v18, v9, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[4:5]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[14:15], v[30:31]
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v12
; SI-GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v19, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v20, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[4:5]
-; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v12
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], v[36:37]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v20, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[16:17]
-; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[6:7], v[8:9], v[36:37]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v0, vcc
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v13
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v15, v18, v1, vcc
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[8:9], 1.0
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[4:5]
; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], 1.0
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v14, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v12, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v15, vcc
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v15, vcc
; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[16:17]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v13
+; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v14
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[4:5]
-; SI-GISEL-NEXT: v_readfirstlane_b32 s1, v10
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v10
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v11
-; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v12
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v11
; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v3
-; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v6
; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v0
; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
; SI-GISEL-NEXT: ; return to shader part epilog
@@ -4492,16 +4492,19 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_fma_f64 v[0:1], v[16:17], v[14:15], 1.0
; VI-SDAG-NEXT: v_mov_b32_e32 v18, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v19, 0x40900000
-; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; VI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[12:13], v6
; VI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v10
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[8:9]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[18:19]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[20:21], vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[20:21]
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[8:9]
+; VI-SDAG-NEXT: v_readfirstlane_b32 s7, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v7, v11, v7, s[10:11]
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, v11, v1, s[12:13]
; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[14:15]
; VI-SDAG-NEXT: v_readfirstlane_b32 s1, v1
@@ -4509,11 +4512,8 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: s_and_b64 vcc, s[18:19], s[8:9]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[16:17], s[10:11]
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v7, v11, v7, s[10:11]
-; VI-SDAG-NEXT: v_readfirstlane_b32 s7, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
; VI-SDAG-NEXT: s_and_b64 vcc, s[14:15], s[12:13]
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[18:19]
; VI-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, v7, s[16:17]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_readfirstlane_b32 s3, v7
@@ -4538,8 +4538,9 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_add_f64 v[12:13], s[2:3], -v[2:3]
; VI-GISEL-NEXT: v_add_f64 v[16:17], s[4:5], -v[6:7]
; VI-GISEL-NEXT: v_add_f64 v[18:19], s[6:7], -v[8:9]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[2:3]
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v7, v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_mul_f64 v[14:15], v[4:5], v[10:11]
; VI-GISEL-NEXT: v_mul_f64 v[22:23], v[12:13], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[20:21], v[14:15]
@@ -4607,54 +4608,53 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[18:19], v[4:5], v[18:19], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[24:25], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], 1.0
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v24, v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v25, 0x7ff00000
+; VI-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[18:19], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v18, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[0:1], v[14:15], v[22:23], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[10:11], v[16:17], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[6:7]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[18:19]
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[6:7], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v24
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[2:3]
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[12:13], v26
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v14
-; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[2:3], v[18:19]
+; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v24
; VI-GISEL-NEXT: v_mov_b32_e32 v20, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[12:13], v14
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[10:11], v7
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v25, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v25, v1, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[12:13]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v25, v3, s[12:13]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[20:21]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[6:7], v[20:21]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v7, v25, v7, s[8:9]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[20:21]
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[20:21]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[12:13]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v7, s[8:9]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[10:11]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[12:13]
-; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
-; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
-; VI-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[20:21]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
-; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; VI-GISEL-NEXT: ; return to shader part epilog
;
; GFX900-SDAG-LABEL: s_exp2_v4f64:
@@ -4760,16 +4760,19 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_fma_f64 v[0:1], v[16:17], v[14:15], 1.0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v18, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v19, 0x40900000
-; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[4:5], v[18:19]
; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[18:19]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[0:1], v[18:19]
; GFX900-SDAG-NEXT: v_ldexp_f64 v[6:7], v[12:13], v6
; GFX900-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[8:9]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[18:19]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[20:21], vcc
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[20:21]
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v5, s[8:9]
+; GFX900-SDAG-NEXT: v_readfirstlane_b32 s7, v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v7, v11, v7, s[10:11]
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, v11, v1, s[12:13]
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[14:15]
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s1, v1
@@ -4777,11 +4780,8 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[18:19], s[8:9]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[16:17], s[10:11]
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v7, v11, v7, s[10:11]
-; GFX900-SDAG-NEXT: v_readfirstlane_b32 s7, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
; GFX900-SDAG-NEXT: s_and_b64 vcc, s[14:15], s[12:13]
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[18:19]
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, v7, s[16:17]
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX900-SDAG-NEXT: v_readfirstlane_b32 s3, v7
@@ -4806,8 +4806,9 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_add_f64 v[12:13], s[2:3], -v[2:3]
; GFX900-GISEL-NEXT: v_add_f64 v[16:17], s[4:5], -v[6:7]
; GFX900-GISEL-NEXT: v_add_f64 v[18:19], s[6:7], -v[8:9]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v26, v[2:3]
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[8:9]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[6:7]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v7, v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_mul_f64 v[14:15], v[4:5], v[10:11]
; GFX900-GISEL-NEXT: v_mul_f64 v[22:23], v[12:13], v[10:11]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[20:21], v[14:15]
@@ -4875,54 +4876,53 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[18:19], v[4:5], v[18:19], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[20:21], v[12:13], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[22:23], v[14:15], v[24:25], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], 1.0
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v24, v[0:1]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v25, 0x7ff00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[16:17], v[10:11], v[16:17], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[18:19], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v18, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v19, 0x40900000
+; GFX900-GISEL-NEXT: v_fma_f64 v[12:13], v[12:13], v[20:21], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[0:1], v[14:15], v[22:23], 1.0
-; GFX900-GISEL-NEXT: v_fma_f64 v[2:3], v[10:11], v[16:17], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[6:7]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[18:19]
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[12:13], s[6:7], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v24
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v14, v[2:3]
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[18:19]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[12:13], v26
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v14
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 s[8:9], s[2:3], v[18:19]
+; GFX900-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[16:17], 1.0
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v20, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v21, 0xc090cc00
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[12:13], v14
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[6:7], v[10:11], v7
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[2:3], v[18:19]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v25, v5, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v25, v1, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[12:13]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v25, v3, s[12:13]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[20:21]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[12:13], s[6:7], v[20:21]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v7, v25, v7, s[8:9]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[18:19]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[18:19]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[0:1], v[20:21]
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[8:9], s[2:3], v[20:21]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[12:13]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[2:3], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v7, s[8:9]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[10:11]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[12:13]
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v4
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v6
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, s[6:7], v[20:21]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v1
-; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v7
; GFX900-GISEL-NEXT: ; return to shader part epilog
%result = call <4 x double> @llvm.exp2.v4f64(<4 x double> %in)
%cast = bitcast <4 x double> %result to <8 x i32>
@@ -5163,20 +5163,20 @@ define double @v_exp2_fabs_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_fabs_f64:
@@ -5277,20 +5277,20 @@ define double @v_exp2_fabs_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%result = call double @llvm.exp2.f64(double %fabs)
@@ -5531,20 +5531,20 @@ define double @v_exp2_fneg_fabs_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -|v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -|v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -|v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_fneg_fabs_f64:
@@ -5645,20 +5645,20 @@ define double @v_exp2_fneg_fabs_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -|v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -|v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -|v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%fneg.fabs = fneg double %fabs
@@ -5900,20 +5900,20 @@ define double @v_exp2_fneg_f64(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_fneg_f64:
@@ -6014,20 +6014,20 @@ define double @v_exp2_fneg_f64(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], -v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, -v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fneg = fneg double %in
%result = call double @llvm.exp2.f64(double %fneg)
@@ -6216,6 +6216,7 @@ define double @v_exp2_f64_fast(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -6249,13 +6250,12 @@ define double @v_exp2_f64_fast(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_fast:
@@ -6318,6 +6318,7 @@ define double @v_exp2_f64_fast(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -6351,13 +6352,12 @@ define double @v_exp2_f64_fast(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call fast double @llvm.exp2.f64(double %in)
ret double %result
@@ -6595,20 +6595,20 @@ define double @v_exp2_f64_afn(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_afn:
@@ -6709,20 +6709,20 @@ define double @v_exp2_f64_afn(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call afn double @llvm.exp2.f64(double %in)
ret double %result
@@ -6910,6 +6910,7 @@ define double @v_exp2_f64_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -6943,13 +6944,12 @@ define double @v_exp2_f64_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_ninf:
@@ -7012,6 +7012,7 @@ define double @v_exp2_f64_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -7045,13 +7046,12 @@ define double @v_exp2_f64_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call ninf double @llvm.exp2.f64(double %in)
ret double %result
@@ -7289,20 +7289,20 @@ define double @v_exp2_f64_nnan(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_nnan:
@@ -7403,20 +7403,20 @@ define double @v_exp2_f64_nnan(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call nnan double @llvm.exp2.f64(double %in)
ret double %result
@@ -7656,20 +7656,20 @@ define double @v_fabs_exp2_f64_afn(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_exp2_f64_afn:
@@ -7770,20 +7770,20 @@ define double @v_fabs_exp2_f64_afn(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], |v[0:1]|, v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs = call double @llvm.fabs.f64(double %in)
%result = call afn double @llvm.exp2.f64(double %fabs)
@@ -7972,6 +7972,7 @@ define double @v_exp2_f64_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -8005,13 +8006,12 @@ define double @v_exp2_f64_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_nnan_ninf:
@@ -8074,6 +8074,7 @@ define double @v_exp2_f64_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -8107,13 +8108,12 @@ define double @v_exp2_f64_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call nnan ninf double @llvm.exp2.f64(double %in)
ret double %result
@@ -8385,20 +8385,20 @@ define double @v_exp2_f64_from_fpext_f16(half %src) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_f16:
@@ -8503,20 +8503,20 @@ define double @v_exp2_f64_from_fpext_f16(half %src) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %src to double
%result = call double @llvm.exp2.f64(double %fpext)
@@ -8759,20 +8759,20 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
@@ -8875,20 +8875,20 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext float %src to double
%result = call double @llvm.exp2.f64(double %fpext)
@@ -9145,20 +9145,20 @@ define double @v_exp2_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_math_f16:
@@ -9265,20 +9265,20 @@ define double @v_exp2_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to double
@@ -9518,20 +9518,20 @@ define double @v_exp2_f64_contract(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_contract:
@@ -9632,20 +9632,20 @@ define double @v_exp2_f64_contract(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7ff00000
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call contract double @llvm.exp2.f64(double %in)
ret double %result
@@ -9833,6 +9833,7 @@ define double @v_exp2_f64_contract_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -9866,13 +9867,12 @@ define double @v_exp2_f64_contract_nnan_ninf(double %in) #0 {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp2_f64_contract_nnan_ninf:
@@ -9935,6 +9935,7 @@ define double @v_exp2_f64_contract_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
@@ -9968,13 +9969,12 @@ define double @v_exp2_f64_contract_nnan_ninf(double %in) #0 {
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v6, v[2:3]
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc090cc00
-; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call contract nnan ninf double @llvm.exp2.f64(double %in)
ret double %result
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index 53b862e8bab2f..b366c64e2db95 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -205,8 +205,8 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL-NEXT: v_not_b32_e32 v2, 63
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; SI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
; SI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
@@ -254,8 +254,8 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: v_not_b32_e32 v2, 63
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
; VI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
@@ -302,8 +302,8 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL-NEXT: v_not_b32_e32 v2, 63
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s11, v0
@@ -711,8 +711,8 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; SI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
@@ -721,9 +721,9 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; SI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
; SI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
@@ -788,8 +788,8 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
@@ -798,9 +798,9 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v5
; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v5
; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
; VI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
@@ -864,8 +864,8 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
@@ -874,9 +874,9 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
index e8bf198f89855..87bb971ae5b8d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
@@ -44,12 +44,12 @@ define amdgpu_kernel void @fma_f16(
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_readfirstlane_b32 s0, v1
; SI-NEXT: s_and_b32 s1, s0, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s1, v0
; SI-NEXT: s_lshr_b32 s3, s0, 8
; SI-NEXT: s_bfe_u32 s4, s0, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s1, v0
; SI-NEXT: s_and_b32 s1, s3, 0xffe
; SI-NEXT: s_sub_i32 s3, 0x3f1, s4
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s3, 0, 13
; SI-NEXT: v_readfirstlane_b32 s3, v0
@@ -184,12 +184,12 @@ define amdgpu_kernel void @fma_f16_imm_a(
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b32 s5, s4, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_lshr_b32 s7, s4, 8
; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_and_b32 s5, s7, 0xffe
; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s7, 0, 13
; SI-NEXT: v_readfirstlane_b32 s7, v0
@@ -312,12 +312,12 @@ define amdgpu_kernel void @fma_f16_imm_b(
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b32 s5, s4, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_lshr_b32 s7, s4, 8
; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_and_b32 s5, s7, 0xffe
; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s7, 0, 13
; SI-NEXT: v_readfirstlane_b32 s7, v0
@@ -440,12 +440,12 @@ define amdgpu_kernel void @fma_f16_imm_c(
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[4:5]
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b32 s5, s4, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_lshr_b32 s7, s4, 8
; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_and_b32 s5, s7, 0xffe
; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s7, 0, 13
; SI-NEXT: v_readfirstlane_b32 s7, v0
@@ -584,12 +584,12 @@ define amdgpu_kernel void @fma_v2f16(
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_readfirstlane_b32 s0, v1
; SI-NEXT: s_and_b32 s1, s0, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s1, v0
; SI-NEXT: s_lshr_b32 s3, s0, 8
; SI-NEXT: s_bfe_u32 s4, s0, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s1, v0
; SI-NEXT: s_and_b32 s1, s3, 0xffe
; SI-NEXT: s_sub_i32 s3, 0x3f1, s4
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s3, 0, 13
; SI-NEXT: v_readfirstlane_b32 s3, v0
@@ -623,12 +623,12 @@ define amdgpu_kernel void @fma_v2f16(
; SI-NEXT: s_cmpk_eq_i32 s4, 0x40f
; SI-NEXT: s_cselect_b32 s1, s1, s3
; SI-NEXT: s_and_b32 s3, s5, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s3, v2
; SI-NEXT: s_lshr_b32 s0, s0, 16
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s3, v2
; SI-NEXT: s_lshr_b32 s4, s5, 8
; SI-NEXT: s_bfe_u32 s6, s5, 0xb0014
; SI-NEXT: s_and_b32 s0, s0, 0x8000
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: s_and_b32 s3, s4, 0xffe
; SI-NEXT: s_sub_i32 s4, 0x3f1, s6
@@ -784,12 +784,12 @@ define amdgpu_kernel void @fma_v2f16_imm_a(
; SI-NEXT: v_fma_f64 v[2:3], v[6:7], s[4:5], v[4:5]
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b32 s5, s4, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_lshr_b32 s7, s4, 8
; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_and_b32 s5, s7, 0xffe
; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s7, 0, 13
; SI-NEXT: v_readfirstlane_b32 s7, v0
@@ -822,12 +822,12 @@ define amdgpu_kernel void @fma_v2f16_imm_a(
; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
; SI-NEXT: s_cselect_b32 s5, s5, s7
; SI-NEXT: s_and_b32 s7, s9, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s7, v2
; SI-NEXT: s_lshr_b32 s4, s4, 16
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s7, v2
; SI-NEXT: s_lshr_b32 s8, s9, 8
; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: s_and_b32 s7, s8, 0xffe
; SI-NEXT: s_sub_i32 s8, 0x3f1, s10
@@ -969,12 +969,12 @@ define amdgpu_kernel void @fma_v2f16_imm_b(
; SI-NEXT: v_fma_f64 v[2:3], v[6:7], s[4:5], v[4:5]
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b32 s5, s4, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_lshr_b32 s7, s4, 8
; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_and_b32 s5, s7, 0xffe
; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s7, 0, 13
; SI-NEXT: v_readfirstlane_b32 s7, v0
@@ -1007,12 +1007,12 @@ define amdgpu_kernel void @fma_v2f16_imm_b(
; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
; SI-NEXT: s_cselect_b32 s5, s5, s7
; SI-NEXT: s_and_b32 s7, s9, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s7, v2
; SI-NEXT: s_lshr_b32 s4, s4, 16
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s7, v2
; SI-NEXT: s_lshr_b32 s8, s9, 8
; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: s_and_b32 s7, s8, 0xffe
; SI-NEXT: s_sub_i32 s8, 0x3f1, s10
@@ -1154,12 +1154,12 @@ define amdgpu_kernel void @fma_v2f16_imm_c(
; SI-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], s[4:5]
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b32 s5, s4, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_lshr_b32 s7, s4, 8
; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
; SI-NEXT: s_and_b32 s5, s7, 0xffe
; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_med3_i32 v1, s7, 0, 13
; SI-NEXT: v_readfirstlane_b32 s7, v0
@@ -1192,12 +1192,12 @@ define amdgpu_kernel void @fma_v2f16_imm_c(
; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
; SI-NEXT: s_cselect_b32 s5, s5, s7
; SI-NEXT: s_and_b32 s7, s9, 0x1ff
-; SI-NEXT: v_or_b32_e32 v0, s7, v2
; SI-NEXT: s_lshr_b32 s4, s4, 16
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_or_b32_e32 v0, s7, v2
; SI-NEXT: s_lshr_b32 s8, s9, 8
; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: s_and_b32 s7, s8, 0xffe
; SI-NEXT: s_sub_i32 s8, 0x3f1, s10
@@ -1355,12 +1355,12 @@ define amdgpu_kernel void @fma_v4f16(
; SI-NEXT: v_fma_f64 v[2:3], v[15:16], v[13:14], v[11:12]
; SI-NEXT: s_and_b32 s3, s0, 0x1ff
; SI-NEXT: v_readfirstlane_b32 s1, v3
-; SI-NEXT: v_or_b32_e32 v3, s3, v5
; SI-NEXT: s_lshr_b32 s4, s0, 8
; SI-NEXT: s_bfe_u32 s5, s0, 0xb0014
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: v_or_b32_e32 v3, s3, v5
; SI-NEXT: s_and_b32 s3, s4, 0xffe
; SI-NEXT: s_sub_i32 s4, 0x3f1, s5
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_med3_i32 v5, s4, 0, 13
; SI-NEXT: v_readfirstlane_b32 s4, v3
@@ -1397,12 +1397,12 @@ define amdgpu_kernel void @fma_v4f16(
; SI-NEXT: s_cmpk_eq_i32 s5, 0x40f
; SI-NEXT: s_cselect_b32 s3, s3, s4
; SI-NEXT: s_and_b32 s4, s6, 0x1ff
-; SI-NEXT: v_or_b32_e32 v3, s4, v7
; SI-NEXT: s_lshr_b32 s0, s0, 16
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: v_or_b32_e32 v3, s4, v7
; SI-NEXT: s_lshr_b32 s5, s6, 8
; SI-NEXT: s_bfe_u32 s7, s6, 0xb0014
; SI-NEXT: s_and_b32 s0, s0, 0x8000
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: s_and_b32 s4, s5, 0xffe
; SI-NEXT: s_sub_i32 s5, 0x3f1, s7
@@ -1437,14 +1437,14 @@ define amdgpu_kernel void @fma_v4f16(
; SI-NEXT: s_cselect_b32 s3, s2, 0x7c00
; SI-NEXT: s_cmpk_eq_i32 s7, 0x40f
; SI-NEXT: s_cselect_b32 s3, s3, s4
-; SI-NEXT: s_and_b32 s5, s1, 0x1ff
; SI-NEXT: s_lshr_b32 s4, s6, 16
-; SI-NEXT: v_or_b32_e32 v2, s5, v2
+; SI-NEXT: s_and_b32 s5, s1, 0x1ff
; SI-NEXT: s_and_b32 s4, s4, 0x8000
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; SI-NEXT: v_or_b32_e32 v2, s5, v2
; SI-NEXT: s_lshr_b32 s6, s1, 8
; SI-NEXT: s_bfe_u32 s7, s1, 0xb0014
; SI-NEXT: s_or_b32 s3, s4, s3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: s_and_b32 s5, s6, 0xffe
; SI-NEXT: s_sub_i32 s6, 0x3f1, s7
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index e239f37a8c055..bcdcbea44844c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -385,12 +385,12 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-SDAG-NEXT: v_frexp_mant_f32_e32 v2, v3
-; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s4
; GFX6-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v3|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5]
; GFX6-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v1, v3
@@ -1456,8 +1456,8 @@ define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) {
; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX6-SDAG-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s4
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v5, v1, v2, s[4:5]
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, v1
@@ -1866,11 +1866,11 @@ define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) {
; GFX6-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v6
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v8, v0, v4, vcc
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v9, v1, v5, vcc
-; GFX6-SDAG-NEXT: v_and_b32_e32 v6, 0x7fffffff, v3
; GFX6-SDAG-NEXT: v_frexp_mant_f64_e32 v[4:5], v[2:3]
-; GFX6-SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v6
+; GFX6-SDAG-NEXT: v_and_b32_e32 v6, 0x7fffffff, v3
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v1, v[2:3]
+; GFX6-SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v6
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v6, v2, v4, s[4:5]
; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v7, v3, v5, s[4:5]
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
index 52e9474f46777..fc409c98b52e4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
@@ -1018,8 +1018,8 @@ define <2 x i1> @isnan_v2bf16(<2 x bfloat> %x) nounwind {
; GFX9CHECK-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
-; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v1, s4 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v1, s4 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
@@ -1029,8 +1029,8 @@ define <2 x i1> @isnan_v2bf16(<2 x bfloat> %x) nounwind {
; GFX10CHECK-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX10CHECK-NEXT: v_mov_b32_e32 v2, 0x7f80
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1
-; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
@@ -1098,8 +1098,8 @@ define <3 x i1> @isnan_v3bf16(<3 x bfloat> %x) nounwind {
; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
-; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v3, s4 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v3, s4 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
@@ -1110,10 +1110,10 @@ define <3 x i1> @isnan_v3bf16(<3 x bfloat> %x) nounwind {
; GFX10CHECK-NEXT: v_mov_b32_e32 v3, 0x7f80
; GFX10CHECK-NEXT: v_and_b32_e32 v4, 0x7fff, v1
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2
-; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v2, v3 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4
+; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v2, v3 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
@@ -1194,9 +1194,9 @@ define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) nounwind {
; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v1, s6 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s6, v3
+; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v3, s6 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
@@ -1210,9 +1210,9 @@ define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) nounwind {
; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v3, v5 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4
+; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v4, v5 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
@@ -1236,9 +1236,9 @@ define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) nounwind {
; GFX11SELDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11SELDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX11SELDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1
-; GFX11SELDAG-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0
; GFX11SELDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11SELDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11SELDAG-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index b3224dd565fe5..b513fb222ffa5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -1370,8 +1370,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX9SELDAG: ; %bb.0:
; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9SELDAG-NEXT: v_cmp_u_f16_sdwa s[4:5], v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1390,8 +1390,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX10SELDAG: ; %bb.0:
; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
-; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, v2
; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1403,8 +1403,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v1 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v2
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v2
; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-TRUE16-LABEL: isnan_v2f16:
@@ -1413,8 +1413,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.h, v0.h
-; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-FAKE16-LABEL: isnan_v2f16:
@@ -1435,8 +1435,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX11GLISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.h, v3.l
-; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11GLISEL-FAKE16-LABEL: isnan_v2f16:
@@ -1517,8 +1517,8 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX9SELDAG: ; %bb.0:
; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9SELDAG-NEXT: v_cmp_u_f16_sdwa s[4:5], v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v1, v1
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
@@ -1543,12 +1543,12 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX10SELDAG: ; %bb.0:
; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
-; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v3
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v3
; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10GLISEL-LABEL: isnan_v3f16:
@@ -1558,11 +1558,11 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v1, 3
-; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v3
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
+; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v3
; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-TRUE16-LABEL: isnan_v3f16:
@@ -1573,8 +1573,8 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.l, v1.l
-; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-FAKE16-LABEL: isnan_v3f16:
@@ -1586,8 +1586,8 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11SELDAG-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v2, v2
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11SELDAG-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
-; GFX11SELDAG-FAKE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11SELDAG-FAKE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11SELDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11GLISEL-TRUE16-LABEL: isnan_v3f16:
@@ -1599,11 +1599,10 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11GLISEL-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.h, v3.l
-; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v4
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v1.l, v5.l
-; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11GLISEL-FAKE16-LABEL: isnan_v3f16:
@@ -1615,8 +1614,8 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11GLISEL-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v2, 3
; GFX11GLISEL-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11GLISEL-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v1, 3
-; GFX11GLISEL-FAKE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11GLISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11GLISEL-FAKE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11GLISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%1 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> %x, i32 3) ; nan
ret <3 x i1> %1
@@ -1701,12 +1700,12 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX9SELDAG: ; %bb.0:
; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9SELDAG-NEXT: v_cmp_u_f16_sdwa s[4:5], v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
; GFX9SELDAG-NEXT: v_cmp_u_f16_sdwa s[4:5], v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v1, v1
-; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v4
; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
@@ -1731,14 +1730,14 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX10SELDAG: ; %bb.0:
; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
+; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
-; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v4
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v4
; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10GLISEL-LABEL: isnan_v4f16:
@@ -1748,13 +1747,13 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v3 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v1, 3
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v1, v3 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v5
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
+; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v5
; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-TRUE16-LABEL: isnan_v4f16:
@@ -1767,16 +1766,16 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.l, v1.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.h, v1.h
-; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, v4
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, v4
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-FAKE16-LABEL: isnan_v4f16:
; GFX11SELDAG-FAKE16: ; %bb.0:
; GFX11SELDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX11SELDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11SELDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11SELDAG-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
@@ -1798,19 +1797,18 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.h, v3.l
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v1.l, v6.l
-; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v4
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v1.h, v7.l
-; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, v5
; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11GLISEL-FAKE16-LABEL: isnan_v4f16:
; GFX11GLISEL-FAKE16: ; %bb.0:
; GFX11GLISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11GLISEL-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v0, 3
; GFX11GLISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11GLISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX11GLISEL-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v0, 3
; GFX11GLISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11GLISEL-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v1, 3
; GFX11GLISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index cef8aa0c8dd38..4496e59c3955e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -889,13 +889,13 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s4
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s5
; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s5
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
@@ -925,11 +925,11 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
@@ -1157,9 +1157,9 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_log_f32_e32 v5, v5
; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7
; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v5
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; SI-GISEL-NEXT: v_fma_f32 v8, v5, v2, -v7
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -1287,9 +1287,9 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v6, v3, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
@@ -1405,9 +1405,9 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v6
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v2, -v8
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -1436,11 +1436,11 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s3
-; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s6
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
@@ -1487,16 +1487,16 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x41b17218, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
@@ -1798,8 +1798,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v1
; SI-GISEL-NEXT: v_fma_f32 v8, v1, v3, -v7
; SI-GISEL-NEXT: v_fma_f32 v8, v1, v4, v8
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 5, v8
; SI-GISEL-NEXT: v_ldexp_f32_e32 v8, s10, v8
@@ -1807,9 +1807,9 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SI-GISEL-NEXT: v_fma_f32 v9, v8, v3, -v7
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -1960,8 +1960,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6
; VI-GISEL-NEXT: v_ldexp_f32 v6, s10, v6
@@ -1972,9 +1972,9 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v6
; VI-GISEL-NEXT: v_sub_f32_e32 v7, v6, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7
@@ -2108,8 +2108,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v1
; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v3, -v8
; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v9, 5, v9
; GFX900-GISEL-NEXT: v_ldexp_f32 v9, s10, v9
@@ -2117,9 +2117,9 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v9
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v3, -v8
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -2149,9 +2149,9 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s6
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s7
@@ -2208,24 +2208,23 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s6
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s6
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s7
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x41b17218, s8
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x41b17218, s9
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
@@ -2467,8 +2466,8 @@ define float @v_log_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -2563,8 +2562,8 @@ define float @v_log_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -2667,8 +2666,8 @@ define float @v_log_fabs_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -2763,8 +2762,8 @@ define float @v_log_fabs_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -2869,8 +2868,8 @@ define float @v_log_fneg_fabs_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -2965,8 +2964,8 @@ define float @v_log_fneg_fabs_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -3072,8 +3071,8 @@ define float @v_log_fneg_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -3168,8 +3167,8 @@ define float @v_log_fneg_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -3389,8 +3388,8 @@ define float @v_log_f32_ninf(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -3485,8 +3484,8 @@ define float @v_log_f32_ninf(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -4106,8 +4105,8 @@ define float @v_log_f32_nnan(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -4202,8 +4201,8 @@ define float @v_log_f32_nnan(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -4446,8 +4445,8 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -4542,8 +4541,8 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -4786,8 +4785,8 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -4882,8 +4881,8 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -5472,8 +5471,8 @@ define float @v_log_f32_dynamic_mode(float %in) #1 {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -5568,8 +5567,8 @@ define float @v_log_f32_dynamic_mode(float %in) #1 {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -6113,8 +6112,8 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -6162,8 +6161,8 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 7da9a6a9e4eea..c31d46b1a7a7f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -889,13 +889,13 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s4
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s5
; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s5
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
@@ -925,11 +925,11 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
@@ -1157,9 +1157,9 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: v_log_f32_e32 v5, v5
; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b
; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7
; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v5
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; SI-GISEL-NEXT: v_fma_f32 v8, v5, v2, -v7
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -1287,9 +1287,9 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v6, v3, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
@@ -1405,9 +1405,9 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v6
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v2, -v8
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -1436,11 +1436,11 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s3
-; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s6
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
@@ -1487,16 +1487,16 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x411a209b, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
@@ -1798,8 +1798,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v1
; SI-GISEL-NEXT: v_fma_f32 v8, v1, v3, -v7
; SI-GISEL-NEXT: v_fma_f32 v8, v1, v4, v8
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 5, v8
; SI-GISEL-NEXT: v_ldexp_f32_e32 v8, s10, v8
@@ -1807,9 +1807,9 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SI-GISEL-NEXT: v_fma_f32 v9, v8, v3, -v7
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -1960,8 +1960,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6
; VI-GISEL-NEXT: v_ldexp_f32 v6, s10, v6
@@ -1972,9 +1972,9 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v6
; VI-GISEL-NEXT: v_sub_f32_e32 v7, v6, v5
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7
@@ -2108,8 +2108,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v1
; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v3, -v8
; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v9, 5, v9
; GFX900-GISEL-NEXT: v_ldexp_f32 v9, s10, v9
@@ -2117,9 +2117,9 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v9
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v3, -v8
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -2149,9 +2149,9 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s6
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s7
@@ -2208,24 +2208,23 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s6
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s6
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s7
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x411a209b, s8
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x411a209b, s9
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
@@ -2467,8 +2466,8 @@ define float @v_log10_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -2563,8 +2562,8 @@ define float @v_log10_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -2667,8 +2666,8 @@ define float @v_log10_fabs_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -2763,8 +2762,8 @@ define float @v_log10_fabs_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -2869,8 +2868,8 @@ define float @v_log10_fneg_fabs_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -2965,8 +2964,8 @@ define float @v_log10_fneg_fabs_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -3072,8 +3071,8 @@ define float @v_log10_fneg_f32(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -3168,8 +3167,8 @@ define float @v_log10_fneg_f32(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -3389,8 +3388,8 @@ define float @v_log10_f32_ninf(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -3485,8 +3484,8 @@ define float @v_log10_f32_ninf(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -4106,8 +4105,8 @@ define float @v_log10_f32_nnan(float %in) {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -4202,8 +4201,8 @@ define float @v_log10_f32_nnan(float %in) {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -4446,8 +4445,8 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -4542,8 +4541,8 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -4786,8 +4785,8 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -4882,8 +4881,8 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -5472,8 +5471,8 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -5568,8 +5567,8 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -6113,8 +6112,8 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -6162,8 +6161,8 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index b2ec9534aa848..998048b14c2b8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -250,8 +250,8 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
@@ -302,8 +302,8 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
@@ -354,8 +354,8 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
@@ -376,10 +376,10 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s4
-; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s5
+; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
@@ -400,21 +400,20 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 5, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
@@ -524,32 +523,32 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; SI-GISEL-LABEL: s_log2_v3f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, s9, v3
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v3
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, s1, v3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; SI-GISEL-NEXT: v_log_f32_e32 v3, v3
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
; SI-GISEL-NEXT: v_log_f32_e32 v4, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; SI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -594,34 +593,34 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
;
; VI-GISEL-LABEL: s_log2_v3f32:
; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v3
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v4
+; VI-GISEL-NEXT: v_ldexp_f32 v3, s1, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3
-; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
; VI-GISEL-NEXT: v_log_f32_e32 v4, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
;
@@ -701,10 +700,10 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s3
-; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s6
+; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s7
@@ -734,30 +733,29 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v6, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s3
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5
@@ -905,8 +903,8 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -916,10 +914,10 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -988,8 +986,8 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -999,10 +997,10 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[0:1]
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -1072,8 +1070,8 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
@@ -1083,10 +1081,10 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v3, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5
; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
@@ -1148,36 +1146,37 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s9
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s8
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v0, 5, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v3, v3, v7 :: v_dual_lshlrev_b32 v2, 5, v2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
index a60741905bdbd..9e1ff01276089 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
@@ -792,8 +792,8 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v2, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -970,8 +970,8 @@ define <2 x half> @v_maximum_v2f16__nsz(<2 x half> %src0, <2 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v2, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -1165,12 +1165,12 @@ define void @s_maximum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) {
; GFX10-LABEL: s_maximum_v2f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_max_f16 v0, s16, s17
; GFX10-NEXT: s_lshr_b32 s4, s17, 16
; GFX10-NEXT: s_lshr_b32 s5, s16, 16
-; GFX10-NEXT: v_pk_max_f16 v0, s16, s17
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s5, s4
; GFX10-NEXT: v_cmp_o_f16_e64 s4, s16, s17
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0x7e00, v0, s4
; GFX10-NEXT: v_cndmask_b32_sdwa v0, v1, v0, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
@@ -1321,8 +1321,8 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v2
-; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_pk_max_f16 v4, v1, v3
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1535,8 +1535,8 @@ define <3 x half> @v_maximum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v2
-; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_pk_max_f16 v4, v1, v3
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1773,11 +1773,11 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_e64 s5, v0, v2
; GFX10-NEXT: v_cndmask_b32_sdwa v2, v4, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
; GFX10-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -2028,11 +2028,11 @@ define <4 x half> @v_maximum_v4f16__nsz(<4 x half> %src0, <4 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_e64 s5, v0, v2
; GFX10-NEXT: v_cndmask_b32_sdwa v2, v4, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
; GFX10-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
index ec8b1f37ca5e4..381f18c29ba5b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
@@ -1843,7 +1843,6 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX7-NEXT: v_max_f32_e32 v2, v2, v18
; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000
; GFX7-NEXT: v_max_f32_e32 v18, v13, v29
-; GFX7-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX7-NEXT: v_cmp_o_f32_e64 s[8:9], v3, v19
; GFX7-NEXT: v_max_f32_e32 v3, v3, v19
; GFX7-NEXT: v_cmp_o_f32_e64 s[10:11], v4, v20
@@ -1864,10 +1863,11 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX7-NEXT: v_max_f32_e32 v11, v11, v27
; GFX7-NEXT: v_cmp_o_f32_e64 s[26:27], v12, v28
; GFX7-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX7-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX7-NEXT: v_max_f32_e32 v19, v14, v30
-; GFX7-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v13, v17, v18, s[28:29]
+; GFX7-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX7-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
@@ -1899,7 +1899,6 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX8-NEXT: v_max_f32_e32 v2, v2, v18
; GFX8-NEXT: v_mov_b32_e32 v17, 0x7fc00000
; GFX8-NEXT: v_max_f32_e32 v18, v13, v29
-; GFX8-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX8-NEXT: v_cmp_o_f32_e64 s[8:9], v3, v19
; GFX8-NEXT: v_max_f32_e32 v3, v3, v19
; GFX8-NEXT: v_cmp_o_f32_e64 s[10:11], v4, v20
@@ -1920,10 +1919,11 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX8-NEXT: v_max_f32_e32 v11, v11, v27
; GFX8-NEXT: v_cmp_o_f32_e64 s[26:27], v12, v28
; GFX8-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX8-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX8-NEXT: v_max_f32_e32 v19, v14, v30
-; GFX8-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v13, v17, v18, s[28:29]
+; GFX8-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX8-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
@@ -1955,7 +1955,6 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX900-NEXT: v_max_f32_e32 v2, v2, v18
; GFX900-NEXT: v_mov_b32_e32 v17, 0x7fc00000
; GFX900-NEXT: v_max_f32_e32 v18, v13, v29
-; GFX900-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX900-NEXT: v_cmp_o_f32_e64 s[8:9], v3, v19
; GFX900-NEXT: v_max_f32_e32 v3, v3, v19
; GFX900-NEXT: v_cmp_o_f32_e64 s[10:11], v4, v20
@@ -1976,10 +1975,11 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX900-NEXT: v_max_f32_e32 v11, v11, v27
; GFX900-NEXT: v_cmp_o_f32_e64 s[26:27], v12, v28
; GFX900-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX900-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX900-NEXT: v_max_f32_e32 v19, v14, v30
-; GFX900-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v13, v17, v18, s[28:29]
+; GFX900-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX900-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[4:5]
; GFX900-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[6:7]
; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
index a98f22fdf72f2..8f05a23797d60 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
@@ -14,9 +14,9 @@ define double @v_maximum_f64(double %src0, double %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64:
@@ -24,9 +24,9 @@ define double @v_maximum_f64(double %src0, double %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64:
@@ -34,9 +34,9 @@ define double @v_maximum_f64(double %src0, double %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64:
@@ -144,9 +144,9 @@ define double @v_maximum_f64__nsz(double %src0, double %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64__nsz:
@@ -154,9 +154,9 @@ define double @v_maximum_f64__nsz(double %src0, double %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64__nsz:
@@ -164,9 +164,9 @@ define double @v_maximum_f64__nsz(double %src0, double %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64__nsz:
@@ -273,33 +273,33 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64__nnan_src0:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64__nnan_src0:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64__nnan_src0:
@@ -365,33 +365,33 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64__nnan_src1:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64__nnan_src1:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64__nnan_src1:
@@ -461,8 +461,8 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) {
; GFX7-NEXT: v_max_f64 v[2:3], s[16:17], v[0:1]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use v[0:1]
; GFX7-NEXT: ;;#ASMEND
@@ -476,8 +476,8 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) {
; GFX8-NEXT: v_max_f64 v[2:3], s[16:17], v[0:1]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v[0:1]
; GFX8-NEXT: ;;#ASMEND
@@ -491,8 +491,8 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) {
; GFX900-NEXT: v_max_f64 v[2:3], s[16:17], v[0:1]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[0:1]
; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use v[0:1]
; GFX900-NEXT: ;;#ASMEND
@@ -570,13 +570,13 @@ define <2 x double> @v_maximum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f64:
@@ -584,13 +584,13 @@ define <2 x double> @v_maximum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v2f64:
@@ -598,13 +598,13 @@ define <2 x double> @v_maximum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v2f64:
@@ -627,27 +627,27 @@ define <2 x double> @v_maximum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
+; GFX10-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v2f64:
@@ -734,13 +734,13 @@ define <2 x double> @v_maximum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f64__nsz:
@@ -748,13 +748,13 @@ define <2 x double> @v_maximum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v2f64__nsz:
@@ -762,13 +762,13 @@ define <2 x double> @v_maximum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v2f64__nsz:
@@ -791,27 +791,27 @@ define <2 x double> @v_maximum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
+; GFX10-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[10:11], v[2:3], v[6:7]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v2f64__nsz:
@@ -900,15 +900,15 @@ define void @s_maximum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX7-NEXT: v_mov_b32_e32 v1, s23
; GFX7-NEXT: v_max_f64 v[2:3], s[18:19], v[0:1]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[18:19], v[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v0, s20
-; GFX7-NEXT: v_mov_b32_e32 v1, s21
-; GFX7-NEXT: v_max_f64 v[4:5], s[16:17], v[0:1]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], v[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX7-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[6:7], s[16:17], v[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v6, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use v[0:3]
; GFX7-NEXT: ;;#ASMEND
@@ -921,15 +921,15 @@ define void @s_maximum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX8-NEXT: v_mov_b32_e32 v1, s23
; GFX8-NEXT: v_max_f64 v[2:3], s[18:19], v[0:1]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[18:19], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s20
-; GFX8-NEXT: v_mov_b32_e32 v1, s21
-; GFX8-NEXT: v_max_f64 v[4:5], s[16:17], v[0:1]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[6:7], s[16:17], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v[0:3]
; GFX8-NEXT: ;;#ASMEND
@@ -942,15 +942,15 @@ define void @s_maximum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX900-NEXT: v_mov_b32_e32 v1, s23
; GFX900-NEXT: v_max_f64 v[2:3], s[18:19], v[0:1]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, s[18:19], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v0, s20
-; GFX900-NEXT: v_mov_b32_e32 v1, s21
-; GFX900-NEXT: v_max_f64 v[4:5], s[16:17], v[0:1]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX900-NEXT: v_mov_b32_e32 v4, s20
+; GFX900-NEXT: v_mov_b32_e32 v5, s21
+; GFX900-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[6:7], s[16:17], v[4:5]
; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, v5, v6, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use v[0:3]
; GFX900-NEXT: ;;#ASMEND
@@ -980,13 +980,13 @@ define void @s_maximum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[0:1], s[18:19], s[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[18:19], s[22:23]
; GFX10-NEXT: v_max_f64 v[4:5], s[16:17], s[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, s[16:17], s[20:21]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[18:19], s[22:23]
; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, 0x7ff80000, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, s5
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[16:17], s[20:21]
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, s4
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use v[0:3]
; GFX10-NEXT: ;;#ASMEND
@@ -996,10 +996,10 @@ define void @s_maximum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], s[2:3], s[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, s[2:3], s[18:19]
; GFX11-NEXT: v_max_f64 v[4:5], s[0:1], s[16:17]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, s[2:3], s[18:19]
; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v1, 0x7ff80000, s2
; GFX11-NEXT: v_cndmask_b32_e64 v2, v0, 0, s2
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, s0
@@ -1043,17 +1043,17 @@ define <3 x double> @v_maximum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX7-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f64:
@@ -1061,17 +1061,17 @@ define <3 x double> @v_maximum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX8-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v3f64:
@@ -1079,17 +1079,17 @@ define <3 x double> @v_maximum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX900-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX900-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v3f64:
@@ -1117,34 +1117,35 @@ define <3 x double> @v_maximum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
+; GFX10-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX10-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
-; GFX10-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
+; GFX11-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX11-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
-; GFX11-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v3f64:
@@ -1240,17 +1241,17 @@ define <3 x double> @v_maximum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX7-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f64__nsz:
@@ -1258,17 +1259,17 @@ define <3 x double> @v_maximum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX8-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v3f64__nsz:
@@ -1276,17 +1277,17 @@ define <3 x double> @v_maximum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX900-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX900-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v3f64__nsz:
@@ -1314,34 +1315,35 @@ define <3 x double> @v_maximum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
+; GFX10-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX10-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
-; GFX10-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
+; GFX11-NEXT: v_max_f64 v[14:15], v[2:3], v[8:9]
+; GFX11-NEXT: v_max_f64 v[16:17], v[4:5], v[10:11]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
-; GFX11-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v3f64__nsz:
@@ -1437,21 +1439,21 @@ define <4 x double> @v_maximum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX7-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX7-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX7-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f64:
@@ -1459,21 +1461,21 @@ define <4 x double> @v_maximum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX8-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX8-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX8-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v4f64:
@@ -1481,21 +1483,21 @@ define <4 x double> @v_maximum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX900-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX900-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX900-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX900-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v4f64:
@@ -1528,42 +1530,42 @@ define <4 x double> @v_maximum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
+; GFX10-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
+; GFX10-NEXT: v_max_f64 v[20:21], v[4:5], v[12:13]
+; GFX10-NEXT: v_max_f64 v[22:23], v[6:7], v[14:15]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
-; GFX10-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
-; GFX10-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
+; GFX11-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
+; GFX11-NEXT: v_max_f64 v[20:21], v[4:5], v[12:13]
+; GFX11-NEXT: v_max_f64 v[22:23], v[6:7], v[14:15]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
-; GFX11-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
-; GFX11-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v4f64:
@@ -1668,21 +1670,21 @@ define <4 x double> @v_maximum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX7-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX7-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX7-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f64__nsz:
@@ -1690,21 +1692,21 @@ define <4 x double> @v_maximum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX8-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX8-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX8-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v4f64__nsz:
@@ -1712,21 +1714,21 @@ define <4 x double> @v_maximum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX900-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
+; GFX900-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX900-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX900-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX900-NEXT: v_max_f64 v[10:11], v[6:7], v[14:15]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v4f64__nsz:
@@ -1759,42 +1761,42 @@ define <4 x double> @v_maximum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
+; GFX10-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
+; GFX10-NEXT: v_max_f64 v[20:21], v[4:5], v[12:13]
+; GFX10-NEXT: v_max_f64 v[22:23], v[6:7], v[14:15]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
-; GFX10-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
-; GFX10-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
+; GFX11-NEXT: v_max_f64 v[18:19], v[2:3], v[10:11]
+; GFX11-NEXT: v_max_f64 v[20:21], v[4:5], v[12:13]
+; GFX11-NEXT: v_max_f64 v[22:23], v[6:7], v[14:15]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
-; GFX11-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
-; GFX11-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v4f64__nsz:
@@ -1900,38 +1902,38 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX7-NEXT: v_mov_b32_e32 v38, 0x7ff80000
; GFX7-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
-; GFX7-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX7-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX7-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX7-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
-; GFX7-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
-; GFX7-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX7-NEXT: v_max_f64 v[34:35], v[10:11], v[26:27]
+; GFX7-NEXT: v_max_f64 v[36:37], v[12:13], v[28:29]
; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v38, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v22, 0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v19, v38, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v23, v38, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v34, 0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v21, v38, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v35, v38, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v36, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v37, v38, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
; GFX7-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v38, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v8f64:
@@ -1940,38 +1942,38 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX8-NEXT: v_mov_b32_e32 v38, 0x7ff80000
; GFX8-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
-; GFX8-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX8-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX8-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX8-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
-; GFX8-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
-; GFX8-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX8-NEXT: v_max_f64 v[34:35], v[10:11], v[26:27]
+; GFX8-NEXT: v_max_f64 v[36:37], v[12:13], v[28:29]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v38, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v22, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v19, v38, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v23, v38, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v34, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v21, v38, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v35, v38, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v36, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v37, v38, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
; GFX8-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v38, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v8f64:
@@ -1980,38 +1982,38 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX900-NEXT: v_mov_b32_e32 v38, 0x7ff80000
; GFX900-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
-; GFX900-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX900-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX900-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX900-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
-; GFX900-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
-; GFX900-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX900-NEXT: v_max_f64 v[34:35], v[10:11], v[26:27]
+; GFX900-NEXT: v_max_f64 v[36:37], v[12:13], v[28:29]
; GFX900-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v38, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, v22, 0, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v19, v38, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v9, v23, v38, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, v34, 0, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v21, v38, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e32 v11, v35, v38, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, v36, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v13, v37, v38, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
; GFX900-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v15, v17, v38, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v8f64:
@@ -2063,38 +2065,38 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
+; GFX10-NEXT: v_max_f64 v[34:35], v[2:3], v[18:19]
+; GFX10-NEXT: v_max_f64 v[36:37], v[4:5], v[20:21]
+; GFX10-NEXT: v_max_f64 v[38:39], v[6:7], v[22:23]
+; GFX10-NEXT: v_max_f64 v[48:49], v[8:9], v[24:25]
+; GFX10-NEXT: v_max_f64 v[50:51], v[10:11], v[26:27]
+; GFX10-NEXT: v_max_f64 v[52:53], v[12:13], v[28:29]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[18:19]
-; GFX10-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[20:21]
-; GFX10-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[22:23]
-; GFX10-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[8:9], v[24:25]
-; GFX10-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[10:11], v[26:27]
-; GFX10-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[12:13], v[28:29]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v16, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v22, 0, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v24, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v26, 0, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s9
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v34, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v35, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v36, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v37, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v38, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v39, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v48, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v50, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v51, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v52, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v53, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_max_f64 v[28:29], v[14:15], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v28, 0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s10
+; GFX10-NEXT: v_max_f64 v[54:55], v[14:15], v[30:31]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[14:15], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v54, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v8f64:
@@ -2102,39 +2104,39 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
+; GFX11-NEXT: v_max_f64 v[34:35], v[2:3], v[18:19]
+; GFX11-NEXT: v_max_f64 v[36:37], v[4:5], v[20:21]
+; GFX11-NEXT: v_max_f64 v[38:39], v[6:7], v[22:23]
+; GFX11-NEXT: v_max_f64 v[48:49], v[8:9], v[24:25]
+; GFX11-NEXT: v_max_f64 v[50:51], v[10:11], v[26:27]
+; GFX11-NEXT: v_max_f64 v[52:53], v[12:13], v[28:29]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[18:19]
-; GFX11-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[20:21]
-; GFX11-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[22:23]
-; GFX11-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[24:25]
-; GFX11-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[26:27]
-; GFX11-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[28:29]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v16, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v18, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v22, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v24, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v26, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s5
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v34, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v35, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v36, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v37, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v38, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v39, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v48, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v50, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v51, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v52, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v53, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[28:29], v[14:15], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[30:31]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v28, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s6
+; GFX11-NEXT: v_max_f64 v[54:55], v[14:15], v[30:31]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[14:15], v[30:31]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v54, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v8f64:
@@ -2178,118 +2180,118 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX7-LABEL: v_maximum_v16f64:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
-; GFX7-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[31:32]
; GFX7-NEXT: v_max_f64 v[2:3], v[2:3], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[31:32]
; GFX7-NEXT: v_max_f64 v[4:5], v[4:5], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[31:32]
; GFX7-NEXT: v_max_f64 v[6:7], v[6:7], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[31:32]
; GFX7-NEXT: v_max_f64 v[8:9], v[8:9], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[8:9]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[10:11], v[31:32]
; GFX7-NEXT: v_max_f64 v[10:11], v[10:11], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[12:13], v[31:32]
; GFX7-NEXT: v_max_f64 v[12:13], v[12:13], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[12:13]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[14:15], v[31:32]
; GFX7-NEXT: v_max_f64 v[14:15], v[14:15], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[16:17], v[16:17], v[31:32]
; GFX7-NEXT: v_max_f64 v[16:17], v[16:17], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX7-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[16:17]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[18:19], v[18:19], v[31:32]
; GFX7-NEXT: v_max_f64 v[18:19], v[18:19], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX7-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[18:19]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[20:21], v[20:21], v[31:32]
; GFX7-NEXT: v_max_f64 v[20:21], v[20:21], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX7-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[20:21]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[22:23], v[22:23], v[31:32]
; GFX7-NEXT: v_max_f64 v[22:23], v[22:23], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX7-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[22:23]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[24:25], v[24:25], v[31:32]
; GFX7-NEXT: v_max_f64 v[24:25], v[24:25], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX7-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[24:25]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[26:27], v[26:27], v[31:32]
; GFX7-NEXT: v_max_f64 v[26:27], v[26:27], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX7-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[26:27]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[28:29], v[28:29], v[31:32]
; GFX7-NEXT: v_max_f64 v[28:29], v[28:29], v[31:32]
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GFX7-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[28:29]
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cmp_u_f64_e64 s[40:41], v[0:1], v[31:32]
+; GFX7-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX7-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[40:41]
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX7-NEXT: v_max_f64 v[30:31], v[30:31], v[32:33]
; GFX7-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX7-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX7-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX7-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX7-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX7-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX7-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX7-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v32, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[28:29]
; GFX7-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
; GFX7-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -2297,118 +2299,118 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX8-LABEL: v_maximum_v16f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[31:32]
; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[31:32]
; GFX8-NEXT: v_max_f64 v[4:5], v[4:5], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[31:32]
; GFX8-NEXT: v_max_f64 v[6:7], v[6:7], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[31:32]
; GFX8-NEXT: v_max_f64 v[8:9], v[8:9], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[8:9]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[10:11], v[31:32]
; GFX8-NEXT: v_max_f64 v[10:11], v[10:11], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[12:13], v[31:32]
; GFX8-NEXT: v_max_f64 v[12:13], v[12:13], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[12:13]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[14:15], v[31:32]
; GFX8-NEXT: v_max_f64 v[14:15], v[14:15], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[16:17], v[16:17], v[31:32]
; GFX8-NEXT: v_max_f64 v[16:17], v[16:17], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[16:17]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[18:19], v[18:19], v[31:32]
; GFX8-NEXT: v_max_f64 v[18:19], v[18:19], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[18:19]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[20:21], v[20:21], v[31:32]
; GFX8-NEXT: v_max_f64 v[20:21], v[20:21], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[20:21]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[22:23], v[22:23], v[31:32]
; GFX8-NEXT: v_max_f64 v[22:23], v[22:23], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[22:23]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[24:25], v[24:25], v[31:32]
; GFX8-NEXT: v_max_f64 v[24:25], v[24:25], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[24:25]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[26:27], v[26:27], v[31:32]
; GFX8-NEXT: v_max_f64 v[26:27], v[26:27], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[26:27]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[28:29], v[28:29], v[31:32]
; GFX8-NEXT: v_max_f64 v[28:29], v[28:29], v[31:32]
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
+; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GFX8-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[28:29]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cmp_u_f64_e64 s[40:41], v[0:1], v[31:32]
+; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX8-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[40:41]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX8-NEXT: v_max_f64 v[30:31], v[30:31], v[32:33]
; GFX8-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX8-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v32, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[28:29]
; GFX8-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -2416,118 +2418,118 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX900-LABEL: v_maximum_v16f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
-; GFX900-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[31:32]
; GFX900-NEXT: v_max_f64 v[2:3], v[2:3], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[31:32]
; GFX900-NEXT: v_max_f64 v[4:5], v[4:5], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[31:32]
; GFX900-NEXT: v_max_f64 v[6:7], v[6:7], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[31:32]
; GFX900-NEXT: v_max_f64 v[8:9], v[8:9], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[8:9]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[10:11], v[31:32]
; GFX900-NEXT: v_max_f64 v[10:11], v[10:11], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[12:13], v[31:32]
; GFX900-NEXT: v_max_f64 v[12:13], v[12:13], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[12:13]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[14:15], v[31:32]
; GFX900-NEXT: v_max_f64 v[14:15], v[14:15], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX900-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[16:17], v[16:17], v[31:32]
; GFX900-NEXT: v_max_f64 v[16:17], v[16:17], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX900-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[18:19], v[18:19], v[31:32]
; GFX900-NEXT: v_max_f64 v[18:19], v[18:19], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX900-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[18:19]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[20:21], v[20:21], v[31:32]
; GFX900-NEXT: v_max_f64 v[20:21], v[20:21], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX900-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[20:21]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[22:23], v[22:23], v[31:32]
; GFX900-NEXT: v_max_f64 v[22:23], v[22:23], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX900-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[22:23]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[24:25], v[24:25], v[31:32]
; GFX900-NEXT: v_max_f64 v[24:25], v[24:25], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX900-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[24:25]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[26:27], v[26:27], v[31:32]
; GFX900-NEXT: v_max_f64 v[26:27], v[26:27], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX900-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[26:27]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[28:29], v[28:29], v[31:32]
; GFX900-NEXT: v_max_f64 v[28:29], v[28:29], v[31:32]
+; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
+; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GFX900-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[28:29]
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: v_cmp_u_f64_e64 s[40:41], v[0:1], v[31:32]
+; GFX900-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX900-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[40:41]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX900-NEXT: v_max_f64 v[30:31], v[30:31], v[32:33]
; GFX900-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX900-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX900-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX900-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX900-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX900-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX900-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX900-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v1, v1, v32, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[28:29]
; GFX900-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
; GFX900-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2724,20 +2726,21 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: s_waitcnt vmcnt(21)
; GFX10-NEXT: v_max_f64 v[84:85], v[2:3], v[33:34]
; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[33:34]
-; GFX10-NEXT: s_waitcnt vmcnt(19)
-; GFX10-NEXT: v_max_f64 v[32:33], v[4:5], v[35:36]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[35:36]
-; GFX10-NEXT: s_clause 0x7
-; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112
+; GFX10-NEXT: s_clause 0x4
+; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:112
+; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:108
; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:104
-; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108
-; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120
-; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116
+; GFX10-NEXT: buffer_load_dword v87, off, s[0:3], s32 offset:120
+; GFX10-NEXT: buffer_load_dword v86, off, s[0:3], s32 offset:116
+; GFX10-NEXT: s_waitcnt vmcnt(24)
+; GFX10-NEXT: v_max_f64 v[96:97], v[4:5], v[35:36]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[35:36]
+; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128
-; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:128
+; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:124
; GFX10-NEXT: s_waitcnt vmcnt(24)
-; GFX10-NEXT: v_max_f64 v[34:35], v[6:7], v[48:49]
+; GFX10-NEXT: v_max_f64 v[98:99], v[6:7], v[48:49]
; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[48:49]
; GFX10-NEXT: s_waitcnt vmcnt(21)
; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[52:53]
@@ -2753,17 +2756,20 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: v_max_f64 v[54:55], v[14:15], v[52:53]
; GFX10-NEXT: s_waitcnt vmcnt(11)
; GFX10-NEXT: v_max_f64 v[64:65], v[20:21], v[70:71]
-; GFX10-NEXT: v_cmp_u_f64_e64 s13, v[20:21], v[70:71]
-; GFX10-NEXT: s_waitcnt vmcnt(9)
-; GFX10-NEXT: v_cmp_u_f64_e64 s12, v[18:19], v[80:81]
+; GFX10-NEXT: v_max_f64 v[100:101], v[22:23], v[68:69]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v82, 0, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: v_max_f64 v[52:53], v[16:17], v[50:51]
; GFX10-NEXT: v_cmp_u_f64_e64 s11, v[16:17], v[50:51]
; GFX10-NEXT: v_max_f64 v[50:51], v[18:19], v[80:81]
-; GFX10-NEXT: v_max_f64 v[70:71], v[22:23], v[68:69]
-; GFX10-NEXT: v_cmp_u_f64_e64 s14, v[22:23], v[68:69]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v34, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v35, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v83, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[18:19], v[80:81]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v84, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v85, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v96, 0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v97, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v98, 0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v99, 0x7ff80000, s6
; GFX10-NEXT: v_cndmask_b32_e64 v8, v48, 0, s7
; GFX10-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, s7
; GFX10-NEXT: v_cndmask_b32_e64 v10, v36, 0, s8
@@ -2774,45 +2780,40 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, s10
; GFX10-NEXT: v_cndmask_b32_e64 v16, v52, 0, s11
; GFX10-NEXT: v_cndmask_b32_e64 v17, v53, 0x7ff80000, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v50, 0, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v51, 0x7ff80000, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v20, v64, 0, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v65, 0x7ff80000, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v70, 0, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v23, v71, 0x7ff80000, s14
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v50, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v51, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[20:21], v[70:71]
+; GFX10-NEXT: v_cndmask_b32_e64 v20, v64, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v21, v65, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[22:23], v[68:69]
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v100, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v23, v101, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(6)
-; GFX10-NEXT: v_max_f64 v[68:69], v[24:25], v[66:67]
-; GFX10-NEXT: v_cmp_u_f64_e64 s15, v[24:25], v[66:67]
+; GFX10-NEXT: v_max_f64 v[112:113], v[26:27], v[32:33]
; GFX10-NEXT: s_waitcnt vmcnt(5)
-; GFX10-NEXT: v_max_f64 v[66:67], v[26:27], v[0:1]
-; GFX10-NEXT: v_cmp_u_f64_e64 s16, v[26:27], v[0:1]
+; GFX10-NEXT: v_max_f64 v[102:103], v[24:25], v[66:67]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[24:25], v[66:67]
; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_max_f64 v[80:81], v[28:29], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e64 s17, v[28:29], v[2:3]
+; GFX10-NEXT: v_max_f64 v[114:115], v[28:29], v[86:87]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_max_f64 v[86:87], v[30:31], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e64 s18, v[30:31], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v82, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v83, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v84, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v85, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v32, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v33, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v24, v68, 0, s15
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v69, 0x7ff80000, s15
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v66, 0, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v67, 0x7ff80000, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v28, v80, 0, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v81, 0x7ff80000, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v30, v86, 0, s18
-; GFX10-NEXT: v_cndmask_b32_e64 v31, v87, 0x7ff80000, s18
+; GFX10-NEXT: v_max_f64 v[36:37], v[30:31], v[34:35]
+; GFX10-NEXT: v_cndmask_b32_e64 v24, v102, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v25, v103, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[26:27], v[32:33]
+; GFX10-NEXT: v_cndmask_b32_e64 v26, v112, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v27, v113, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[28:29], v[86:87]
+; GFX10-NEXT: v_cndmask_b32_e64 v28, v114, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v29, v115, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[30:31], v[34:35]
+; GFX10-NEXT: v_cndmask_b32_e64 v30, v36, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v31, v37, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v16f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1f
-; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:16
@@ -2831,100 +2832,101 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:72
; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:68
-; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:80
-; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:76
-; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:88
-; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:84
-; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:96
-; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:92
-; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:104
-; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:100
-; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:112
-; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:108
-; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:120
-; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:120
+; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:80
+; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:76
+; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:112
+; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:88
+; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:84
+; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:104
+; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:96
+; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:92
+; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:100
+; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:108
+; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:128
; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:124
-; GFX11-NEXT: s_waitcnt vmcnt(30)
+; GFX11-NEXT: s_waitcnt vmcnt(31)
; GFX11-NEXT: v_max_f64 v[96:97], v[0:1], v[32:33]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[32:33]
-; GFX11-NEXT: s_waitcnt vmcnt(28)
-; GFX11-NEXT: v_max_f64 v[32:33], v[2:3], v[34:35]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[34:35]
-; GFX11-NEXT: s_waitcnt vmcnt(26)
-; GFX11-NEXT: v_max_f64 v[34:35], v[4:5], v[36:37]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[36:37]
-; GFX11-NEXT: s_waitcnt vmcnt(24)
-; GFX11-NEXT: v_max_f64 v[36:37], v[6:7], v[38:39]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[38:39]
-; GFX11-NEXT: s_waitcnt vmcnt(22)
-; GFX11-NEXT: v_max_f64 v[38:39], v[8:9], v[48:49]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[48:49]
-; GFX11-NEXT: s_waitcnt vmcnt(20)
-; GFX11-NEXT: v_max_f64 v[48:49], v[10:11], v[50:51]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[50:51]
-; GFX11-NEXT: s_waitcnt vmcnt(18)
-; GFX11-NEXT: v_max_f64 v[50:51], v[12:13], v[52:53]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[52:53]
-; GFX11-NEXT: s_waitcnt vmcnt(16)
-; GFX11-NEXT: v_max_f64 v[52:53], v[14:15], v[54:55]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[54:55]
-; GFX11-NEXT: s_waitcnt vmcnt(14)
-; GFX11-NEXT: v_max_f64 v[54:55], v[16:17], v[64:65]
-; GFX11-NEXT: v_cmp_u_f64_e64 s7, v[16:17], v[64:65]
+; GFX11-NEXT: s_waitcnt vmcnt(29)
+; GFX11-NEXT: v_max_f64 v[98:99], v[2:3], v[34:35]
+; GFX11-NEXT: s_waitcnt vmcnt(27)
+; GFX11-NEXT: v_max_f64 v[100:101], v[4:5], v[36:37]
+; GFX11-NEXT: s_waitcnt vmcnt(25)
+; GFX11-NEXT: v_max_f64 v[102:103], v[6:7], v[38:39]
+; GFX11-NEXT: s_waitcnt vmcnt(23)
+; GFX11-NEXT: v_max_f64 v[112:113], v[8:9], v[48:49]
+; GFX11-NEXT: s_waitcnt vmcnt(21)
+; GFX11-NEXT: v_max_f64 v[114:115], v[10:11], v[50:51]
+; GFX11-NEXT: s_waitcnt vmcnt(19)
+; GFX11-NEXT: v_max_f64 v[116:117], v[12:13], v[52:53]
+; GFX11-NEXT: s_waitcnt vmcnt(17)
+; GFX11-NEXT: v_max_f64 v[118:119], v[14:15], v[54:55]
+; GFX11-NEXT: s_waitcnt vmcnt(15)
+; GFX11-NEXT: v_max_f64 v[128:129], v[16:17], v[64:65]
; GFX11-NEXT: s_waitcnt vmcnt(12)
-; GFX11-NEXT: v_max_f64 v[64:65], v[18:19], v[66:67]
-; GFX11-NEXT: v_cmp_u_f64_e64 s8, v[18:19], v[66:67]
-; GFX11-NEXT: s_waitcnt vmcnt(10)
-; GFX11-NEXT: v_max_f64 v[66:67], v[20:21], v[68:69]
-; GFX11-NEXT: v_cmp_u_f64_e64 s9, v[20:21], v[68:69]
-; GFX11-NEXT: s_waitcnt vmcnt(8)
-; GFX11-NEXT: v_max_f64 v[68:69], v[22:23], v[70:71]
-; GFX11-NEXT: v_cmp_u_f64_e64 s10, v[22:23], v[70:71]
+; GFX11-NEXT: v_max_f64 v[130:131], v[18:19], v[68:69]
+; GFX11-NEXT: s_waitcnt vmcnt(9)
+; GFX11-NEXT: v_max_f64 v[132:133], v[20:21], v[80:81]
; GFX11-NEXT: s_waitcnt vmcnt(6)
-; GFX11-NEXT: v_max_f64 v[70:71], v[24:25], v[80:81]
-; GFX11-NEXT: v_cmp_u_f64_e64 s11, v[24:25], v[80:81]
+; GFX11-NEXT: v_max_f64 v[32:33], v[22:23], v[84:85]
+; GFX11-NEXT: s_waitcnt vmcnt(5)
+; GFX11-NEXT: v_max_f64 v[134:135], v[24:25], v[82:83]
; GFX11-NEXT: s_waitcnt vmcnt(4)
-; GFX11-NEXT: v_max_f64 v[80:81], v[26:27], v[82:83]
-; GFX11-NEXT: v_cmp_u_f64_e64 s12, v[26:27], v[82:83]
-; GFX11-NEXT: s_waitcnt vmcnt(2)
-; GFX11-NEXT: v_max_f64 v[82:83], v[28:29], v[84:85]
-; GFX11-NEXT: v_cmp_u_f64_e64 s13, v[28:29], v[84:85]
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[84:85], v[30:31], v[86:87]
-; GFX11-NEXT: v_cmp_u_f64_e64 s14, v[30:31], v[86:87]
+; GFX11-NEXT: v_max_f64 v[144:145], v[26:27], v[70:71]
+; GFX11-NEXT: s_waitcnt vmcnt(3)
+; GFX11-NEXT: v_max_f64 v[146:147], v[28:29], v[66:67]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v96, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v97, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v32, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v33, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v34, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v35, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v36, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v37, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v38, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v39, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v48, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v49, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v50, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v51, 0x7ff80000, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v52, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v53, 0x7ff80000, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v54, 0, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v17, v55, 0x7ff80000, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v18, v64, 0, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v19, v65, 0x7ff80000, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v20, v66, 0, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v67, 0x7ff80000, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v68, 0, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v23, v69, 0x7ff80000, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v24, v70, 0, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v25, v71, 0x7ff80000, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v26, v80, 0, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v27, v81, 0x7ff80000, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v28, v82, 0, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v29, v83, 0x7ff80000, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v30, v84, 0, s14
-; GFX11-NEXT: v_cndmask_b32_e64 v31, v85, 0x7ff80000, s14
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_max_f64 v[96:97], v[30:31], v[86:87]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[34:35]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v98, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v99, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[36:37]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v100, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v101, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[38:39]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v102, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v103, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[48:49]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v112, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v113, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[50:51]
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v114, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v115, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[12:13], v[52:53]
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v116, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v117, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[14:15], v[54:55]
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v118, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v119, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[16:17], v[64:65]
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v128, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v17, v129, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[18:19], v[68:69]
+; GFX11-NEXT: v_cndmask_b32_e64 v18, v130, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v19, v131, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[20:21], v[80:81]
+; GFX11-NEXT: v_cndmask_b32_e64 v20, v132, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v21, v133, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[22:23], v[84:85]
+; GFX11-NEXT: v_cndmask_b32_e64 v22, v32, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v23, v33, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[24:25], v[82:83]
+; GFX11-NEXT: v_cndmask_b32_e64 v24, v134, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v25, v135, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[26:27], v[70:71]
+; GFX11-NEXT: v_cndmask_b32_e64 v26, v144, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v27, v145, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[28:29], v[66:67]
+; GFX11-NEXT: v_cndmask_b32_e64 v28, v146, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v29, v147, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[30:31], v[86:87]
+; GFX11-NEXT: v_cndmask_b32_e64 v30, v96, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v31, v97, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_maximum_v16f64:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
index cd01dfc2d3dc8..c764adb1442c6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
@@ -683,8 +683,8 @@ define <2 x half> @v_minimum_v2f16(<2 x half> %src0, <2 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v2, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -822,8 +822,8 @@ define <2 x half> @v_minimum_v2f16__nsz(<2 x half> %src0, <2 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v2, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -975,12 +975,12 @@ define void @s_minimum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) {
; GFX10-LABEL: s_minimum_v2f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_min_f16 v0, s16, s17
; GFX10-NEXT: s_lshr_b32 s4, s17, 16
; GFX10-NEXT: s_lshr_b32 s5, s16, 16
-; GFX10-NEXT: v_pk_min_f16 v0, s16, s17
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s5, s4
; GFX10-NEXT: v_cmp_o_f16_e64 s4, s16, s17
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0x7e00, v0, s4
; GFX10-NEXT: v_cndmask_b32_sdwa v0, v1, v0, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
@@ -1103,8 +1103,8 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v2
-; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_pk_min_f16 v4, v1, v3
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1268,8 +1268,8 @@ define <3 x half> @v_minimum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v2
-; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_pk_min_f16 v4, v1, v3
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1447,11 +1447,11 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_e64 s5, v0, v2
; GFX10-NEXT: v_cndmask_b32_sdwa v2, v4, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
; GFX10-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -1635,11 +1635,11 @@ define <4 x half> @v_minimum_v4f16__nsz(<4 x half> %src0, <4 x half> %src1) {
; GFX10-NEXT: v_cmp_o_f16_e64 s5, v0, v2
; GFX10-NEXT: v_cndmask_b32_sdwa v2, v4, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
; GFX10-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
index 57ab11987145e..7436bc019797a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
@@ -1843,7 +1843,6 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX7-NEXT: v_min_f32_e32 v2, v2, v18
; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000
; GFX7-NEXT: v_min_f32_e32 v18, v13, v29
-; GFX7-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX7-NEXT: v_cmp_o_f32_e64 s[8:9], v3, v19
; GFX7-NEXT: v_min_f32_e32 v3, v3, v19
; GFX7-NEXT: v_cmp_o_f32_e64 s[10:11], v4, v20
@@ -1864,10 +1863,11 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX7-NEXT: v_min_f32_e32 v11, v11, v27
; GFX7-NEXT: v_cmp_o_f32_e64 s[26:27], v12, v28
; GFX7-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX7-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX7-NEXT: v_min_f32_e32 v19, v14, v30
-; GFX7-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v13, v17, v18, s[28:29]
+; GFX7-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX7-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
@@ -1899,7 +1899,6 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX8-NEXT: v_min_f32_e32 v2, v2, v18
; GFX8-NEXT: v_mov_b32_e32 v17, 0x7fc00000
; GFX8-NEXT: v_min_f32_e32 v18, v13, v29
-; GFX8-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX8-NEXT: v_cmp_o_f32_e64 s[8:9], v3, v19
; GFX8-NEXT: v_min_f32_e32 v3, v3, v19
; GFX8-NEXT: v_cmp_o_f32_e64 s[10:11], v4, v20
@@ -1920,10 +1919,11 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX8-NEXT: v_min_f32_e32 v11, v11, v27
; GFX8-NEXT: v_cmp_o_f32_e64 s[26:27], v12, v28
; GFX8-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX8-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX8-NEXT: v_min_f32_e32 v19, v14, v30
-; GFX8-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v13, v17, v18, s[28:29]
+; GFX8-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX8-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
@@ -1955,7 +1955,6 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX900-NEXT: v_min_f32_e32 v2, v2, v18
; GFX900-NEXT: v_mov_b32_e32 v17, 0x7fc00000
; GFX900-NEXT: v_min_f32_e32 v18, v13, v29
-; GFX900-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX900-NEXT: v_cmp_o_f32_e64 s[8:9], v3, v19
; GFX900-NEXT: v_min_f32_e32 v3, v3, v19
; GFX900-NEXT: v_cmp_o_f32_e64 s[10:11], v4, v20
@@ -1976,10 +1975,11 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX900-NEXT: v_min_f32_e32 v11, v11, v27
; GFX900-NEXT: v_cmp_o_f32_e64 s[26:27], v12, v28
; GFX900-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX900-NEXT: v_cmp_o_f32_e64 s[28:29], v13, v29
; GFX900-NEXT: v_min_f32_e32 v19, v14, v30
-; GFX900-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v13, v17, v18, s[28:29]
+; GFX900-NEXT: v_cmp_o_f32_e64 s[40:41], v14, v30
; GFX900-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[4:5]
; GFX900-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[6:7]
; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
index 1d7678779b8be..4250fcba4feae 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
@@ -14,9 +14,9 @@ define double @v_minimum_f64(double %src0, double %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64:
@@ -24,9 +24,9 @@ define double @v_minimum_f64(double %src0, double %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64:
@@ -34,9 +34,9 @@ define double @v_minimum_f64(double %src0, double %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64:
@@ -144,9 +144,9 @@ define double @v_minimum_f64__nsz(double %src0, double %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64__nsz:
@@ -154,9 +154,9 @@ define double @v_minimum_f64__nsz(double %src0, double %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64__nsz:
@@ -164,9 +164,9 @@ define double @v_minimum_f64__nsz(double %src0, double %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64__nsz:
@@ -273,33 +273,33 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64__nnan_src0:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64__nnan_src0:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64__nnan_src0:
@@ -365,33 +365,33 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64__nnan_src1:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64__nnan_src1:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64__nnan_src1:
@@ -461,8 +461,8 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) {
; GFX7-NEXT: v_min_f64 v[2:3], s[16:17], v[0:1]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use v[0:1]
; GFX7-NEXT: ;;#ASMEND
@@ -476,8 +476,8 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) {
; GFX8-NEXT: v_min_f64 v[2:3], s[16:17], v[0:1]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v[0:1]
; GFX8-NEXT: ;;#ASMEND
@@ -491,8 +491,8 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) {
; GFX900-NEXT: v_min_f64 v[2:3], s[16:17], v[0:1]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[0:1]
; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use v[0:1]
; GFX900-NEXT: ;;#ASMEND
@@ -570,13 +570,13 @@ define <2 x double> @v_minimum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v2f64:
@@ -584,13 +584,13 @@ define <2 x double> @v_minimum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v2f64:
@@ -598,13 +598,13 @@ define <2 x double> @v_minimum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v2f64:
@@ -627,27 +627,27 @@ define <2 x double> @v_minimum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
+; GFX10-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v2f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v2f64:
@@ -734,13 +734,13 @@ define <2 x double> @v_minimum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v2f64__nsz:
@@ -748,13 +748,13 @@ define <2 x double> @v_minimum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v2f64__nsz:
@@ -762,13 +762,13 @@ define <2 x double> @v_minimum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v2f64__nsz:
@@ -791,27 +791,27 @@ define <2 x double> @v_minimum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
+; GFX10-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v2f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[10:11], v[2:3], v[6:7]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v2f64__nsz:
@@ -900,15 +900,15 @@ define void @s_minimum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX7-NEXT: v_mov_b32_e32 v1, s23
; GFX7-NEXT: v_min_f64 v[2:3], s[18:19], v[0:1]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[18:19], v[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v0, s20
-; GFX7-NEXT: v_mov_b32_e32 v1, s21
-; GFX7-NEXT: v_min_f64 v[4:5], s[16:17], v[0:1]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], v[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX7-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[6:7], s[16:17], v[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v6, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use v[0:3]
; GFX7-NEXT: ;;#ASMEND
@@ -921,15 +921,15 @@ define void @s_minimum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX8-NEXT: v_mov_b32_e32 v1, s23
; GFX8-NEXT: v_min_f64 v[2:3], s[18:19], v[0:1]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[18:19], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s20
-; GFX8-NEXT: v_mov_b32_e32 v1, s21
-; GFX8-NEXT: v_min_f64 v[4:5], s[16:17], v[0:1]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[6:7], s[16:17], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v[0:3]
; GFX8-NEXT: ;;#ASMEND
@@ -942,15 +942,15 @@ define void @s_minimum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX900-NEXT: v_mov_b32_e32 v1, s23
; GFX900-NEXT: v_min_f64 v[2:3], s[18:19], v[0:1]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, s[18:19], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v0, s20
-; GFX900-NEXT: v_mov_b32_e32 v1, s21
-; GFX900-NEXT: v_min_f64 v[4:5], s[16:17], v[0:1]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], s[16:17], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX900-NEXT: v_mov_b32_e32 v4, s20
+; GFX900-NEXT: v_mov_b32_e32 v5, s21
+; GFX900-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[6:7], s[16:17], v[4:5]
; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, v5, v6, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, s[16:17], v[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use v[0:3]
; GFX900-NEXT: ;;#ASMEND
@@ -980,13 +980,13 @@ define void @s_minimum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[0:1], s[18:19], s[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[18:19], s[22:23]
; GFX10-NEXT: v_min_f64 v[4:5], s[16:17], s[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, s[16:17], s[20:21]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[18:19], s[22:23]
; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, 0x7ff80000, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, s5
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[16:17], s[20:21]
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, s4
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use v[0:3]
; GFX10-NEXT: ;;#ASMEND
@@ -996,10 +996,10 @@ define void @s_minimum_v2f64(<2 x double> inreg %src0, <2 x double> inreg %src1)
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[0:1], s[2:3], s[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, s[2:3], s[18:19]
; GFX11-NEXT: v_min_f64 v[4:5], s[0:1], s[16:17]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, s[2:3], s[18:19]
; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v1, 0x7ff80000, s2
; GFX11-NEXT: v_cndmask_b32_e64 v2, v0, 0, s2
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, s0
@@ -1043,17 +1043,17 @@ define <3 x double> @v_minimum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX7-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v3f64:
@@ -1061,17 +1061,17 @@ define <3 x double> @v_minimum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX8-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v3f64:
@@ -1079,17 +1079,17 @@ define <3 x double> @v_minimum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX900-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX900-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v3f64:
@@ -1117,34 +1117,35 @@ define <3 x double> @v_minimum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
+; GFX10-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX10-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
-; GFX10-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v3f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
+; GFX11-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX11-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
-; GFX11-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v3f64:
@@ -1240,17 +1241,17 @@ define <3 x double> @v_minimum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX7-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v3f64__nsz:
@@ -1258,17 +1259,17 @@ define <3 x double> @v_minimum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX8-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v3f64__nsz:
@@ -1276,17 +1277,17 @@ define <3 x double> @v_minimum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX900-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
-; GFX900-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
-; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
+; GFX900-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX900-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v15, v6, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v17, v6, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v3f64__nsz:
@@ -1314,34 +1315,35 @@ define <3 x double> @v_minimum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
+; GFX10-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX10-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
-; GFX10-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v3f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
+; GFX11-NEXT: v_min_f64 v[14:15], v[2:3], v[8:9]
+; GFX11-NEXT: v_min_f64 v[16:17], v[4:5], v[10:11]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
-; GFX11-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v14, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v15, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v3f64__nsz:
@@ -1437,21 +1439,21 @@ define <4 x double> @v_minimum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX7-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX7-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX7-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v4f64:
@@ -1459,21 +1461,21 @@ define <4 x double> @v_minimum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX8-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX8-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX8-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v4f64:
@@ -1481,21 +1483,21 @@ define <4 x double> @v_minimum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX900-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX900-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX900-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX900-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v4f64:
@@ -1528,42 +1530,42 @@ define <4 x double> @v_minimum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
+; GFX10-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
+; GFX10-NEXT: v_min_f64 v[20:21], v[4:5], v[12:13]
+; GFX10-NEXT: v_min_f64 v[22:23], v[6:7], v[14:15]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
-; GFX10-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
-; GFX10-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
+; GFX11-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
+; GFX11-NEXT: v_min_f64 v[20:21], v[4:5], v[12:13]
+; GFX11-NEXT: v_min_f64 v[22:23], v[6:7], v[14:15]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
-; GFX11-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
-; GFX11-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v4f64:
@@ -1668,21 +1670,21 @@ define <4 x double> @v_minimum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX7-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX7-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX7-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v4f64__nsz:
@@ -1690,21 +1692,21 @@ define <4 x double> @v_minimum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX8-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX8-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX8-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v4f64__nsz:
@@ -1712,21 +1714,21 @@ define <4 x double> @v_minimum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX900-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX900-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
+; GFX900-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
-; GFX900-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
-; GFX900-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
+; GFX900-NEXT: v_min_f64 v[10:11], v[6:7], v[14:15]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_mov_b32_e32 v16, 0x7ff80000
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v19, v16, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v7, v11, v16, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v4f64__nsz:
@@ -1759,42 +1761,42 @@ define <4 x double> @v_minimum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
+; GFX10-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
+; GFX10-NEXT: v_min_f64 v[20:21], v[4:5], v[12:13]
+; GFX10-NEXT: v_min_f64 v[22:23], v[6:7], v[14:15]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
-; GFX10-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
-; GFX10-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v4f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
+; GFX11-NEXT: v_min_f64 v[18:19], v[2:3], v[10:11]
+; GFX11-NEXT: v_min_f64 v[20:21], v[4:5], v[12:13]
+; GFX11-NEXT: v_min_f64 v[22:23], v[6:7], v[14:15]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
-; GFX11-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
-; GFX11-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v19, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v20, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v21, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v22, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v23, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v4f64__nsz:
@@ -1900,38 +1902,38 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX7-NEXT: v_mov_b32_e32 v38, 0x7ff80000
; GFX7-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
-; GFX7-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX7-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX7-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX7-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
-; GFX7-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
-; GFX7-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX7-NEXT: v_min_f64 v[34:35], v[10:11], v[26:27]
+; GFX7-NEXT: v_min_f64 v[36:37], v[12:13], v[28:29]
; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v38, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v22, 0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v19, v38, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v23, v38, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v34, 0, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v21, v38, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v35, v38, vcc
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v36, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v37, v38, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
; GFX7-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v38, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v8f64:
@@ -1940,38 +1942,38 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX8-NEXT: v_mov_b32_e32 v38, 0x7ff80000
; GFX8-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
-; GFX8-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX8-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX8-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX8-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
-; GFX8-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
-; GFX8-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX8-NEXT: v_min_f64 v[34:35], v[10:11], v[26:27]
+; GFX8-NEXT: v_min_f64 v[36:37], v[12:13], v[28:29]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v38, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v22, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v19, v38, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v23, v38, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v34, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v21, v38, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v35, v38, vcc
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v36, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v37, v38, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
; GFX8-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v38, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v8f64:
@@ -1980,38 +1982,38 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX900-NEXT: v_mov_b32_e32 v38, 0x7ff80000
; GFX900-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
-; GFX900-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX900-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX900-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX900-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
-; GFX900-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
-; GFX900-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
; GFX900-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX900-NEXT: v_min_f64 v[34:35], v[10:11], v[26:27]
+; GFX900-NEXT: v_min_f64 v[36:37], v[12:13], v[28:29]
; GFX900-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v38, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, v22, 0, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v19, v38, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v9, v23, v38, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, v34, 0, vcc
; GFX900-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v21, v38, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e32 v11, v35, v38, vcc
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, v36, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v13, v37, v38, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
; GFX900-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v15, v17, v38, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v8f64:
@@ -2063,38 +2065,38 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
+; GFX10-NEXT: v_min_f64 v[34:35], v[2:3], v[18:19]
+; GFX10-NEXT: v_min_f64 v[36:37], v[4:5], v[20:21]
+; GFX10-NEXT: v_min_f64 v[38:39], v[6:7], v[22:23]
+; GFX10-NEXT: v_min_f64 v[48:49], v[8:9], v[24:25]
+; GFX10-NEXT: v_min_f64 v[50:51], v[10:11], v[26:27]
+; GFX10-NEXT: v_min_f64 v[52:53], v[12:13], v[28:29]
; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[18:19]
-; GFX10-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[20:21]
-; GFX10-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[22:23]
-; GFX10-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[8:9], v[24:25]
-; GFX10-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[10:11], v[26:27]
-; GFX10-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[12:13], v[28:29]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v16, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v22, 0, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v24, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v26, 0, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s9
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v34, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v35, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v36, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v37, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v38, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v39, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v48, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v50, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v51, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v52, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v53, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_min_f64 v[28:29], v[14:15], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v28, 0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s10
+; GFX10-NEXT: v_min_f64 v[54:55], v[14:15], v[30:31]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[14:15], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v54, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v8f64:
@@ -2102,39 +2104,39 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
+; GFX11-NEXT: v_min_f64 v[34:35], v[2:3], v[18:19]
+; GFX11-NEXT: v_min_f64 v[36:37], v[4:5], v[20:21]
+; GFX11-NEXT: v_min_f64 v[38:39], v[6:7], v[22:23]
+; GFX11-NEXT: v_min_f64 v[48:49], v[8:9], v[24:25]
+; GFX11-NEXT: v_min_f64 v[50:51], v[10:11], v[26:27]
+; GFX11-NEXT: v_min_f64 v[52:53], v[12:13], v[28:29]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[18:19]
-; GFX11-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[20:21]
-; GFX11-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[22:23]
-; GFX11-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[24:25]
-; GFX11-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[26:27]
-; GFX11-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[28:29]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v16, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v18, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v22, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v24, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v26, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s5
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v34, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v35, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v36, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v37, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v38, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v39, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v48, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v50, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v51, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v52, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v53, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_min_f64 v[28:29], v[14:15], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[30:31]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v28, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s6
+; GFX11-NEXT: v_min_f64 v[54:55], v[14:15], v[30:31]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[14:15], v[30:31]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v54, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v8f64:
@@ -2178,118 +2180,118 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX7-LABEL: v_minimum_v16f64:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
-; GFX7-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[31:32]
; GFX7-NEXT: v_min_f64 v[2:3], v[2:3], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[31:32]
; GFX7-NEXT: v_min_f64 v[4:5], v[4:5], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[31:32]
; GFX7-NEXT: v_min_f64 v[6:7], v[6:7], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[31:32]
; GFX7-NEXT: v_min_f64 v[8:9], v[8:9], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[8:9]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[10:11], v[31:32]
; GFX7-NEXT: v_min_f64 v[10:11], v[10:11], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[12:13], v[31:32]
; GFX7-NEXT: v_min_f64 v[12:13], v[12:13], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[12:13]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[14:15], v[31:32]
; GFX7-NEXT: v_min_f64 v[14:15], v[14:15], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[16:17], v[16:17], v[31:32]
; GFX7-NEXT: v_min_f64 v[16:17], v[16:17], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX7-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[16:17]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[18:19], v[18:19], v[31:32]
; GFX7-NEXT: v_min_f64 v[18:19], v[18:19], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX7-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[18:19]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[20:21], v[20:21], v[31:32]
; GFX7-NEXT: v_min_f64 v[20:21], v[20:21], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX7-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[20:21]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[22:23], v[22:23], v[31:32]
; GFX7-NEXT: v_min_f64 v[22:23], v[22:23], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX7-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[22:23]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[24:25], v[24:25], v[31:32]
; GFX7-NEXT: v_min_f64 v[24:25], v[24:25], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX7-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[24:25]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[26:27], v[26:27], v[31:32]
; GFX7-NEXT: v_min_f64 v[26:27], v[26:27], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX7-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[26:27]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[28:29], v[28:29], v[31:32]
; GFX7-NEXT: v_min_f64 v[28:29], v[28:29], v[31:32]
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GFX7-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[28:29]
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cmp_u_f64_e64 s[40:41], v[0:1], v[31:32]
+; GFX7-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX7-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[40:41]
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX7-NEXT: v_min_f64 v[30:31], v[30:31], v[32:33]
; GFX7-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX7-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX7-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX7-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX7-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX7-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX7-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX7-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v32, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[28:29]
; GFX7-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
; GFX7-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -2297,118 +2299,118 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX8-LABEL: v_minimum_v16f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[31:32]
; GFX8-NEXT: v_min_f64 v[2:3], v[2:3], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[31:32]
; GFX8-NEXT: v_min_f64 v[4:5], v[4:5], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[31:32]
; GFX8-NEXT: v_min_f64 v[6:7], v[6:7], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[31:32]
; GFX8-NEXT: v_min_f64 v[8:9], v[8:9], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[8:9]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[10:11], v[31:32]
; GFX8-NEXT: v_min_f64 v[10:11], v[10:11], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[12:13], v[31:32]
; GFX8-NEXT: v_min_f64 v[12:13], v[12:13], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[12:13]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[14:15], v[31:32]
; GFX8-NEXT: v_min_f64 v[14:15], v[14:15], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[16:17], v[16:17], v[31:32]
; GFX8-NEXT: v_min_f64 v[16:17], v[16:17], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[16:17]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[18:19], v[18:19], v[31:32]
; GFX8-NEXT: v_min_f64 v[18:19], v[18:19], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[18:19]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[20:21], v[20:21], v[31:32]
; GFX8-NEXT: v_min_f64 v[20:21], v[20:21], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[20:21]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[22:23], v[22:23], v[31:32]
; GFX8-NEXT: v_min_f64 v[22:23], v[22:23], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[22:23]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[24:25], v[24:25], v[31:32]
; GFX8-NEXT: v_min_f64 v[24:25], v[24:25], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[24:25]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[26:27], v[26:27], v[31:32]
; GFX8-NEXT: v_min_f64 v[26:27], v[26:27], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[26:27]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[28:29], v[28:29], v[31:32]
; GFX8-NEXT: v_min_f64 v[28:29], v[28:29], v[31:32]
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
+; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GFX8-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[28:29]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cmp_u_f64_e64 s[40:41], v[0:1], v[31:32]
+; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX8-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[40:41]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX8-NEXT: v_min_f64 v[30:31], v[30:31], v[32:33]
; GFX8-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX8-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v32, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[28:29]
; GFX8-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -2416,118 +2418,118 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX900-LABEL: v_minimum_v16f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
-; GFX900-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[31:32]
; GFX900-NEXT: v_min_f64 v[2:3], v[2:3], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[31:32]
; GFX900-NEXT: v_min_f64 v[4:5], v[4:5], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[31:32]
; GFX900-NEXT: v_min_f64 v[6:7], v[6:7], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[31:32]
; GFX900-NEXT: v_min_f64 v[8:9], v[8:9], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[8:9]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[10:11], v[31:32]
; GFX900-NEXT: v_min_f64 v[10:11], v[10:11], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[12:13], v[31:32]
; GFX900-NEXT: v_min_f64 v[12:13], v[12:13], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[12:13]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[14:15], v[31:32]
; GFX900-NEXT: v_min_f64 v[14:15], v[14:15], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX900-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[16:17], v[16:17], v[31:32]
; GFX900-NEXT: v_min_f64 v[16:17], v[16:17], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX900-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[18:19], v[18:19], v[31:32]
; GFX900-NEXT: v_min_f64 v[18:19], v[18:19], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX900-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[18:19]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[20:21], v[20:21], v[31:32]
; GFX900-NEXT: v_min_f64 v[20:21], v[20:21], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX900-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[20:21]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[22:23], v[22:23], v[31:32]
; GFX900-NEXT: v_min_f64 v[22:23], v[22:23], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX900-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[22:23]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[24:25], v[24:25], v[31:32]
; GFX900-NEXT: v_min_f64 v[24:25], v[24:25], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX900-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[24:25]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[26:27], v[26:27], v[31:32]
; GFX900-NEXT: v_min_f64 v[26:27], v[26:27], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX900-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[26:27]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX900-NEXT: v_cmp_u_f64_e64 s[28:29], v[28:29], v[31:32]
; GFX900-NEXT: v_min_f64 v[28:29], v[28:29], v[31:32]
+; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
+; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GFX900-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[28:29]
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: v_cmp_u_f64_e64 s[40:41], v[0:1], v[31:32]
+; GFX900-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX900-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[40:41]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX900-NEXT: v_min_f64 v[30:31], v[30:31], v[32:33]
; GFX900-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX900-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX900-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX900-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX900-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX900-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX900-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX900-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v1, v1, v32, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[28:29]
; GFX900-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
; GFX900-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2724,20 +2726,21 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: s_waitcnt vmcnt(21)
; GFX10-NEXT: v_min_f64 v[84:85], v[2:3], v[33:34]
; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[33:34]
-; GFX10-NEXT: s_waitcnt vmcnt(19)
-; GFX10-NEXT: v_min_f64 v[32:33], v[4:5], v[35:36]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[35:36]
-; GFX10-NEXT: s_clause 0x7
-; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112
+; GFX10-NEXT: s_clause 0x4
+; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:112
+; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:108
; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:104
-; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108
-; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120
-; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116
+; GFX10-NEXT: buffer_load_dword v87, off, s[0:3], s32 offset:120
+; GFX10-NEXT: buffer_load_dword v86, off, s[0:3], s32 offset:116
+; GFX10-NEXT: s_waitcnt vmcnt(24)
+; GFX10-NEXT: v_min_f64 v[96:97], v[4:5], v[35:36]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[35:36]
+; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128
-; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:128
+; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:124
; GFX10-NEXT: s_waitcnt vmcnt(24)
-; GFX10-NEXT: v_min_f64 v[34:35], v[6:7], v[48:49]
+; GFX10-NEXT: v_min_f64 v[98:99], v[6:7], v[48:49]
; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[48:49]
; GFX10-NEXT: s_waitcnt vmcnt(21)
; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[52:53]
@@ -2753,17 +2756,20 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: v_min_f64 v[54:55], v[14:15], v[52:53]
; GFX10-NEXT: s_waitcnt vmcnt(11)
; GFX10-NEXT: v_min_f64 v[64:65], v[20:21], v[70:71]
-; GFX10-NEXT: v_cmp_u_f64_e64 s13, v[20:21], v[70:71]
-; GFX10-NEXT: s_waitcnt vmcnt(9)
-; GFX10-NEXT: v_cmp_u_f64_e64 s12, v[18:19], v[80:81]
+; GFX10-NEXT: v_min_f64 v[100:101], v[22:23], v[68:69]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v82, 0, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: v_min_f64 v[52:53], v[16:17], v[50:51]
; GFX10-NEXT: v_cmp_u_f64_e64 s11, v[16:17], v[50:51]
; GFX10-NEXT: v_min_f64 v[50:51], v[18:19], v[80:81]
-; GFX10-NEXT: v_min_f64 v[70:71], v[22:23], v[68:69]
-; GFX10-NEXT: v_cmp_u_f64_e64 s14, v[22:23], v[68:69]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v34, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v35, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v83, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[18:19], v[80:81]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v84, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v85, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v96, 0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v97, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v98, 0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v99, 0x7ff80000, s6
; GFX10-NEXT: v_cndmask_b32_e64 v8, v48, 0, s7
; GFX10-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, s7
; GFX10-NEXT: v_cndmask_b32_e64 v10, v36, 0, s8
@@ -2774,45 +2780,40 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, s10
; GFX10-NEXT: v_cndmask_b32_e64 v16, v52, 0, s11
; GFX10-NEXT: v_cndmask_b32_e64 v17, v53, 0x7ff80000, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v50, 0, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v51, 0x7ff80000, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v20, v64, 0, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v65, 0x7ff80000, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v70, 0, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v23, v71, 0x7ff80000, s14
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v50, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v51, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[20:21], v[70:71]
+; GFX10-NEXT: v_cndmask_b32_e64 v20, v64, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v21, v65, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[22:23], v[68:69]
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v100, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v23, v101, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(6)
-; GFX10-NEXT: v_min_f64 v[68:69], v[24:25], v[66:67]
-; GFX10-NEXT: v_cmp_u_f64_e64 s15, v[24:25], v[66:67]
+; GFX10-NEXT: v_min_f64 v[112:113], v[26:27], v[32:33]
; GFX10-NEXT: s_waitcnt vmcnt(5)
-; GFX10-NEXT: v_min_f64 v[66:67], v[26:27], v[0:1]
-; GFX10-NEXT: v_cmp_u_f64_e64 s16, v[26:27], v[0:1]
+; GFX10-NEXT: v_min_f64 v[102:103], v[24:25], v[66:67]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[24:25], v[66:67]
; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_min_f64 v[80:81], v[28:29], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e64 s17, v[28:29], v[2:3]
+; GFX10-NEXT: v_min_f64 v[114:115], v[28:29], v[86:87]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_min_f64 v[86:87], v[30:31], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e64 s18, v[30:31], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v82, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v83, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v84, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v85, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v32, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v33, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v24, v68, 0, s15
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v69, 0x7ff80000, s15
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v66, 0, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v67, 0x7ff80000, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v28, v80, 0, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v81, 0x7ff80000, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v30, v86, 0, s18
-; GFX10-NEXT: v_cndmask_b32_e64 v31, v87, 0x7ff80000, s18
+; GFX10-NEXT: v_min_f64 v[36:37], v[30:31], v[34:35]
+; GFX10-NEXT: v_cndmask_b32_e64 v24, v102, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v25, v103, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[26:27], v[32:33]
+; GFX10-NEXT: v_cndmask_b32_e64 v26, v112, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v27, v113, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[28:29], v[86:87]
+; GFX10-NEXT: v_cndmask_b32_e64 v28, v114, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v29, v115, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[30:31], v[34:35]
+; GFX10-NEXT: v_cndmask_b32_e64 v30, v36, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v31, v37, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v16f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1f
-; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:16
@@ -2831,100 +2832,101 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:72
; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:68
-; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:80
-; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:76
-; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:88
-; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:84
-; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:96
-; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:92
-; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:104
-; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:100
-; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:112
-; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:108
-; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:120
-; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:120
+; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:80
+; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:76
+; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:112
+; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:88
+; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:84
+; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:104
+; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:96
+; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:92
+; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:100
+; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:108
+; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:128
; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:124
-; GFX11-NEXT: s_waitcnt vmcnt(30)
+; GFX11-NEXT: s_waitcnt vmcnt(31)
; GFX11-NEXT: v_min_f64 v[96:97], v[0:1], v[32:33]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[32:33]
-; GFX11-NEXT: s_waitcnt vmcnt(28)
-; GFX11-NEXT: v_min_f64 v[32:33], v[2:3], v[34:35]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[34:35]
-; GFX11-NEXT: s_waitcnt vmcnt(26)
-; GFX11-NEXT: v_min_f64 v[34:35], v[4:5], v[36:37]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[36:37]
-; GFX11-NEXT: s_waitcnt vmcnt(24)
-; GFX11-NEXT: v_min_f64 v[36:37], v[6:7], v[38:39]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[38:39]
-; GFX11-NEXT: s_waitcnt vmcnt(22)
-; GFX11-NEXT: v_min_f64 v[38:39], v[8:9], v[48:49]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[48:49]
-; GFX11-NEXT: s_waitcnt vmcnt(20)
-; GFX11-NEXT: v_min_f64 v[48:49], v[10:11], v[50:51]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[50:51]
-; GFX11-NEXT: s_waitcnt vmcnt(18)
-; GFX11-NEXT: v_min_f64 v[50:51], v[12:13], v[52:53]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[52:53]
-; GFX11-NEXT: s_waitcnt vmcnt(16)
-; GFX11-NEXT: v_min_f64 v[52:53], v[14:15], v[54:55]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[54:55]
-; GFX11-NEXT: s_waitcnt vmcnt(14)
-; GFX11-NEXT: v_min_f64 v[54:55], v[16:17], v[64:65]
-; GFX11-NEXT: v_cmp_u_f64_e64 s7, v[16:17], v[64:65]
+; GFX11-NEXT: s_waitcnt vmcnt(29)
+; GFX11-NEXT: v_min_f64 v[98:99], v[2:3], v[34:35]
+; GFX11-NEXT: s_waitcnt vmcnt(27)
+; GFX11-NEXT: v_min_f64 v[100:101], v[4:5], v[36:37]
+; GFX11-NEXT: s_waitcnt vmcnt(25)
+; GFX11-NEXT: v_min_f64 v[102:103], v[6:7], v[38:39]
+; GFX11-NEXT: s_waitcnt vmcnt(23)
+; GFX11-NEXT: v_min_f64 v[112:113], v[8:9], v[48:49]
+; GFX11-NEXT: s_waitcnt vmcnt(21)
+; GFX11-NEXT: v_min_f64 v[114:115], v[10:11], v[50:51]
+; GFX11-NEXT: s_waitcnt vmcnt(19)
+; GFX11-NEXT: v_min_f64 v[116:117], v[12:13], v[52:53]
+; GFX11-NEXT: s_waitcnt vmcnt(17)
+; GFX11-NEXT: v_min_f64 v[118:119], v[14:15], v[54:55]
+; GFX11-NEXT: s_waitcnt vmcnt(15)
+; GFX11-NEXT: v_min_f64 v[128:129], v[16:17], v[64:65]
; GFX11-NEXT: s_waitcnt vmcnt(12)
-; GFX11-NEXT: v_min_f64 v[64:65], v[18:19], v[66:67]
-; GFX11-NEXT: v_cmp_u_f64_e64 s8, v[18:19], v[66:67]
-; GFX11-NEXT: s_waitcnt vmcnt(10)
-; GFX11-NEXT: v_min_f64 v[66:67], v[20:21], v[68:69]
-; GFX11-NEXT: v_cmp_u_f64_e64 s9, v[20:21], v[68:69]
-; GFX11-NEXT: s_waitcnt vmcnt(8)
-; GFX11-NEXT: v_min_f64 v[68:69], v[22:23], v[70:71]
-; GFX11-NEXT: v_cmp_u_f64_e64 s10, v[22:23], v[70:71]
+; GFX11-NEXT: v_min_f64 v[130:131], v[18:19], v[68:69]
+; GFX11-NEXT: s_waitcnt vmcnt(9)
+; GFX11-NEXT: v_min_f64 v[132:133], v[20:21], v[80:81]
; GFX11-NEXT: s_waitcnt vmcnt(6)
-; GFX11-NEXT: v_min_f64 v[70:71], v[24:25], v[80:81]
-; GFX11-NEXT: v_cmp_u_f64_e64 s11, v[24:25], v[80:81]
+; GFX11-NEXT: v_min_f64 v[32:33], v[22:23], v[84:85]
+; GFX11-NEXT: s_waitcnt vmcnt(5)
+; GFX11-NEXT: v_min_f64 v[134:135], v[24:25], v[82:83]
; GFX11-NEXT: s_waitcnt vmcnt(4)
-; GFX11-NEXT: v_min_f64 v[80:81], v[26:27], v[82:83]
-; GFX11-NEXT: v_cmp_u_f64_e64 s12, v[26:27], v[82:83]
-; GFX11-NEXT: s_waitcnt vmcnt(2)
-; GFX11-NEXT: v_min_f64 v[82:83], v[28:29], v[84:85]
-; GFX11-NEXT: v_cmp_u_f64_e64 s13, v[28:29], v[84:85]
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_min_f64 v[84:85], v[30:31], v[86:87]
-; GFX11-NEXT: v_cmp_u_f64_e64 s14, v[30:31], v[86:87]
+; GFX11-NEXT: v_min_f64 v[144:145], v[26:27], v[70:71]
+; GFX11-NEXT: s_waitcnt vmcnt(3)
+; GFX11-NEXT: v_min_f64 v[146:147], v[28:29], v[66:67]
; GFX11-NEXT: v_cndmask_b32_e64 v0, v96, 0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v97, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v32, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v33, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v34, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v35, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v36, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v37, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v38, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v39, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v48, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v49, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v50, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v51, 0x7ff80000, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v52, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v53, 0x7ff80000, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v54, 0, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v17, v55, 0x7ff80000, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v18, v64, 0, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v19, v65, 0x7ff80000, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v20, v66, 0, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v67, 0x7ff80000, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v68, 0, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v23, v69, 0x7ff80000, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v24, v70, 0, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v25, v71, 0x7ff80000, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v26, v80, 0, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v27, v81, 0x7ff80000, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v28, v82, 0, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v29, v83, 0x7ff80000, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v30, v84, 0, s14
-; GFX11-NEXT: v_cndmask_b32_e64 v31, v85, 0x7ff80000, s14
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_min_f64 v[96:97], v[30:31], v[86:87]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[34:35]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v98, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v99, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[36:37]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v100, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v101, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[38:39]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v102, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v103, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[48:49]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v112, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v113, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[50:51]
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v114, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v115, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[12:13], v[52:53]
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v116, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v117, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[14:15], v[54:55]
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v118, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v119, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[16:17], v[64:65]
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v128, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v17, v129, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[18:19], v[68:69]
+; GFX11-NEXT: v_cndmask_b32_e64 v18, v130, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v19, v131, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[20:21], v[80:81]
+; GFX11-NEXT: v_cndmask_b32_e64 v20, v132, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v21, v133, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[22:23], v[84:85]
+; GFX11-NEXT: v_cndmask_b32_e64 v22, v32, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v23, v33, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[24:25], v[82:83]
+; GFX11-NEXT: v_cndmask_b32_e64 v24, v134, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v25, v135, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[26:27], v[70:71]
+; GFX11-NEXT: v_cndmask_b32_e64 v26, v144, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v27, v145, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[28:29], v[66:67]
+; GFX11-NEXT: v_cndmask_b32_e64 v28, v146, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v29, v147, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[30:31], v[86:87]
+; GFX11-NEXT: v_cndmask_b32_e64 v30, v96, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v31, v97, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v_minimum_v16f64:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.modf.ll b/llvm/test/CodeGen/AMDGPU/llvm.modf.ll
index c03e82a8c03b1..df29ef4df6947 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.modf.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.modf.ll
@@ -28,8 +28,8 @@ define { half, half } @test_modf_f16(half %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7c00
; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7c00
; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
@@ -57,8 +57,8 @@ define half @test_modf_f16_only_use_fract(half %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX9-GISEL-NEXT: v_sub_f16_e32 v1, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
@@ -106,8 +106,8 @@ define { <2 x half>, <2 x half> } @test_modf_v2f16(<2 x half> %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7c00
; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7c00
; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
@@ -115,8 +115,8 @@ define { <2 x half>, <2 x half> } @test_modf_v2f16(<2 x half> %x) {
; GFX9-GISEL-NEXT: v_or_b32_e32 v2, v2, v5
; GFX9-GISEL-NEXT: v_trunc_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-GISEL-NEXT: v_sub_f16_sdwa v6, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_cmp_eq_f16_sdwa s[4:5], |v0|, v3 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xffff8000
+; GFX9-GISEL-NEXT: v_cmp_eq_f16_sdwa s[4:5], |v0|, v3 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, 0, s[4:5]
; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX9-GISEL-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -153,8 +153,8 @@ define <2 x half> @test_modf_v2f16_only_use_fract(<2 x half> %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX9-GISEL-NEXT: v_sub_f16_e32 v1, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
@@ -162,8 +162,8 @@ define <2 x half> @test_modf_v2f16_only_use_fract(<2 x half> %x) {
; GFX9-GISEL-NEXT: v_or_b32_e32 v1, v1, v4
; GFX9-GISEL-NEXT: v_trunc_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-GISEL-NEXT: v_sub_f16_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_cmp_eq_f16_sdwa s[4:5], |v0|, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_cmp_eq_f16_sdwa s[4:5], |v0|, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX9-GISEL-NEXT: v_and_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -214,8 +214,8 @@ define { float, float } @test_modf_f32(float %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, -2
@@ -243,8 +243,8 @@ define float @test_modf_f32_only_use_fract(float %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX9-GISEL-NEXT: v_sub_f32_e32 v1, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v2
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v2, -2
@@ -289,8 +289,8 @@ define { <2 x float>, <2 x float> } @test_modf_v2f32(<2 x float> %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX9-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v4
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5]
; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v5, -2
@@ -329,8 +329,8 @@ define <2 x float> @test_modf_v2f32_only_use_fract(<2 x float> %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, -2
@@ -366,8 +366,8 @@ define { double, double } @test_modf_f64(double %x) {
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x204
-; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s4
; GFX9-SDAG-NEXT: s_brev_b32 s6, -2
+; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s4
; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v5, 0, s[4:5]
@@ -378,15 +378,15 @@ define { double, double } @test_modf_f64(double %x) {
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7ff00000
-; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[4:5]
-; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, -2
-; GFX9-GISEL-NEXT: v_add_f64 v[6:7], v[0:1], -v[2:3]
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v6, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_and_or_b32 v1, v5, v4, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0x7ff00000
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v8, -2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[6:7]
+; GFX9-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, v8, v9
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call { double, double } @llvm.modf.f64(double %x)
ret { double, double } %result
@@ -398,8 +398,8 @@ define double @test_modf_f64_only_use_fract(double %x) {
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x204
-; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s4
; GFX9-SDAG-NEXT: s_brev_b32 s6, -2
+; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s4
; GFX9-SDAG-NEXT: v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[4:5]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v3, 0, s[4:5]
@@ -412,13 +412,13 @@ define double @test_modf_f64_only_use_fract(double %x) {
; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7ff00000
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v7, 0x80000000, v1
; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[4:5]
-; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, -2
; GFX9-GISEL-NEXT: v_add_f64 v[2:3], v[0:1], -v[2:3]
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[4:5]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v3, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_and_or_b32 v1, v2, v4, v1
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, v6, v7
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call { double, double } @llvm.modf.f64(double %x)
%result.0 = extractvalue { double, double } %result, 0
@@ -443,9 +443,9 @@ define { <2 x double>, <2 x double> } @test_modf_v2f64(<2 x double> %x) {
; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[4:5], v[0:1]
; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[6:7], v[2:3]
; GFX9-SDAG-NEXT: s_movk_i32 s6, 0x204
+; GFX9-SDAG-NEXT: s_brev_b32 s8, -2
; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s6
; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[6:7], v[2:3], s6
-; GFX9-SDAG-NEXT: s_brev_b32 s8, -2
; GFX9-SDAG-NEXT: v_add_f64 v[8:9], v[0:1], -v[4:5]
; GFX9-SDAG-NEXT: v_add_f64 v[10:11], v[2:3], -v[6:7]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, 0, s[4:5]
@@ -461,21 +461,21 @@ define { <2 x double>, <2 x double> } @test_modf_v2f64(<2 x double> %x) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[4:5], v[0:1]
; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[6:7], v[2:3]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v9, 0x7ff00000
-; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[8:9]
-; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[6:7], |v[2:3]|, v[8:9]
-; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v8, -2
-; GFX9-GISEL-NEXT: v_add_f64 v[10:11], v[0:1], -v[4:5]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v11, 0x7ff00000
+; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[10:11]
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v14, -2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v15, 0x80000000, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v16, 0x80000000, v3
+; GFX9-GISEL-NEXT: v_add_f64 v[8:9], v[0:1], -v[4:5]
; GFX9-GISEL-NEXT: v_add_f64 v[12:13], v[2:3], -v[6:7]
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v3
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v10, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v10, v13, 0, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v12, 0, s[6:7]
-; GFX9-GISEL-NEXT: v_and_or_b32 v1, v9, v8, v1
-; GFX9-GISEL-NEXT: v_and_or_b32 v3, v10, v8, v3
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v8, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v9, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[2:3]|, v[10:11]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v13, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v12, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, v14, v15
+; GFX9-GISEL-NEXT: v_and_or_b32 v3, v3, v14, v16
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double> %x)
ret { <2 x double>, <2 x double> } %result
@@ -488,9 +488,9 @@ define <2 x double> @test_modf_v2f64_only_use_fract(<2 x double> %x) {
; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[4:5], v[0:1]
; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[6:7], v[2:3]
; GFX9-SDAG-NEXT: s_movk_i32 s6, 0x204
+; GFX9-SDAG-NEXT: s_brev_b32 s8, -2
; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s6
; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[6:7], v[2:3], s6
-; GFX9-SDAG-NEXT: s_brev_b32 s8, -2
; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[4:5]
; GFX9-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], -v[6:7]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
@@ -509,18 +509,18 @@ define <2 x double> @test_modf_v2f64_only_use_fract(<2 x double> %x) {
; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v9, 0x7ff00000
; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[8:9]
-; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[6:7], |v[2:3]|, v[8:9]
-; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v8, -2
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v11, 0x80000000, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v12, 0x80000000, v3
; GFX9-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[4:5]
; GFX9-GISEL-NEXT: v_add_f64 v[6:7], v[2:3], -v[6:7]
-; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v3
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v5, 0, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[6:7]
-; GFX9-GISEL-NEXT: v_and_or_b32 v1, v4, v8, v1
-; GFX9-GISEL-NEXT: v_and_or_b32 v3, v5, v8, v3
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[2:3]|, v[8:9]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, v10, v11
+; GFX9-GISEL-NEXT: v_and_or_b32 v3, v3, v10, v12
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double> %x)
%result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
index 5af56a28cd2f1..659786792adc4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
@@ -44,8 +44,8 @@ define { i64, i1 } @umulo_i64_v_v(i64 %x, i64 %y) {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_add3_u32 v1, v1, v5, v7
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -222,16 +222,16 @@ define { i64, i1 } @smulo_i64_v_v(i64 %x, i64 %y) {
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v9, vcc_lo
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
-; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
+; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v6, v5
+; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v2, v4
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
-; GFX10-NEXT: v_mov_b32_e32 v3, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[5:6]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -257,21 +257,21 @@ define { i64, i1 } @smulo_i64_v_v(i64 %x, i64 %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_subrev_co_ci_u32_e64 v10, null, 0, v9, vcc_lo
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
-; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
-; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v5, vcc_lo
+; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v6, v5
+; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v8, vcc_lo
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
-; GFX11-NEXT: v_mov_b32_e32 v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7
-; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v8, v7 :: v_dual_cndmask_b32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[5:6]
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -308,21 +308,21 @@ define { i64, i1 } @smulo_i64_v_v(i64 %x, i64 %y) {
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_subrev_co_ci_u32_e64 v10, null, 0, v9, vcc_lo
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
+; GFX12-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
-; GFX12-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX12-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4
+; GFX12-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
+; GFX12-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo
+; GFX12-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_sub_co_u32 v4, vcc_lo, v2, v4
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v5, vcc_lo
+; GFX12-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v8, vcc_lo
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX12-NEXT: v_dual_cndmask_b32 v3, v8, v7 :: v_dual_cndmask_b32 v2, v2, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[5:6]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -729,8 +729,8 @@ define { i64, i1 } @smulo_i64_v_4(i64 %i) {
; GFX9-NEXT: v_alignbit_b32 v3, v1, v0, 30
; GFX9-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, v[5:6], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -741,9 +741,9 @@ define { i64, i1 } @smulo_i64_v_4(i64 %i) {
; GFX10-NEXT: v_alignbit_b32 v3, v1, v0, 30
; GFX10-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: smulo_i64_v_4:
@@ -754,9 +754,9 @@ define { i64, i1 } @smulo_i64_v_4(i64 %i) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: smulo_i64_v_4:
@@ -771,10 +771,9 @@ define { i64, i1 } @smulo_i64_v_4(i64 %i) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
bb:
%umulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %i, i64 4)
@@ -798,11 +797,11 @@ define { i64, i1 } @umulo_i64_v_4(i64 %i) {
; GFX9-LABEL: umulo_i64_v_4:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v7, 0x3fffffff, v1
; GFX9-NEXT: v_mov_b32_e32 v6, v0
-; GFX9-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
-; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, v[6:7], v[0:1]
; GFX9-NEXT: v_alignbit_b32 v3, v1, v0, 30
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, v[6:7], v[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v3
@@ -811,26 +810,26 @@ define { i64, i1 } @umulo_i64_v_4(i64 %i) {
; GFX10-LABEL: umulo_i64_v_4:
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v7, 0x3fffffff, v1
; GFX10-NEXT: v_mov_b32_e32 v6, v0
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
; GFX10-NEXT: v_alignbit_b32 v3, v1, v0, 30
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: umulo_i64_v_4:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1
; GFX11-NEXT: v_alignbit_b32 v3, v1, v0, 30
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: umulo_i64_v_4:
@@ -840,14 +839,14 @@ define { i64, i1 } @umulo_i64_v_4(i64 %i) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1
; GFX12-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1
; GFX12-NEXT: v_alignbit_b32 v3, v1, v0, 30
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]
-; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
bb:
%umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %i, i64 4)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
index 802ffc1e7ea7b..83a4d421f11f7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
@@ -196,17 +196,16 @@ define amdgpu_kernel void @round_v2f32(ptr addrspace(1) %out, <2 x float> %in) #
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_ge_f32_e64 s4, |v1|, 0.5
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_ge_f32_e64 s4, |v3|, 0.5
-; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s3
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-NEXT: v_add_f32_e32 v1, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s2
; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: v_add_f32_e32 v0, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v1, v0, v1 :: v_dual_add_f32 v0, v2, v3
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX11-NEXT: s_endpgm
;
@@ -371,23 +370,21 @@ define amdgpu_kernel void @round_v4f32(ptr addrspace(1) %out, <4 x float> %in) #
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v2|, 0.5
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v3|, 0.5
-; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s6
; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v6|, 0.5
-; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v3, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1.0, s6
; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v7|, 0.5
-; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfi_b32 v6, 0x7fffffff, v6, s1
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s6
+; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s3
+; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v3, s2
+; GFX11-NEXT: v_bfi_b32 v6, 0x7fffffff, v6, s1
; GFX11-NEXT: s_mov_b32 s6, -1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v8
; GFX11-NEXT: v_dual_add_f32 v1, v4, v6 :: v_dual_add_f32 v0, v5, v7
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[4:7], 0
; GFX11-NEXT: s_endpgm
@@ -647,59 +644,52 @@ define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #
; GFX11-NEXT: v_trunc_f32_e32 v4, s9
; GFX11-NEXT: v_trunc_f32_e32 v8, s8
; GFX11-NEXT: v_trunc_f32_e32 v5, s15
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_sub_f32 v2, s11, v0 :: v_dual_sub_f32 v3, s10, v1
-; GFX11-NEXT: v_sub_f32_e32 v7, s9, v4
-; GFX11-NEXT: v_trunc_f32_e32 v9, s13
-; GFX11-NEXT: v_sub_f32_e32 v11, s8, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v2|, 0.5
-; GFX11-NEXT: v_sub_f32_e32 v12, s15, v5
; GFX11-NEXT: v_trunc_f32_e32 v6, s14
-; GFX11-NEXT: v_sub_f32_e32 v14, s13, v9
-; GFX11-NEXT: v_trunc_f32_e32 v10, s12
+; GFX11-NEXT: v_dual_sub_f32 v7, s9, v4 :: v_dual_sub_f32 v12, s15, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v2|, 0.5
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v3|, 0.5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s2
+; GFX11-NEXT: v_trunc_f32_e32 v9, s13
+; GFX11-NEXT: v_sub_f32_e32 v11, s8, v8
+; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s11
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v7|, 0.5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfi_b32 v16, 0x7fffffff, v3, s10
+; GFX11-NEXT: v_dual_sub_f32 v13, s14, v6 :: v_dual_sub_f32 v14, s13, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v11|, 0.5
-; GFX11-NEXT: v_sub_f32_e32 v13, s14, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v16
-; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v12|, 0.5
-; GFX11-NEXT: v_add_f32_e32 v1, v4, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, s8
+; GFX11-NEXT: v_trunc_f32_e32 v10, s12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 1.0, s2
+; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v16
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v13|, 0.5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_bfi_b32 v12, 0x7fffffff, v12, s15
; GFX11-NEXT: v_cndmask_b32_e64 v13, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v14|, 0.5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_add_f32_e32 v7, v5, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, 1.0, s2
+; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s9
+; GFX11-NEXT: v_bfi_b32 v12, 0x7fffffff, v12, s15
; GFX11-NEXT: v_bfi_b32 v13, 0x7fffffff, v13, s14
; GFX11-NEXT: v_sub_f32_e32 v15, s12, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, 1.0, s2
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v14, s13
+; GFX11-NEXT: v_add_f32_e32 v1, v4, v7
+; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, s8
; GFX11-NEXT: v_add_f32_e32 v6, v6, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v15|, 0.5
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v14, s13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v15, 0, 1.0, s2
+; GFX11-NEXT: v_add_f32_e32 v7, v5, v12
; GFX11-NEXT: v_dual_add_f32 v5, v9, v0 :: v_dual_add_f32 v0, v8, v11
; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v15, s12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v4, v10, v4
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 offset:16
@@ -761,6 +751,8 @@ define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #
; R600-NEXT: ADD T0.X, T3.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT: ADD_INT * T2.X, PS, literal.x,
+; R600-NEXT: 4(5.605194e-45), 0(0.000000e+00)
%result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
store <8 x float> %result, ptr addrspace(1) %out
ret void
@@ -913,11 +905,11 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX6-NEXT: v_sub_f32_e32 v5, v1, v3
; GFX6-NEXT: v_trunc_f32_e32 v2, v0
; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v5|, 0.5
-; GFX6-NEXT: v_sub_f32_e32 v4, v0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[2:3]
+; GFX6-NEXT: v_sub_f32_e32 v4, v0, v2
; GFX6-NEXT: v_bfi_b32 v1, s4, v5, v1
-; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v4|, 0.5
; GFX6-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v4|, 0.5
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[2:3]
; GFX6-NEXT: v_bfi_b32 v0, s4, v3, v0
; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -1032,16 +1024,16 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e64 s4, |v3|, 0.5
-; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x3c00, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, s3
; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s2
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_f16_e32 v1, v1, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index b0da72184f050..43e6b1f1516b8 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -6871,8 +6871,8 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2
@@ -6990,8 +6990,8 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -7232,8 +7232,8 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2 offset:65532
@@ -7351,8 +7351,8 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -7590,8 +7590,8 @@ define void @local_atomic_fadd_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
@@ -7706,8 +7706,8 @@ define void @local_atomic_fadd_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
@@ -7934,8 +7934,8 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4 offset:65532
@@ -8050,8 +8050,8 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 43d77d0afa8c6..ea310fb1edcec 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -6792,8 +6792,8 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2
@@ -6911,8 +6911,8 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -7276,8 +7276,8 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2 offset:65532
@@ -7395,8 +7395,8 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -7750,8 +7750,8 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
@@ -7866,8 +7866,8 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
@@ -8210,8 +8210,8 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4 offset:65532
@@ -8326,8 +8326,8 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 1759a212c6ea3..2741809951a60 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -6792,8 +6792,8 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2
@@ -6911,8 +6911,8 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -7276,8 +7276,8 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2 offset:65532
@@ -7395,8 +7395,8 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -7750,8 +7750,8 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
@@ -7866,8 +7866,8 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
@@ -8210,8 +8210,8 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4 offset:65532
@@ -8326,8 +8326,8 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index 5feb76edf3d17..6e8733b36e730 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -7574,8 +7574,8 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2
@@ -7693,8 +7693,8 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -8058,8 +8058,8 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX10-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v2, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v2, v0, v4, v2 offset:65532
@@ -8177,8 +8177,8 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v2, v5, v2, 16
@@ -8532,8 +8532,8 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
@@ -8648,8 +8648,8 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
@@ -8992,8 +8992,8 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX10-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX10-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v4, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4 offset:65532
@@ -9108,8 +9108,8 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX8-NEXT: v_alignbit_b32 v4, v5, v4, 16
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
index 199b79932402f..2a7dd4c31b9bd 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
@@ -532,16 +532,16 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v2, s1, s6, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-NEXT: v_add_co_u32 v0, s1, s4, v0
-; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
+; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: .LBB4_2: ; %for.body
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xffffff50, v2
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v3, vcc_lo
@@ -574,16 +574,16 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX12-SPREFETCH-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX12-SPREFETCH-NEXT: s_wait_kmcnt 0x0
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, s1, s6, v0
-; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v0, s1, s4, v0
-; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
+; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: .LBB4_2: ; %for.body
; GFX12-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v4, vcc_lo, 0xffffff50, v2
; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v3, vcc_lo
@@ -617,16 +617,16 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX12ES2-SPREFETCH-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX12ES2-SPREFETCH-NEXT: s_wait_kmcnt 0x0
; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v2, s1, s6, v0
-; GFX12ES2-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12ES2-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v0, s1, s4, v0
-; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12ES2-SPREFETCH-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
+; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12ES2-SPREFETCH-NEXT: .LBB4_2: ; %for.body
; GFX12ES2-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12ES2-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12ES2-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v4, vcc_lo, 0xffffff50, v2
; GFX12ES2-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v3, vcc_lo
@@ -719,12 +719,12 @@ define amdgpu_kernel void @copy_global_divergent(ptr addrspace(1) nocapture %d,
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v2, s1, s6, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-NEXT: v_add_co_u32 v0, s1, s4, v0
-; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
+; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: .LBB5_2: ; %for.body
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -757,12 +757,12 @@ define amdgpu_kernel void @copy_global_divergent(ptr addrspace(1) nocapture %d,
; GFX12-SPREFETCH-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX12-SPREFETCH-NEXT: s_wait_kmcnt 0x0
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, s1, s6, v0
-; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v0, s1, s4, v0
-; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
+; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: .LBB5_2: ; %for.body
; GFX12-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -796,12 +796,12 @@ define amdgpu_kernel void @copy_global_divergent(ptr addrspace(1) nocapture %d,
; GFX12ES2-SPREFETCH-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX12ES2-SPREFETCH-NEXT: s_wait_kmcnt 0x0
; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v2, s1, s6, v0
-; GFX12ES2-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12ES2-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v0, s1, s4, v0
-; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12ES2-SPREFETCH-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
+; GFX12ES2-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
; GFX12ES2-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12ES2-SPREFETCH-NEXT: .LBB5_2: ; %for.body
; GFX12ES2-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/lrint.ll b/llvm/test/CodeGen/AMDGPU/lrint.ll
index ff9e382653efc..10da359850943 100644
--- a/llvm/test/CodeGen/AMDGPU/lrint.ll
+++ b/llvm/test/CodeGen/AMDGPU/lrint.ll
@@ -806,22 +806,22 @@ define <2 x i64> @intrinsic_lrint_v2i64_v2f32(<2 x float> %arg) {
; GFX11-GISEL-NEXT: v_fma_f32 v2, 0xcf800000, v4, |v2|
; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v5, |v3|
; GFX11-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v2
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v4
-; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v4, v5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX11-GISEL-NEXT: v_xor_b32_e32 v4, v4, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_xor_b32_e32 v5, v0, v3
-; GFX11-GISEL-NEXT: v_xor_b32_e32 v4, v4, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_sub_co_ci_u32_e64 v1, null, v2, v6, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_sub_co_u32 v2, vcc_lo, v5, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_sub_co_ci_u32_e64 v3, null, v4, v3, vcc_lo
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lround.ll b/llvm/test/CodeGen/AMDGPU/lround.ll
index 4f0a243477c98..641ad57585a46 100644
--- a/llvm/test/CodeGen/AMDGPU/lround.ll
+++ b/llvm/test/CodeGen/AMDGPU/lround.ll
@@ -1065,12 +1065,12 @@ define <2 x i32> @intrinsic_lround_v2i32_v2f32(<2 x float> %arg) {
; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v4|, 0.5
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s4
; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v5|, 0.5
-; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s4
-; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
; GFX10-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
-; GFX10-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX10-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1084,12 +1084,12 @@ define <2 x i32> @intrinsic_lround_v2i32_v2f32(<2 x float> %arg) {
; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v4|, 0.5
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s4
; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v5|, 0.5
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s4
-; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v5
-; GFX10-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX10-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1104,10 +1104,10 @@ define <2 x i32> @intrinsic_lround_v2i32_v2f32(<2 x float> %arg) {
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s0
; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v5|, 0.5
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
; GFX11-SDAG-NEXT: v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1126,10 +1126,10 @@ define <2 x i32> @intrinsic_lround_v2i32_v2f32(<2 x float> %arg) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s0
; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v5|, 0.5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v5
; GFX11-GISEL-NEXT: v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1236,28 +1236,28 @@ define <2 x i64> @intrinsic_lround_v2i64_v2f32(<2 x float> %arg) {
; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v4|, 0.5
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s4
; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v5|, 0.5
-; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s4
-; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
; GFX10-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
-; GFX10-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX10-SDAG-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v0|
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v0, v0
; GFX10-SDAG-NEXT: v_trunc_f32_e32 v1, v1
+; GFX10-SDAG-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v0|
; GFX10-SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v0
-; GFX10-SDAG-NEXT: v_floor_f32_e32 v2, v2
; GFX10-SDAG-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v1|
; GFX10-SDAG-NEXT: v_ashrrev_i32_e32 v6, 31, v1
-; GFX10-SDAG-NEXT: v_fma_f32 v4, 0xcf800000, v2, |v0|
+; GFX10-SDAG-NEXT: v_floor_f32_e32 v2, v2
; GFX10-SDAG-NEXT: v_floor_f32_e32 v3, v3
+; GFX10-SDAG-NEXT: v_fma_f32 v4, 0xcf800000, v2, |v0|
; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-SDAG-NEXT: v_fma_f32 v0, 0xcf800000, v3, |v1|
-; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v4
; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v4
; GFX10-SDAG-NEXT: v_xor_b32_e32 v2, v2, v5
; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-SDAG-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX10-SDAG-NEXT: v_xor_b32_e32 v3, v3, v6
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX10-SDAG-NEXT: v_xor_b32_e32 v4, v0, v6
; GFX10-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v5
; GFX10-SDAG-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v2, v5, vcc_lo
@@ -1275,29 +1275,29 @@ define <2 x i64> @intrinsic_lround_v2i64_v2f32(<2 x float> %arg) {
; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v4|, 0.5
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s4
; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v5|, 0.5
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s4
-; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v5
-; GFX10-GISEL-NEXT: v_trunc_f32_e32 v2, v0
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v2, v0
; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v0
-; GFX10-GISEL-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v2|
; GFX10-GISEL-NEXT: v_trunc_f32_e32 v3, v1
-; GFX10-GISEL-NEXT: v_floor_f32_e32 v4, v4
+; GFX10-GISEL-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v2|
; GFX10-GISEL-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v3|
-; GFX10-GISEL-NEXT: v_fma_f32 v2, 0xcf800000, v4, |v2|
+; GFX10-GISEL-NEXT: v_floor_f32_e32 v4, v4
; GFX10-GISEL-NEXT: v_floor_f32_e32 v5, v5
+; GFX10-GISEL-NEXT: v_fma_f32 v2, 0xcf800000, v4, |v2|
; GFX10-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v5, |v3|
; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v2
; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v4
-; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v4, v5
; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v4, v5
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
-; GFX10-GISEL-NEXT: v_xor_b32_e32 v4, v4, v3
; GFX10-GISEL-NEXT: v_xor_b32_e32 v5, v0, v3
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v4, v4, v3
; GFX10-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v6
; GFX10-GISEL-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v2, v6, vcc_lo
; GFX10-GISEL-NEXT: v_sub_co_u32 v2, vcc_lo, v5, v3
@@ -1315,10 +1315,10 @@ define <2 x i64> @intrinsic_lround_v2i64_v2f32(<2 x float> %arg) {
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s0
; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v5|, 0.5
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
; GFX11-SDAG-NEXT: v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1328,25 +1328,25 @@ define <2 x i64> @intrinsic_lround_v2i64_v2f32(<2 x float> %arg) {
; GFX11-SDAG-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v0|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v0
; GFX11-SDAG-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v1|
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SDAG-NEXT: v_floor_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v6, 31, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_floor_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_floor_f32_e32 v3, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_fma_f32 v4, 0xcf800000, v2, |v0|
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_fma_f32 v0, 0xcf800000, v3, |v1|
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v4
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v4
; GFX11-SDAG-NEXT: v_xor_b32_e32 v2, v2, v5
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_xor_b32_e32 v3, v3, v6
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v0, v6
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v5
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v2, v5, vcc_lo
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1365,10 +1365,10 @@ define <2 x i64> @intrinsic_lround_v2i64_v2f32(<2 x float> %arg) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s0
; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v5|, 0.5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v5
; GFX11-GISEL-NEXT: v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index 4b658de512f81..24df07b8896fd 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -472,19 +472,19 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_xor_b32_e32 v5, v60, v58
; CHECK-NEXT: v_lshrrev_b64 v[3:4], 16, v[45:46]
; CHECK-NEXT: v_mad_u64_u32 v[7:8], null, 0x180, v73, s[66:67]
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; CHECK-NEXT: v_lshrrev_b64 v[1:2], 16, v[56:57]
-; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; CHECK-NEXT: v_lshlrev_b32_e32 v9, 6, v72
+; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; CHECK-NEXT: v_lshlrev_b32_e32 v11, 12, v63
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; CHECK-NEXT: v_xor_b32_e32 v6, v61, v59
; CHECK-NEXT: ; implicit-def: $vgpr42
; CHECK-NEXT: ; implicit-def: $vgpr43
; CHECK-NEXT: ; implicit-def: $vgpr44
-; CHECK-NEXT: v_add_co_u32 v7, vcc_lo, v7, v0
; CHECK-NEXT: v_or_b32_e32 v4, v10, v4
; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v45
; CHECK-NEXT: v_or3_b32 v9, v9, v11, v62
+; CHECK-NEXT: v_add_co_u32 v7, vcc_lo, v7, v0
; CHECK-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
; CHECK-NEXT: v_lshrrev_b64 v[5:6], 16, v[5:6]
; CHECK-NEXT: v_or_b32_e32 v2, v10, v2
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index a19853adabb58..51bcac079c0bd 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -856,13 +856,13 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX10-LABEL: v_maximumnum_v2bf16_nnan:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v5, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v5, v4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, v0, s4
; GFX10-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
@@ -1207,15 +1207,15 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, v0, v2, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
@@ -1241,9 +1241,9 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v9, v5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
@@ -2167,9 +2167,9 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v2
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v8, v13
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
@@ -2301,35 +2301,34 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
@@ -2479,40 +2478,40 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
@@ -2717,23 +2716,23 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v9, v8
; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v12, v11
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v7, v6
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v9, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v12, v11
; GFX10-NEXT: v_cndmask_b32_e64 v8, v14, v13, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v7, v6
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v13
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
@@ -2808,48 +2807,47 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v11
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v6, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2924,48 +2922,50 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v11
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v14, v13, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v6, 0xffff0000, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)
@@ -3386,48 +3386,48 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v11, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v12, s5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v11, v11
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v8
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v11, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s4
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v0
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v9, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v2
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v9, v9
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v10, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v9, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v11, v11
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v0, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s4
-; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v10, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v10, v9
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v13, v11
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v15, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v0, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v12
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v15, v14
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
@@ -3594,9 +3594,9 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v11, 16, v8
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
@@ -3609,61 +3609,58 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
@@ -3852,10 +3849,10 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v15, 16, v9
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v11, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
@@ -3866,67 +3863,66 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v14
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v12, v10, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v11
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v7
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v14
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v14
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
@@ -4489,33 +4485,33 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v14, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v12, v12
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v12, v14, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v17, v17
; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v9
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v12
; GFX10-NEXT: v_cndmask_b32_e64 v14, v15, v13, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v13
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v16, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v3
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v9, s4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v18, v19
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v13, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v3, s4
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
@@ -4780,40 +4776,40 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v12, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v9, s0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v18, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
@@ -4826,21 +4822,22 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v17, v16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
@@ -5118,50 +5115,50 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v12, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v17
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v9, s0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v18, v19
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v13, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
@@ -5175,11 +5172,13 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v17, v16
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -5187,13 +5186,12 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
@@ -6237,45 +6235,45 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v21, v22
; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX10-NEXT: v_cmp_u_f32_e64 s5, v20, v20
; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v18, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v16
+; GFX10-NEXT: v_cmp_u_f32_e64 s5, v20, v20
; GFX10-NEXT: v_cndmask_b32_e64 v20, v22, v21, s5
-; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v12
; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v19
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v24, v24
; GFX10-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
-; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX10-NEXT: v_cndmask_b32_e64 v17, v21, v20, s4
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v17
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v21, v21
-; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v24, v25
; GFX10-NEXT: v_cndmask_b32_e64 v21, v23, v22, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v18
-; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v24, v25
; GFX10-NEXT: v_cndmask_b32_e64 v23, v17, v20, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v21, s5
; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v21, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v22
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v17, v17
+; GFX10-NEXT: v_cndmask_b32_e64 v25, v25, v24, s5
; GFX10-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v22
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v25, v24, s5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v20
; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v10
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v25
; GFX10-NEXT: v_cndmask_b32_e32 v19, v24, v25, vcc_lo
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v25
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v19
; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v21, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
@@ -6283,14 +6281,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v18, v24
-; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v20, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v21
; GFX10-NEXT: v_cndmask_b32_e64 v24, v19, v25, s5
; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v10
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v27, v27
+; GFX10-NEXT: v_cndmask_b32_e64 v27, v29, v28, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v20, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v24
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v29, v28, s5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v21
; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v1
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v20
; GFX10-NEXT: v_cndmask_b32_e32 v19, v28, v27, vcc_lo
@@ -6305,10 +6303,10 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
; GFX10-NEXT: v_cndmask_b32_e64 v20, v19, v27, s7
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v26, v29, v28, s7
; GFX10-NEXT: v_cndmask_b32_e32 v19, v22, v21, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v29, v28, s7
; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v0
; GFX10-NEXT: v_cndmask_b32_e32 v22, v28, v26, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
@@ -6321,136 +6319,130 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v21, v24
; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v27, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v21, v22, v26, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v25, v25
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v29, v28, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v27, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v7
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v21
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v29, v28, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v14
; GFX10-NEXT: v_cndmask_b32_e32 v24, v28, v22, vcc_lo
-; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v28, v28
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v28, v28
; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v6
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v7, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v26
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v25, v27
; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v24, v24, v22, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v28, v28
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v26, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v14, s5
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v27, v25
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v7, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v29, v29
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v6, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v25
+; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v26, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v14
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v22
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v25
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v5
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v27, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v13
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v6, s7
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v25, v25
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s7
+; GFX10-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v14
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v5
; GFX10-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v25, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v26, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v5, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v4, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v25, v25
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v25, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v11
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v4, s7
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v27, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s7
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v15, v15
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s7
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v15, v15
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s6
-; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x5040100
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v2
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v14, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v13, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v4
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v14, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v15, v15
-; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v13, v13
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v2, s6
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v2, s6
-; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v14, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v10
+; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v14, v13
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s6
; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v24, v15
-; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v26, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v26, v25
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v2, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v8
; GFX10-NEXT: s_and_b32 s5, s5, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v1
@@ -6458,16 +6450,22 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v14
-; GFX10-NEXT: v_perm_b32 v3, v23, v3, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v2
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v11
; GFX10-NEXT: s_and_b32 s5, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, v1, s5
; GFX10-NEXT: s_and_b32 s5, s7, s8
+; GFX10-NEXT: v_perm_b32 v3, v23, v3, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s5
; GFX10-NEXT: s_and_b32 s5, s9, s10
; GFX10-NEXT: v_perm_b32 v1, v21, v1, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s5
+; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x5040100
; GFX10-NEXT: v_perm_b32 v0, v22, v0, 0x5040100
+; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x5040100
+; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v2, v20, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -6817,75 +6815,73 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v19
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v21, v20, s0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v21, v23, v22, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v22, v21 :: v_dual_lshlrev_b32 v25, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v25
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v24, v23, s1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v29, v28, s1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
@@ -6897,17 +6893,15 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v20, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v24, v25, s3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v27, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v26, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
@@ -6916,162 +6910,147 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v23
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v24, v26, s1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v29, v28, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v28, v23 :: v_dual_lshlrev_b32 v29, 16, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v25, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v23, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v14, s1
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v27, v25
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v23
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v13
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v14
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, v13, v5, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v25, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s3
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v10, s2
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v8, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v14, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v14, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1
@@ -7079,20 +7058,22 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s5, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v20, v2, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7501,27 +7482,27 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v19
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v21, v20, s0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -7530,61 +7511,62 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v18
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v22, v21 :: v_dual_lshlrev_b32 v25, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v25
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v24, v23, s1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v25, v29, v28, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v19
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v21
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v25
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v25
@@ -7592,16 +7574,15 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v20, v26
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v24, v25, s3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v27, v27
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v26, vcc_lo
@@ -7613,186 +7594,178 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v23
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v24, v26, s1
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v23, v29, v28, s1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v28, v23 :: v_dual_lshlrev_b32 v29, 16, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v6
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v26
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v25, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v23, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v23
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v14, s1
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v27, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v23
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v14
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v14
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v26, 16, v5
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v13, v13, v5, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v25, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s3
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s3
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v10, s2
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX12-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v8, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v14, v13
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v14, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1
@@ -7801,21 +7774,25 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX12-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s5, s6
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
+; GFX12-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v20, v2, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x bfloat> @llvm.maximumnum.v16bf16(<16 x bfloat> %x, <16 x bfloat> %y)
@@ -8041,12 +8018,12 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v12
; GFX8-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
-; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX8-NEXT: v_cndmask_b32_e32 v37, v51, v50, vcc
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
+; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v31
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX8-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v32
; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v35
@@ -8599,12 +8576,12 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v12
; GFX900-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc
; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
-; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX900-NEXT: v_cndmask_b32_e32 v37, v51, v50, vcc
; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
+; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc
-; GFX900-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v31
+; GFX900-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX900-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[4:5]
; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v32
; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v35
@@ -9143,14 +9120,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX950-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc
; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX950-NEXT: v_cmp_u_f32_e64 s[0:1], v48, v48
+; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v31
; GFX950-NEXT: v_cndmask_b32_e32 v37, v52, v51, vcc
; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
-; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v31
-; GFX950-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[0:1]
+; GFX950-NEXT: v_cmp_u_f32_e64 s[0:1], v48, v48
+; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v35
; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[0:1]
; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v32
-; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v35
; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v38
; GFX950-NEXT: v_cmp_gt_f32_e64 s[2:3], v39, v48
; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31
@@ -9784,14 +9761,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v35, v33
; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v39
; GFX10-NEXT: v_cndmask_b32_e32 v38, v49, v31, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v31
+; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
; GFX10-NEXT: v_cndmask_b32_e64 v33, v53, v52, s6
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v36, v37
; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v38
; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v9
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v35, v35
; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v25
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v35, v35
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v33
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v49, v50
; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v9
@@ -9799,93 +9776,93 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v36, v36
; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v25
; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v24
-; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v31, vcc_lo
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v50
; GFX10-NEXT: v_cndmask_b32_e64 v35, v49, v37, s6
; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v50
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v36, v36
+; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v31, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v53, v37, v35, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v49, v49
; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v24
-; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v7
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v49, v49
; GFX10-NEXT: v_cndmask_b32_e64 v36, v54, v52, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s7, v37, v37
+; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v7
; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v51, v55
+; GFX10-NEXT: v_cmp_u_f32_e64 s7, v37, v37
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v35
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v53
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v36
; GFX10-NEXT: v_cndmask_b32_e64 v66, v52, v36, s7
; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v23
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v49, v49
-; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v6
-; GFX10-NEXT: v_cmp_gt_f32_e64 s9, v51, v54
-; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX10-NEXT: v_cndmask_b32_e64 v37, v65, v64, s7
-; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52
+; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v22
-; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v22
-; GFX10-NEXT: v_cmp_u_f32_e64 s10, v51, v51
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v37
+; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v53
; GFX10-NEXT: v_cndmask_b32_e64 v64, v64, v37, s7
+; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v22
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v49, v49
-; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v64
; GFX10-NEXT: v_cndmask_b32_e64 v49, v67, v65, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v37
+; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v64
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52
+; GFX10-NEXT: v_cmp_gt_f32_e64 s9, v51, v54
+; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v66
; GFX10-NEXT: v_cndmask_b32_e64 v65, v65, v49, s7
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v68, v69
; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v69, 16, v20
+; GFX10-NEXT: v_cmp_u_f32_e64 s10, v51, v51
; GFX10-NEXT: v_cndmask_b32_e64 v51, v52, v54, s10
-; GFX10-NEXT: v_cmp_gt_f32_e64 s8, v55, v67
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v36
; GFX10-NEXT: v_cmp_u_f32_e64 s10, v68, v68
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v65
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v51
; GFX10-NEXT: v_cndmask_b32_e64 v52, v70, v69, s10
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v66
; GFX10-NEXT: v_cmp_u_f32_e64 s10, v71, v71
-; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v52
; GFX10-NEXT: v_cndmask_b32_e64 v70, v54, v51, s10
; GFX10-NEXT: v_cmp_u_f32_e64 s10, v80, v80
+; GFX10-NEXT: v_cndmask_b32_e64 v69, v69, v52, s10
; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s8, v55, v67
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v65
+; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v19
; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v51
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v70
-; GFX10-NEXT: v_cndmask_b32_e64 v69, v69, v52, s10
-; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v54
-; GFX10-NEXT: v_cmp_gt_f32_e64 s11, v68, v81
+; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v52
; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v69
+; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v54
; GFX10-NEXT: v_cndmask_b32_e64 v54, v80, v71, s10
; GFX10-NEXT: v_cmp_gt_f32_e64 s10, v55, v67
; GFX10-NEXT: v_and_b32_e32 v67, 0xffff0000, v19
+; GFX10-NEXT: v_cmp_gt_f32_e64 s11, v68, v81
; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v2
; GFX10-NEXT: v_cmp_gt_f32_e64 s12, v82, v83
; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v18
; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX10-NEXT: v_cmp_u_f32_e64 s13, v67, v67
; GFX10-NEXT: v_and_b32_e32 v82, 0xffff0000, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v54
+; GFX10-NEXT: v_cmp_u_f32_e64 s13, v67, v67
; GFX10-NEXT: v_cndmask_b32_e64 v67, v71, v54, s13
; GFX10-NEXT: v_cmp_u_f32_e64 s13, v68, v68
-; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v67
; GFX10-NEXT: v_cndmask_b32_e64 v68, v81, v80, s13
; GFX10-NEXT: v_cmp_u_f32_e64 s13, v82, v82
+; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v17
; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v54
+; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v67
; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v68, s13
; GFX10-NEXT: v_cmp_u_f32_e64 s13, v71, v71
; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v17
; GFX10-NEXT: v_cndmask_b32_e64 v82, v82, v81, s13
-; GFX10-NEXT: v_cmp_u_f32_e64 s14, v71, v71
; GFX10-NEXT: v_cmp_gt_f32_e64 s13, v55, v83
; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v68
; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v80
-; GFX10-NEXT: v_cmp_eq_u16_e64 s22, 0, v82
+; GFX10-NEXT: v_cmp_u_f32_e64 s14, v71, v71
; GFX10-NEXT: v_cndmask_b32_e64 v71, v81, v82, s14
; GFX10-NEXT: v_cndmask_b32_e64 v67, v67, v54, s13
+; GFX10-NEXT: v_cmp_eq_u16_e64 s22, 0, v82
; GFX10-NEXT: v_cmp_gt_f32_e64 s14, v55, v83
; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v82
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v71
@@ -9897,9 +9874,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
; GFX10-NEXT: v_cndmask_b32_e64 v83, v83, v81, s16
; GFX10-NEXT: v_cmp_u_f32_e64 s16, v55, v55
-; GFX10-NEXT: v_cmp_eq_u16_e64 s23, 0, v83
; GFX10-NEXT: v_cndmask_b32_e64 v55, v81, v83, s16
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v83
+; GFX10-NEXT: v_cmp_eq_u16_e64 s23, 0, v83
; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v55
; GFX10-NEXT: v_cmp_gt_f32_e64 s16, v81, v84
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v14
@@ -9908,8 +9885,8 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v30
; GFX10-NEXT: v_cndmask_b32_e64 v84, v14, v30, s17
; GFX10-NEXT: v_cmp_u_f32_e64 s17, v81, v81
-; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v84
; GFX10-NEXT: v_cndmask_b32_e64 v81, v30, v84, s17
+; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v84
; GFX10-NEXT: v_cmp_eq_u16_e64 s24, 0, v84
; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v81
; GFX10-NEXT: v_cmp_gt_f32_e64 s17, v86, v85
@@ -9929,13 +9906,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v30
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v86, s19
; GFX10-NEXT: v_cmp_u_f32_e64 s19, v13, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v14
; GFX10-NEXT: v_cndmask_b32_e64 v13, v86, v14, s19
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v14
; GFX10-NEXT: v_cmp_eq_u16_e64 s20, 0, v14
; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v13
; GFX10-NEXT: v_cmp_gt_f32_e64 s19, v30, v86
-; GFX10-NEXT: v_and_b32_e32 v86, 0xffff0000, v15
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v14, s19
+; GFX10-NEXT: v_and_b32_e32 v86, 0xffff0000, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v13
; GFX10-NEXT: v_cmp_eq_f32_e64 s19, 0, v30
; GFX10-NEXT: s_and_b32 s19, s19, s20
@@ -9973,53 +9950,53 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v48
; GFX10-NEXT: v_cmp_u_f32_e64 s18, v29, v29
+; GFX10-NEXT: v_cndmask_b32_e64 v81, v12, v28, s18
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v28
-; GFX10-NEXT: v_cmp_eq_u16_e64 s21, 0, v68
; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v50
-; GFX10-NEXT: v_cndmask_b32_e64 v81, v12, v28, s18
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX10-NEXT: v_cmp_u_f32_e64 s18, v29, v29
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v38, v31, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v53
+; GFX10-NEXT: v_cmp_eq_u16_e64 s21, 0, v68
; GFX10-NEXT: v_cmp_u_f32_e64 s19, v12, v12
; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v32, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v53
+; GFX10-NEXT: v_cmp_u_f32_e64 s18, v29, v29
+; GFX10-NEXT: v_cndmask_b32_e64 v29, v38, v31, s4
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v37
; GFX10-NEXT: v_cmp_eq_f32_e64 s8, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v64
-; GFX10-NEXT: v_cndmask_b32_e64 v96, v11, v27, s19
-; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v49
; GFX10-NEXT: v_cndmask_b32_e32 v30, v39, v33, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v65
; GFX10-NEXT: s_and_b32 vcc_lo, s6, s20
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v49
; GFX10-NEXT: v_cndmask_b32_e32 v31, v48, v35, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v65
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX10-NEXT: v_cndmask_b32_e64 v96, v11, v27, s19
+; GFX10-NEXT: v_cndmask_b32_e64 v97, v28, v81, s18
; GFX10-NEXT: v_cmp_eq_f32_e64 s10, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v66
-; GFX10-NEXT: v_cndmask_b32_e64 v97, v28, v81, s18
-; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; GFX10-NEXT: s_and_b32 vcc_lo, s7, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v51
-; GFX10-NEXT: v_cmp_eq_f32_e64 s11, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v67
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; GFX10-NEXT: v_cndmask_b32_e32 v11, v50, v36, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s8, s4
-; GFX10-NEXT: v_cmp_eq_u16_e64 s19, 0, v52
+; GFX10-NEXT: v_cmp_eq_f32_e64 s11, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v67
; GFX10-NEXT: v_cndmask_b32_e32 v28, v53, v37, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s12, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v69
; GFX10-NEXT: s_and_b32 vcc_lo, s9, s5
-; GFX10-NEXT: v_cmp_eq_u16_e64 s20, 0, v54
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v51
; GFX10-NEXT: v_cndmask_b32_e32 v32, v64, v49, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s12, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v69
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX10-NEXT: v_cmp_eq_u16_e64 s19, 0, v52
+; GFX10-NEXT: v_cmp_eq_u16_e64 s20, 0, v54
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v96
; GFX10-NEXT: v_cmp_eq_f32_e64 s13, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v70
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v96
; GFX10-NEXT: v_cmp_eq_f32_e64 s14, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v55
; GFX10-NEXT: v_cmp_eq_f32_e64 s15, 0, v34
@@ -10073,12 +10050,12 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v87, v87
; GFX10-NEXT: v_cndmask_b32_e32 v37, v51, v37, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s6, s5
-; GFX10-NEXT: v_perm_b32 v14, v14, v36, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e64 v51, v27, v96, s4
; GFX10-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v85
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v97
-; GFX10-NEXT: v_cndmask_b32_e64 v51, v27, v96, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v81
+; GFX10-NEXT: v_perm_b32 v14, v14, v36, 0x5040100
; GFX10-NEXT: s_and_b32 vcc_lo, s17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v27, v80, v85, vcc_lo
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v49
@@ -10095,44 +10072,44 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v10
; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v51, v51
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v25, s5
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52
; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v50
; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v26
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v25, s5
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v52
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v10
; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v54, v53
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
; GFX10-NEXT: v_cndmask_b32_e64 v26, v26, v10, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v55, v55
; GFX10-NEXT: v_cndmask_b32_e64 v51, v25, v9, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
; GFX10-NEXT: v_cndmask_b32_e32 v25, v49, v81, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v51
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_perm_b32 v12, v12, v25, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v10
; GFX10-NEXT: v_cndmask_b32_e32 v50, v50, v96, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v53, v52
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v22
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v49, v51, v9, s5
-; GFX10-NEXT: v_cmp_u_f32_e64 s5, v54, v54
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v24
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_cmp_u_f32_e64 s5, v54, v54
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v24, s5
; GFX10-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v49
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v24, s5
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v49
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v22
; GFX10-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v51, v51
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6
+; GFX10-NEXT: v_perm_b32 v12, v12, v25, 0x5040100
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52
@@ -10141,119 +10118,111 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v9
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v52, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v7
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v24, v24, v8, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v49, v9, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v24
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v22, s5
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v24
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v52, v26
-; GFX10-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6
; GFX10-NEXT: v_cndmask_b32_e64 v23, v23, v7, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v53, v53
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v6, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v26
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v49, v9, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v22
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v8
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v5
-; GFX10-NEXT: v_perm_b32 v8, v11, v8, 0x5040100
-; GFX10-NEXT: v_perm_b32 v11, v29, v50, 0x5040100
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v51, v49
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v21
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v6, s7
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v21, s7
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v22
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v21, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v5
+; GFX10-NEXT: v_perm_b32 v8, v11, v8, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v5
+; GFX10-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
; GFX10-NEXT: v_perm_b32 v7, v28, v7, 0x5040100
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v23, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v20, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v26, v26
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v19, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v49, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v3
; GFX10-NEXT: v_cndmask_b32_e64 v21, v21, v5, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v23, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX10-NEXT: v_cndmask_b32_e64 v20, v20, v4, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v23
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v19
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v23
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v26, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v19
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v20, v20, v4, s7
; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v51, v49
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s7
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v23, v23
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s7
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v19
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v23, v23
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v18, s6
-; GFX10-NEXT: v_perm_b32 v5, v15, v5, 0x5040100
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v2
-; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v2
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v21
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v2
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v22, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v17
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX10-NEXT: v_perm_b32 v6, v32, v6, 0x5040100
-; GFX10-NEXT: v_perm_b32 v15, v38, v37, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v17, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v17
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v21, v21
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v18
-; GFX10-NEXT: v_perm_b32 v4, v33, v4, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v16, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v4
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v22, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v1, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v23, v23
-; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v0, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v21, v21
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v2, s6
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v2, s6
-; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v22, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v18
+; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v22, v21
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v1, s6
; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v24, v23
-; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v49, v26
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v0, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v3
+; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v49, v26
; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v2, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v16
; GFX10-NEXT: s_and_b32 s5, s5, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v1
@@ -10261,17 +10230,25 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v21
; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v22
-; GFX10-NEXT: v_perm_b32 v3, v34, v3, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v2
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v19
; GFX10-NEXT: s_and_b32 s5, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v1, s5
; GFX10-NEXT: s_and_b32 s5, s7, s8
+; GFX10-NEXT: v_perm_b32 v3, v34, v3, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, v0, s5
; GFX10-NEXT: s_and_b32 s5, s9, s10
; GFX10-NEXT: v_perm_b32 v1, v39, v1, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s5
+; GFX10-NEXT: v_perm_b32 v4, v33, v4, 0x5040100
; GFX10-NEXT: v_perm_b32 v0, v48, v0, 0x5040100
+; GFX10-NEXT: v_perm_b32 v5, v15, v5, 0x5040100
+; GFX10-NEXT: v_perm_b32 v6, v32, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v11, v29, v50, 0x5040100
+; GFX10-NEXT: v_perm_b32 v15, v38, v37, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_maximumnum_v32bf16:
@@ -10898,7 +10875,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
@@ -10906,18 +10882,20 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v130, v144, v135, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo
@@ -10931,226 +10909,244 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v102, 16, v11
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v28 :: v_dual_and_b32 v97, 0xffff0000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v11, v27 :: v_dual_lshlrev_b32 v82, 16, v29
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s17, v49, v133
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s16, v37, v132
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s18, v53, v134
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v71, v80, s4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v99, v103, v112, s8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v54, v98
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s16, v37, v132
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v117, v117
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s18, v53, v134
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v65, v135
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v69, v144
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v71, v145
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v99, v103, v112, s8
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v117, v117
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v38, v147, v34, s13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v87
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v83, v146
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v54, v98
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v112
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v99
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v65, v135
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v86, v147
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v69, v144
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v71, v145
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v83, v146
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v86, v147
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v97, v54
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v113
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v101, v98
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v128
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v117
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v130
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v101, v98
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v103, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v48
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v103, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v115, v132
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v64
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v119, v49
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v68
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v131, v133
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v80
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v38, v38, v34, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v66, v53
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v39
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v84
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v82, v134
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v48
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v82
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v100
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s15, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v64
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s16, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v112
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v68
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s17, s1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v80
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v51, v52, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s18, s2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v84
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s19, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v68, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s20, s4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v100
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v67, v80, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s21, s5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v69, v84, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v69, v84 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s22, s6
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v70, v96, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s23, s7
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v71, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v118
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v83
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v38
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v128
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v113
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v34
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
@@ -11238,47 +11234,45 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v26
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v38, v32
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v25, s1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v38, v32
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v26, v10, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v50, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v31, v29
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v31, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v24, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v51, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8
@@ -11287,138 +11281,123 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v28, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v8, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v22, s1
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v28, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v23, v7, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v21, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v21, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v55, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v20, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v19, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v21, v21, v5, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v25, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s3
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v20
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v18, s2
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v17, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v16, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v22, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v22, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1
@@ -11426,20 +11405,22 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v17, v1, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v16, v0, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s5, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v49, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v18, v2, s1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v34, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v65, v2, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -12140,7 +12121,6 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
@@ -12149,20 +12129,22 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v130, v144, v135, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v13
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -12178,252 +12160,285 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v102, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v28 :: v_dual_and_b32 v97, 0xffff0000, v23
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
; GFX12-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s17, v49, v133
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s16, v37, v132
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s18, v53, v134
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v70, v71, v80, s4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v54, v98
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s16, v37, v132
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s18, v53, v134
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v65, v135
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v69, v144
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v71, v145
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v99, v103, v112, s8
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v117, v117
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v38, v147, v34, s13
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v87
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v83, v146
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v54, v98
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v112
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v99
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v65, v135
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v86, v147
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v69, v144
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v97, v54
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v113
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v71, v145
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v128
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v117
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v101, v98
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v83, v146
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v130
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v86, v147
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v97, v54
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v101, v98
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v103, v37
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v115, v132
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v119, v49
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v48
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v131, v133
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v64
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v68
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v38, v38, v34, s15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v66, v53
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v35
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v39
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v82, v134
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v80
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v53
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v48
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v82
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v84
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s15, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v64
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s16, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v68
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v39, v48, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s17, s1
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v100
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v80
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v51, v52, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s18, s2
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v84
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v64, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s19, s3
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v51, v65, v68 :: v_dual_lshlrev_b32 v50, 16, v15
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v68, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s20, s4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v100
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v67, v80 :: v_dual_lshlrev_b32 v101, 16, v54
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v67, v80, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s21, s5
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v112
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v69, v84, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v69, v84 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s22, s6
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v70, v96, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s23, s7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v112
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v71, v100, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v116
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v118
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v83
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v49
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v38
@@ -12536,52 +12551,53 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v26
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v38, v32
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v25, s1
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v31
-; GFX12-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v38, v32
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v26, v26, v10, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v50, v50
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v11
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v31, v29
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
-; GFX12-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v31, v29
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v24, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v24, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23
; GFX12-FAKE16-NEXT: v_perm_b32 v10, v51, v10, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX12-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
@@ -12592,156 +12608,150 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v28, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v8, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v22, s1
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v28, v26
-; GFX12-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v23, v23, v7, s1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v21, s3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX12-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5
+; GFX12-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v55, v7, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v20, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v19, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v21, v21, v5, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v25, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s3
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s3
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v20
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v18, s2
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v17, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
-; GFX12-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v16, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v22, v21
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v22, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v23
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v25
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1
@@ -12750,21 +12760,25 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v22
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v2
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v17, v1, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX12-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v16, v0, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s5, s6
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v49, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v18, v2, s1
+; GFX12-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v34, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v65, v2, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <32 x bfloat> @llvm.maximumnum.v32bf16(<32 x bfloat> %x, <32 x bfloat> %y)
@@ -13557,15 +13571,15 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, v0, v2, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
@@ -13591,9 +13605,9 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v9, v5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
@@ -14171,9 +14185,9 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v2
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v8, v13
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
@@ -14305,35 +14319,34 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
@@ -14483,40 +14496,40 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
index cc0fce9a5261b..243b3f368bf07 100644
--- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
@@ -764,11 +764,11 @@ define void @memcpy_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0)
; UNROLL3-NEXT: v_add_co_u32 v12, vcc_lo, v2, s4
; UNROLL3-NEXT: v_add_co_ci_u32_e64 v13, null, s5, v3, vcc_lo
; UNROLL3-NEXT: v_add_co_u32 v16, vcc_lo, v0, s4
-; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: s_clause 0x2
; UNROLL3-NEXT: flat_load_dwordx4 v[4:7], v[12:13]
; UNROLL3-NEXT: flat_load_dwordx4 v[8:11], v[12:13] offset:16
; UNROLL3-NEXT: flat_load_dwordx4 v[12:15], v[12:13] offset:32
+; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: v_add_co_ci_u32_e64 v17, null, s5, v1, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, 0
; UNROLL3-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
@@ -804,7 +804,6 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1)
; CHECK-NEXT: v_add_co_u32 v96, vcc_lo, v2, s4
; CHECK-NEXT: v_add_co_ci_u32_e64 v97, null, s5, v3, vcc_lo
; CHECK-NEXT: v_add_co_u32 v100, vcc_lo, v0, s4
-; CHECK-NEXT: s_add_u32 s4, s4, 0x100
; CHECK-NEXT: s_clause 0xf
; CHECK-NEXT: global_load_dwordx4 v[4:7], v[96:97], off offset:224
; CHECK-NEXT: global_load_dwordx4 v[8:11], v[96:97], off offset:240
@@ -822,6 +821,7 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1)
; CHECK-NEXT: global_load_dwordx4 v[80:83], v[96:97], off offset:48
; CHECK-NEXT: global_load_dwordx4 v[84:87], v[96:97], off
; CHECK-NEXT: global_load_dwordx4 v[96:99], v[96:97], off offset:16
+; CHECK-NEXT: s_add_u32 s4, s4, 0x100
; CHECK-NEXT: v_add_co_ci_u32_e64 v101, null, s5, v1, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, 0
; CHECK-NEXT: s_waitcnt vmcnt(15)
@@ -1518,11 +1518,11 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1)
; UNROLL3-NEXT: v_add_co_u32 v12, vcc_lo, v2, s4
; UNROLL3-NEXT: v_add_co_ci_u32_e64 v13, null, s5, v3, vcc_lo
; UNROLL3-NEXT: v_add_co_u32 v16, vcc_lo, v0, s4
-; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: s_clause 0x2
; UNROLL3-NEXT: global_load_dwordx4 v[4:7], v[12:13], off
; UNROLL3-NEXT: global_load_dwordx4 v[8:11], v[12:13], off offset:16
; UNROLL3-NEXT: global_load_dwordx4 v[12:15], v[12:13], off offset:32
+; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: v_add_co_ci_u32_e64 v17, null, s5, v1, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, 0
; UNROLL3-NEXT: s_waitcnt vmcnt(2)
@@ -1557,7 +1557,6 @@ define void @memcpy_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4)
; CHECK-NEXT: v_add_co_u32 v96, vcc_lo, v2, s4
; CHECK-NEXT: v_add_co_ci_u32_e64 v97, null, s5, v3, vcc_lo
; CHECK-NEXT: v_add_co_u32 v100, vcc_lo, v0, s4
-; CHECK-NEXT: s_add_u32 s4, s4, 0x100
; CHECK-NEXT: s_clause 0xf
; CHECK-NEXT: global_load_dwordx4 v[4:7], v[96:97], off offset:240
; CHECK-NEXT: global_load_dwordx4 v[8:11], v[96:97], off offset:224
@@ -1575,6 +1574,7 @@ define void @memcpy_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4)
; CHECK-NEXT: global_load_dwordx4 v[80:83], v[96:97], off offset:32
; CHECK-NEXT: global_load_dwordx4 v[84:87], v[96:97], off offset:16
; CHECK-NEXT: global_load_dwordx4 v[96:99], v[96:97], off
+; CHECK-NEXT: s_add_u32 s4, s4, 0x100
; CHECK-NEXT: v_add_co_ci_u32_e64 v101, null, s5, v1, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, 0
; CHECK-NEXT: v_add_co_u32 v102, vcc_lo, v100, 48
@@ -1627,7 +1627,6 @@ define void @memcpy_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4)
; ALIGNED-NEXT: v_add_co_u32 v8, vcc_lo, v2, s4
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v9, null, s5, v3, vcc_lo
; ALIGNED-NEXT: v_add_co_u32 v84, vcc_lo, v0, s4
-; ALIGNED-NEXT: v_add_co_ci_u32_e64 v85, null, s5, v1, vcc_lo
; ALIGNED-NEXT: s_clause 0xf
; ALIGNED-NEXT: global_load_dwordx4 v[98:101], v[8:9], off offset:240
; ALIGNED-NEXT: global_load_dwordx4 v[112:115], v[8:9], off offset:224
@@ -1645,11 +1644,12 @@ define void @memcpy_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4)
; ALIGNED-NEXT: global_load_dwordx4 v[12:15], v[8:9], off offset:32
; ALIGNED-NEXT: global_load_dwordx4 v[4:7], v[8:9], off
; ALIGNED-NEXT: global_load_dwordx4 v[8:11], v[8:9], off offset:16
+; ALIGNED-NEXT: v_add_co_ci_u32_e64 v85, null, s5, v1, vcc_lo
; ALIGNED-NEXT: v_add_co_u32 v96, vcc_lo, v84, 6
+; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v97, null, 0, v85, vcc_lo
; ALIGNED-NEXT: v_add_co_u32 v86, vcc_lo, v84, 3
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v87, null, 0, v85, vcc_lo
-; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100
; ALIGNED-NEXT: s_addc_u32 s5, s5, 0
; ALIGNED-NEXT: s_waitcnt vmcnt(15)
; ALIGNED-NEXT: buffer_store_dword v100, off, s[0:3], s32 offset:168
@@ -2130,11 +2130,11 @@ define void @memcpy_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4)
; UNROLL3-NEXT: v_add_co_u32 v12, vcc_lo, v2, s4
; UNROLL3-NEXT: v_add_co_ci_u32_e64 v13, null, s5, v3, vcc_lo
; UNROLL3-NEXT: v_add_co_u32 v16, vcc_lo, v0, s4
-; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: s_clause 0x2
; UNROLL3-NEXT: global_load_dwordx4 v[4:7], v[12:13], off offset:16
; UNROLL3-NEXT: global_load_dwordx4 v[8:11], v[12:13], off
; UNROLL3-NEXT: global_load_dwordx4 v[12:15], v[12:13], off offset:32
+; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: v_add_co_ci_u32_e64 v17, null, s5, v1, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, 0
; UNROLL3-NEXT: s_waitcnt vmcnt(2)
@@ -3684,9 +3684,9 @@ define void @memcpy_p0_p5_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(5)
; CHECK-NEXT: s_add_u32 s4, s4, 0x100
; CHECK-NEXT: v_add_co_ci_u32_e64 v101, null, s5, v1, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_add_co_u32 v102, vcc_lo, v100, 48
-; CHECK-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5]
; CHECK-NEXT: v_add_nc_u32_e32 v2, 0x100, v2
+; CHECK-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5]
+; CHECK-NEXT: v_add_co_u32 v102, vcc_lo, v100, 48
; CHECK-NEXT: v_add_co_ci_u32_e64 v103, null, 0, v101, vcc_lo
; CHECK-NEXT: s_waitcnt vmcnt(43)
; CHECK-NEXT: flat_store_dwordx4 v[102:103], v[23:26] offset:192
@@ -5405,8 +5405,8 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; CHECK-NEXT: v_add_co_u32 v100, vcc_lo, v0, 48
; CHECK-NEXT: v_add_co_ci_u32_e64 v101, null, 0, v1, vcc_lo
; CHECK-NEXT: v_add_co_u32 v2, vcc_lo, 0x100, v2
-; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 0xffffff00
+; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, -1
; CHECK-NEXT: s_waitcnt vmcnt(15) lgkmcnt(15)
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[4:7] offset:128
@@ -5478,8 +5478,8 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; CHECK-NEXT: v_add_co_u32 v100, vcc_lo, v0, 48
; CHECK-NEXT: v_add_co_ci_u32_e64 v101, null, 0, v1, vcc_lo
; CHECK-NEXT: v_add_co_u32 v2, vcc_lo, 0xffffff00, v2
-; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 0x100
+; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, 0
; CHECK-NEXT: s_waitcnt vmcnt(15) lgkmcnt(15)
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[4:7] offset:128
@@ -5861,14 +5861,14 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: v_lshrrev_b32_e32 v97, 8, v97
; ALIGNED-NEXT: v_lshrrev_b32_e32 v103, 24, v96
; ALIGNED-NEXT: v_lshrrev_b32_e32 v96, 8, v96
-; ALIGNED-NEXT: v_lshrrev_b32_e32 v115, 24, v32
-; ALIGNED-NEXT: v_lshrrev_b32_e32 v32, 8, v32
; ALIGNED-NEXT: v_lshrrev_b32_e32 v112, 24, v35
; ALIGNED-NEXT: v_lshrrev_b32_e32 v35, 8, v35
; ALIGNED-NEXT: v_lshrrev_b32_e32 v113, 24, v34
; ALIGNED-NEXT: v_lshrrev_b32_e32 v34, 8, v34
; ALIGNED-NEXT: v_lshrrev_b32_e32 v114, 24, v33
; ALIGNED-NEXT: v_lshrrev_b32_e32 v33, 8, v33
+; ALIGNED-NEXT: v_lshrrev_b32_e32 v115, 24, v32
+; ALIGNED-NEXT: v_lshrrev_b32_e32 v32, 8, v32
; ALIGNED-NEXT: s_waitcnt vmcnt(3)
; ALIGNED-NEXT: flat_store_byte_d16_hi v[22:23], v19 offset:120
; ALIGNED-NEXT: flat_store_byte v[20:21], v19 offset:121
@@ -5991,9 +5991,7 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: flat_store_byte v[20:21], v49 offset:226
; ALIGNED-NEXT: v_lshrrev_b32_e32 v49, 24, v10
; ALIGNED-NEXT: v_lshrrev_b32_e32 v54, 8, v54
-; ALIGNED-NEXT: flat_store_byte v[0:1], v32 offset:1
; ALIGNED-NEXT: v_lshrrev_b32_e32 v10, 8, v10
-; ALIGNED-NEXT: v_add_co_u32 v0, vcc_lo, 0x100, v0
; ALIGNED-NEXT: flat_store_byte v[20:21], v101 offset:24
; ALIGNED-NEXT: v_lshrrev_b32_e32 v101, 24, v53
; ALIGNED-NEXT: flat_store_byte v[20:21], v24 offset:224
@@ -6038,6 +6036,7 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: flat_store_byte v[20:21], v115
; ALIGNED-NEXT: v_lshrrev_b32_e32 v115, 24, v81
; ALIGNED-NEXT: v_lshrrev_b32_e32 v81, 8, v81
+; ALIGNED-NEXT: flat_store_byte v[0:1], v32 offset:1
; ALIGNED-NEXT: v_lshrrev_b32_e32 v32, 24, v80
; ALIGNED-NEXT: v_lshrrev_b32_e32 v80, 8, v80
; ALIGNED-NEXT: flat_store_byte v[20:21], v96 offset:252
@@ -6133,6 +6132,7 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: flat_store_byte v[20:21], v13 offset:98
; ALIGNED-NEXT: flat_store_byte v[20:21], v50 offset:96
; ALIGNED-NEXT: flat_store_byte v[20:21], v12 offset:94
+; ALIGNED-NEXT: v_add_co_u32 v0, vcc_lo, 0x100, v0
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; ALIGNED-NEXT: flat_store_byte v[20:21], v99 offset:92
; ALIGNED-NEXT: flat_store_byte v[20:21], v11 offset:90
@@ -6500,14 +6500,14 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: v_lshrrev_b32_e32 v97, 8, v97
; ALIGNED-NEXT: v_lshrrev_b32_e32 v103, 24, v96
; ALIGNED-NEXT: v_lshrrev_b32_e32 v96, 8, v96
-; ALIGNED-NEXT: v_lshrrev_b32_e32 v115, 24, v70
-; ALIGNED-NEXT: v_lshrrev_b32_e32 v70, 8, v70
; ALIGNED-NEXT: v_lshrrev_b32_e32 v112, 24, v84
; ALIGNED-NEXT: v_lshrrev_b32_e32 v84, 8, v84
; ALIGNED-NEXT: v_lshrrev_b32_e32 v113, 24, v83
; ALIGNED-NEXT: v_lshrrev_b32_e32 v83, 8, v83
; ALIGNED-NEXT: v_lshrrev_b32_e32 v114, 24, v82
; ALIGNED-NEXT: v_lshrrev_b32_e32 v82, 8, v82
+; ALIGNED-NEXT: v_lshrrev_b32_e32 v115, 24, v70
+; ALIGNED-NEXT: v_lshrrev_b32_e32 v70, 8, v70
; ALIGNED-NEXT: s_waitcnt vmcnt(3)
; ALIGNED-NEXT: flat_store_byte_d16_hi v[22:23], v15 offset:120
; ALIGNED-NEXT: flat_store_byte v[20:21], v15 offset:121
@@ -6630,9 +6630,7 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: flat_store_byte v[20:21], v67 offset:226
; ALIGNED-NEXT: v_lshrrev_b32_e32 v67, 24, v6
; ALIGNED-NEXT: v_lshrrev_b32_e32 v68, 8, v68
-; ALIGNED-NEXT: flat_store_byte v[16:17], v70 offset:1
; ALIGNED-NEXT: v_lshrrev_b32_e32 v6, 8, v6
-; ALIGNED-NEXT: v_add_co_u32 v16, vcc_lo, 0xffffff00, v16
; ALIGNED-NEXT: flat_store_byte v[20:21], v101 offset:24
; ALIGNED-NEXT: v_lshrrev_b32_e32 v101, 24, v53
; ALIGNED-NEXT: flat_store_byte v[20:21], v30 offset:224
@@ -6677,6 +6675,7 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: flat_store_byte v[20:21], v115
; ALIGNED-NEXT: v_lshrrev_b32_e32 v115, 24, v28
; ALIGNED-NEXT: v_lshrrev_b32_e32 v28, 8, v28
+; ALIGNED-NEXT: flat_store_byte v[16:17], v70 offset:1
; ALIGNED-NEXT: v_lshrrev_b32_e32 v70, 24, v25
; ALIGNED-NEXT: v_lshrrev_b32_e32 v25, 8, v25
; ALIGNED-NEXT: flat_store_byte v[20:21], v96 offset:252
@@ -6772,6 +6771,7 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; ALIGNED-NEXT: flat_store_byte v[20:21], v9 offset:98
; ALIGNED-NEXT: flat_store_byte v[20:21], v80 offset:96
; ALIGNED-NEXT: flat_store_byte v[20:21], v8 offset:94
+; ALIGNED-NEXT: v_add_co_u32 v16, vcc_lo, 0xffffff00, v16
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v17, null, -1, v17, vcc_lo
; ALIGNED-NEXT: flat_store_byte v[20:21], v99 offset:92
; ALIGNED-NEXT: flat_store_byte v[20:21], v7 offset:90
@@ -6848,8 +6848,8 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; UNROLL3-NEXT: flat_load_dwordx4 v[12:15], v[4:5] offset:16
; UNROLL3-NEXT: flat_load_dwordx4 v[16:19], v[4:5] offset:32
; UNROLL3-NEXT: v_add_co_u32 v4, vcc_lo, v4, 48
-; UNROLL3-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; UNROLL3-NEXT: s_add_u32 s4, s4, 0xffffffd0
+; UNROLL3-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, -1
; UNROLL3-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
; UNROLL3-NEXT: flat_store_dwordx4 v[6:7], v[8:11]
@@ -6894,8 +6894,8 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; UNROLL3-NEXT: flat_load_dwordx4 v[10:13], v[2:3] offset:16
; UNROLL3-NEXT: flat_load_dwordx4 v[14:17], v[2:3] offset:32
; UNROLL3-NEXT: v_add_co_u32 v2, vcc_lo, 0xffffffd0, v2
-; UNROLL3-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo
; UNROLL3-NEXT: s_add_u32 s4, s4, 48
+; UNROLL3-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, 0
; UNROLL3-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
; UNROLL3-NEXT: flat_store_dwordx4 v[4:5], v[6:9]
@@ -6946,8 +6946,8 @@ define void @memmove_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1
; CHECK-NEXT: global_load_dwordx4 v[84:87], v[2:3], off
; CHECK-NEXT: global_load_dwordx4 v[96:99], v[2:3], off offset:16
; CHECK-NEXT: v_add_co_u32 v2, vcc_lo, 0x100, v2
-; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 0xffffff00
+; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, -1
; CHECK-NEXT: s_waitcnt vmcnt(15)
; CHECK-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:224
@@ -7097,8 +7097,8 @@ define void @memmove_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1
; ALIGNED-NEXT: global_load_dwordx4 v[28:31], v[2:3], off offset:192
; ALIGNED-NEXT: global_load_dwordx4 v[24:27], v[2:3], off offset:208
; ALIGNED-NEXT: v_add_co_u32 v2, vcc_lo, 0x100, v2
-; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; ALIGNED-NEXT: s_add_u32 s4, s4, 0xffffff00
+; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; ALIGNED-NEXT: s_addc_u32 s5, s5, -1
; ALIGNED-NEXT: s_waitcnt vmcnt(15)
; ALIGNED-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80
@@ -8364,8 +8364,8 @@ define void @memmove_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1
; UNROLL3-NEXT: global_load_dwordx4 v[12:15], v[4:5], off offset:16
; UNROLL3-NEXT: global_load_dwordx4 v[16:19], v[4:5], off offset:32
; UNROLL3-NEXT: v_add_co_u32 v4, vcc_lo, v4, 48
-; UNROLL3-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; UNROLL3-NEXT: s_add_u32 s4, s4, 0xffffffd0
+; UNROLL3-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, -1
; UNROLL3-NEXT: s_waitcnt vmcnt(2)
; UNROLL3-NEXT: global_store_dwordx4 v[6:7], v[8:11], off
@@ -8463,8 +8463,8 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; CHECK-NEXT: v_add_co_u32 v100, vcc_lo, v0, 48
; CHECK-NEXT: v_add_co_ci_u32_e64 v101, null, 0, v1, vcc_lo
; CHECK-NEXT: v_add_co_u32 v2, vcc_lo, 0x100, v2
-; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 0xffffff00
+; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; CHECK-NEXT: s_addc_u32 s5, s5, -1
; CHECK-NEXT: s_waitcnt vmcnt(15)
; CHECK-NEXT: flat_store_dwordx4 v[100:101], v[4:7] offset:192
@@ -8609,8 +8609,8 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; ALIGNED-NEXT: v_add_co_u32 v98, vcc_lo, v0, 3
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v99, null, 0, v1, vcc_lo
; ALIGNED-NEXT: v_add_co_u32 v2, vcc_lo, 0x100, v2
-; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; ALIGNED-NEXT: s_add_u32 s4, s4, 0xffffff00
+; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; ALIGNED-NEXT: s_addc_u32 s5, s5, -1
; ALIGNED-NEXT: s_waitcnt vmcnt(15)
; ALIGNED-NEXT: buffer_store_dword v114, off, s[0:3], s32 offset:168
@@ -8956,6 +8956,7 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; ALIGNED-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4
; ALIGNED-NEXT: buffer_store_dword v24, off, s[0:3], s32
; ALIGNED-NEXT: flat_store_byte v[98:99], v80 offset:88
+; ALIGNED-NEXT: v_lshrrev_b32_e32 v80, 24, v5
; ALIGNED-NEXT: flat_store_byte v[98:99], v81 offset:86
; ALIGNED-NEXT: flat_store_byte v[98:99], v82 offset:92
; ALIGNED-NEXT: flat_store_byte v[98:99], v83 offset:90
@@ -9069,7 +9070,6 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; ALIGNED-NEXT: flat_store_byte v[0:1], v83 offset:1
; ALIGNED-NEXT: flat_store_byte v[0:1], v4
; ALIGNED-NEXT: v_add_co_u32 v0, vcc_lo, 0x100, v0
-; ALIGNED-NEXT: v_lshrrev_b32_e32 v80, 24, v5
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; ALIGNED-NEXT: v_lshrrev_b32_e32 v81, 8, v5
; ALIGNED-NEXT: s_cmp_lg_u64 s[4:5], 0
@@ -9464,6 +9464,7 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; ALIGNED-NEXT: flat_store_byte v[98:99], v25 offset:81
; ALIGNED-NEXT: flat_store_byte_d16_hi v[96:97], v24 offset:76
; ALIGNED-NEXT: flat_store_byte v[98:99], v24 offset:77
+; ALIGNED-NEXT: v_lshrrev_b32_e32 v24, 24, v5
; ALIGNED-NEXT: v_lshrrev_b32_e32 v27, 8, v4
; ALIGNED-NEXT: flat_store_byte v[98:99], v80 offset:88
; ALIGNED-NEXT: flat_store_byte v[98:99], v81 offset:86
@@ -9570,7 +9571,6 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; ALIGNED-NEXT: flat_store_byte v[0:1], v27 offset:1
; ALIGNED-NEXT: flat_store_byte v[0:1], v4
; ALIGNED-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffff00, v0
-; ALIGNED-NEXT: v_lshrrev_b32_e32 v24, 24, v5
; ALIGNED-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; ALIGNED-NEXT: v_lshrrev_b32_e32 v25, 8, v5
; ALIGNED-NEXT: s_cmp_eq_u64 s[4:5], 0
@@ -9606,8 +9606,8 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; UNROLL3-NEXT: global_load_dwordx4 v[12:15], v[4:5], off
; UNROLL3-NEXT: global_load_dwordx4 v[16:19], v[4:5], off offset:32
; UNROLL3-NEXT: v_add_co_u32 v4, vcc_lo, v4, 48
-; UNROLL3-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; UNROLL3-NEXT: s_add_u32 s4, s4, 0xffffffd0
+; UNROLL3-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; UNROLL3-NEXT: s_addc_u32 s5, s5, -1
; UNROLL3-NEXT: s_waitcnt vmcnt(2)
; UNROLL3-NEXT: flat_store_dwordx4 v[6:7], v[8:11] offset:16
@@ -15995,8 +15995,8 @@ define void @memset_p0_sz2048(ptr addrspace(0) %dst) {
; ALIGNED-NEXT: .LBB10_1: ; %static-memset-expansion-main-body
; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1
; ALIGNED-NEXT: v_add_co_u32 v2, vcc_lo, v0, s4
-; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, s5, v1, vcc_lo
; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100
+; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, s5, v1, vcc_lo
; ALIGNED-NEXT: s_addc_u32 s5, s5, 0
; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:204
; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:200
diff --git a/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll b/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
index d95965caa81ab..3dd98279b9853 100644
--- a/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
@@ -1077,8 +1077,8 @@ define void @memmove_p1_p3(ptr addrspace(1) align 1 %dst, ptr addrspace(3) align
; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s7, 0
-; CHECK-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; CHECK-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; CHECK-NEXT: .LBB7_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1291,8 +1291,8 @@ define void @memmove_p1_p5(ptr addrspace(1) align 1 %dst, ptr addrspace(5) align
; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s7, 0
-; CHECK-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; CHECK-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; CHECK-NEXT: .LBB9_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1482,8 +1482,8 @@ define void @memmove_p3_p1(ptr addrspace(3) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v11, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 16
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: global_load_dwordx4 v[10:13], v[10:11], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: s_or_b32 s7, vcc_lo, s7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ds_write_b128 v9, v[10:13]
@@ -1499,8 +1499,8 @@ define void @memmove_p3_p1(ptr addrspace(3) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s7, 0
-; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_co_ci_u32_e64 v2, null, v2, v4, vcc_lo
; CHECK-NEXT: .LBB11_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1508,8 +1508,8 @@ define void @memmove_p3_p1(ptr addrspace(3) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v4, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 1
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: global_load_ubyte v3, v[3:4], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: s_or_b32 s7, vcc_lo, s7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ds_write_b8 v0, v3
@@ -1626,8 +1626,8 @@ define void @memmove_p3_p3(ptr addrspace(3) align 1 %dst, ptr addrspace(3) align
; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: v_add_nc_u32_e32 v4, -16, v5
; CHECK-NEXT: v_add_nc_u32_e32 v2, v0, v4
-; CHECK-NEXT: v_sub_co_u32 v0, vcc_lo, 0, v5
; CHECK-NEXT: v_add_nc_u32_e32 v4, v1, v4
+; CHECK-NEXT: v_sub_co_u32 v0, vcc_lo, 0, v5
; CHECK-NEXT: v_sub_co_ci_u32_e64 v1, null, 0, v3, vcc_lo
; CHECK-NEXT: .LBB12_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1673,8 +1673,8 @@ define void @memmove_p3_p4(ptr addrspace(3) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v11, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 16
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: global_load_dwordx4 v[10:13], v[10:11], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: s_or_b32 s7, vcc_lo, s7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ds_write_b128 v9, v[10:13]
@@ -1690,8 +1690,8 @@ define void @memmove_p3_p4(ptr addrspace(3) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s7, 0
-; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_co_ci_u32_e64 v2, null, v2, v4, vcc_lo
; CHECK-NEXT: .LBB13_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1699,8 +1699,8 @@ define void @memmove_p3_p4(ptr addrspace(3) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v4, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 1
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: global_load_ubyte v3, v[3:4], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: s_or_b32 s7, vcc_lo, s7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ds_write_b8 v0, v3
@@ -1788,17 +1788,17 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-LABEL: memmove_p5_p0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_and_b32_e32 v5, 15, v3
-; CHECK-NEXT: v_mov_b32_e32 v6, 0
+; CHECK-NEXT: v_and_b32_e32 v7, 15, v3
+; CHECK-NEXT: v_mov_b32_e32 v8, 0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, -1, v0
; CHECK-NEXT: s_mov_b64 s[4:5], src_private_base
-; CHECK-NEXT: v_and_b32_e32 v7, -16, v3
-; CHECK-NEXT: v_mov_b32_e32 v8, v4
-; CHECK-NEXT: v_cmp_ne_u64_e64 s4, 0, v[5:6]
+; CHECK-NEXT: v_and_b32_e32 v5, -16, v3
+; CHECK-NEXT: v_mov_b32_e32 v6, v4
+; CHECK-NEXT: v_cmp_ne_u64_e64 s4, 0, v[7:8]
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, s5, vcc_lo
; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v0, vcc_lo
; CHECK-NEXT: s_mov_b32 s6, exec_lo
-; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[7:8]
+; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[5:6]
; CHECK-NEXT: v_cmpx_ge_u64_e64 v[1:2], v[9:10]
; CHECK-NEXT: s_xor_b32 s7, exec_lo, s6
; CHECK-NEXT: s_cbranch_execnz .LBB15_3
@@ -1813,9 +1813,9 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: s_cbranch_execz .LBB15_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v10, v2
-; CHECK-NEXT: v_mov_b32_e32 v12, v8
+; CHECK-NEXT: v_mov_b32_e32 v12, v6
; CHECK-NEXT: v_mov_b32_e32 v9, v1
-; CHECK-NEXT: v_mov_b32_e32 v11, v7
+; CHECK-NEXT: v_mov_b32_e32 v11, v5
; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: s_mov_b32 s8, 0
; CHECK-NEXT: .p2align 6
@@ -1844,17 +1844,17 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: v_add_nc_u32_e32 v3, v0, v3
-; CHECK-NEXT: v_add_co_u32 v0, s5, v1, v7
-; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, v2, v8, s5
+; CHECK-NEXT: v_add_co_u32 v0, s5, v1, v5
+; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, v2, v6, s5
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB15_8: ; %memmove_fwd_residual_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flat_load_ubyte v2, v[0:1]
-; CHECK-NEXT: v_add_co_u32 v5, s5, v5, -1
-; CHECK-NEXT: v_add_co_ci_u32_e64 v6, null, -1, v6, s5
+; CHECK-NEXT: v_add_co_u32 v7, s5, v7, -1
+; CHECK-NEXT: v_add_co_ci_u32_e64 v8, null, -1, v8, s5
; CHECK-NEXT: v_add_co_u32 v0, s5, v0, 1
; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, s5
-; CHECK-NEXT: v_cmp_eq_u64_e64 s6, 0, v[5:6]
+; CHECK-NEXT: v_cmp_eq_u64_e64 s6, 0, v[7:8]
; CHECK-NEXT: s_or_b32 s9, s6, s9
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen
@@ -1863,11 +1863,11 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: s_cbranch_execnz .LBB15_8
; CHECK-NEXT: .LBB15_9: ; %Flow32
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s8
-; CHECK-NEXT: ; implicit-def: $vgpr7_vgpr8
+; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3_vgpr4
; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: ; implicit-def: $vgpr1_vgpr2
-; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
+; CHECK-NEXT: ; implicit-def: $vgpr7_vgpr8
; CHECK-NEXT: s_andn2_saveexec_b32 s6, s7
; CHECK-NEXT: s_cbranch_execz .LBB15_2
; CHECK-NEXT: .LBB15_10: ; %memmove_copy_backwards
@@ -1884,11 +1884,11 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: .LBB15_12: ; %memmove_bwd_residual_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flat_load_ubyte v11, v[9:10]
-; CHECK-NEXT: v_add_co_u32 v5, s4, v5, -1
-; CHECK-NEXT: v_add_co_ci_u32_e64 v6, null, -1, v6, s4
+; CHECK-NEXT: v_add_co_u32 v7, s4, v7, -1
+; CHECK-NEXT: v_add_co_ci_u32_e64 v8, null, -1, v8, s4
; CHECK-NEXT: v_add_co_u32 v9, s4, v9, -1
; CHECK-NEXT: v_add_co_ci_u32_e64 v10, null, -1, v10, s4
-; CHECK-NEXT: v_cmp_eq_u64_e64 s5, 0, v[5:6]
+; CHECK-NEXT: v_cmp_eq_u64_e64 s5, 0, v[7:8]
; CHECK-NEXT: s_or_b32 s8, s5, s8
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: buffer_store_byte v11, v4, s[0:3], 0 offen
@@ -1908,17 +1908,17 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB15_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_add_co_u32 v3, vcc_lo, v1, v7
-; CHECK-NEXT: v_add_co_ci_u32_e64 v4, null, v2, v8, vcc_lo
-; CHECK-NEXT: v_add_co_u32 v7, vcc_lo, v7, -16
-; CHECK-NEXT: v_add_co_ci_u32_e64 v8, null, -1, v8, vcc_lo
-; CHECK-NEXT: flat_load_dwordx4 v[3:6], v[3:4]
+; CHECK-NEXT: v_add_co_u32 v3, vcc_lo, v1, v5
+; CHECK-NEXT: v_add_co_ci_u32_e64 v4, null, v2, v6, vcc_lo
+; CHECK-NEXT: v_add_co_u32 v5, vcc_lo, v5, -16
+; CHECK-NEXT: v_add_co_ci_u32_e64 v6, null, -1, v6, vcc_lo
+; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[3:4]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:12
-; CHECK-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:8
-; CHECK-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen offset:4
-; CHECK-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; CHECK-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
+; CHECK-NEXT: buffer_store_dword v10, v0, s[0:3], 0 offen offset:12
+; CHECK-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:8
+; CHECK-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:4
+; CHECK-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen
+; CHECK-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
; CHECK-NEXT: v_add_nc_u32_e32 v0, -16, v0
; CHECK-NEXT: s_or_b32 s5, vcc_lo, s5
; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
@@ -1954,8 +1954,8 @@ define void @memmove_p5_p1(ptr addrspace(5) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v11, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 16
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: global_load_dwordx4 v[10:13], v[10:11], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_store_dword v13, v9, s[0:3], 0 offen offset:12
; CHECK-NEXT: buffer_store_dword v12, v9, s[0:3], 0 offen offset:8
@@ -1974,8 +1974,8 @@ define void @memmove_p5_p1(ptr addrspace(5) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s7, 0
-; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_co_ci_u32_e64 v2, null, v2, v4, vcc_lo
; CHECK-NEXT: .LBB16_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1983,8 +1983,8 @@ define void @memmove_p5_p1(ptr addrspace(5) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v4, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 1
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: global_load_ubyte v3, v[3:4], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: s_or_b32 s7, vcc_lo, s7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_store_byte v3, v0, s[0:3], 0 offen
@@ -2086,8 +2086,8 @@ define void @memmove_p5_p4(ptr addrspace(5) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v11, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 16
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: global_load_dwordx4 v[10:13], v[10:11], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[7:8]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_store_dword v13, v9, s[0:3], 0 offen offset:12
; CHECK-NEXT: buffer_store_dword v12, v9, s[0:3], 0 offen offset:8
@@ -2106,8 +2106,8 @@ define void @memmove_p5_p4(ptr addrspace(5) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: v_and_b32_e32 v3, -16, v3
; CHECK-NEXT: s_mov_b32 s7, 0
-; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; CHECK-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; CHECK-NEXT: v_add_co_ci_u32_e64 v2, null, v2, v4, vcc_lo
; CHECK-NEXT: .LBB18_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2115,8 +2115,8 @@ define void @memmove_p5_p4(ptr addrspace(5) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: v_add_co_ci_u32_e64 v4, null, s5, v2, vcc_lo
; CHECK-NEXT: s_add_u32 s4, s4, 1
; CHECK-NEXT: s_addc_u32 s5, s5, 0
-; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: global_load_ubyte v3, v[3:4], off
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
; CHECK-NEXT: s_or_b32 s7, vcc_lo, s7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_store_byte v3, v0, s[0:3], 0 offen
@@ -2242,8 +2242,8 @@ define void @memmove_p5_p5(ptr addrspace(5) align 1 %dst, ptr addrspace(5) align
; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: v_add_nc_u32_e32 v4, -16, v5
; CHECK-NEXT: v_add_nc_u32_e32 v2, v0, v4
-; CHECK-NEXT: v_sub_co_u32 v0, vcc_lo, 0, v5
; CHECK-NEXT: v_add_nc_u32_e32 v4, v1, v4
+; CHECK-NEXT: v_sub_co_u32 v0, vcc_lo, 0, v5
; CHECK-NEXT: v_sub_co_ci_u32_e64 v1, null, 0, v3, vcc_lo
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB19_15: ; %memmove_bwd_main_loop
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index 6ebb6aaa4520f..d6714c7f2bc22 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -3161,9 +3161,9 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_cmp_lt_u32_e32 vcc, v4, v5
; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; CI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CI-NEXT: flat_store_short v[0:1], v4
-; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CI-NEXT: flat_store_byte v[2:3], v0
+; CI-NEXT: flat_store_byte v[2:3], v5
; CI-NEXT: s_endpgm
;
; VI-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3189,9 +3189,9 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; VI-NEXT: v_and_b32_e32 v7, 0xffff, v5
; VI-NEXT: v_cmp_lt_u32_e32 vcc, v7, v6
; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: flat_store_short v[0:1], v4
-; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-NEXT: flat_store_byte v[2:3], v0
+; VI-NEXT: flat_store_byte v[2:3], v5
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3204,9 +3204,9 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:WORD_0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9-NEXT: global_store_byte v0, v1, s[2:3]
+; GFX9-NEXT: global_store_byte v0, v2, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: v_test_umin_ult_i16_multi_use:
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index ba0617dac5d0d..a9cd1754a9e3a 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -868,13 +868,13 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX10-LABEL: v_minimumnum_v2bf16_nnan:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v5, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v5, v4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, v0, s4
; GFX10-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
@@ -1222,15 +1222,15 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, v0, v2, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
@@ -1256,9 +1256,9 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v9, v5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
@@ -2187,9 +2187,9 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v2
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v8, v13
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
@@ -2321,35 +2321,34 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
@@ -2499,40 +2498,40 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
@@ -2740,23 +2739,23 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v9, v8
; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
-; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v12, v11
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v7, v6
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v9, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v12, v11
; GFX10-NEXT: v_cndmask_b32_e64 v8, v14, v13, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
+; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v7, v6
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v13
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
@@ -2831,48 +2830,47 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v11
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v6, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2947,48 +2945,50 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v11
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v14, v13, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v6, 0xffff0000, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)
@@ -3412,48 +3412,48 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v11, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v12, s5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v11, v11
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v8
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v11, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s4
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v0
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v9, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v2
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v9, v9
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v10, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v9, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v11, v11
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v0, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s4
-; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v10, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v10, v9
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s4
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v13, v11
-; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v15, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v0, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v12
+; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v15, v14
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
@@ -3620,9 +3620,9 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v11, 16, v8
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
@@ -3635,61 +3635,58 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
@@ -3878,10 +3875,10 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v15, 16, v9
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v11, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
@@ -3892,67 +3889,66 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v14
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v12, v10, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v11
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v7
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v14
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v14
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
@@ -4517,33 +4513,33 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v14, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v12, v12
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v12, v14, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v17, v17
; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v9
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v12
; GFX10-NEXT: v_cndmask_b32_e64 v14, v15, v13, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v13
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v16, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v3
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v9, s4
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v18, v19
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v13, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v3, s4
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
@@ -4808,40 +4804,40 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v12, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v9, s0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v18, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
@@ -4854,21 +4850,22 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v17, v16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
@@ -5146,50 +5143,50 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v12, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
; GFX12-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v13
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v17
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v9, s0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v18, v19
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v13, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
@@ -5203,11 +5200,13 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v17, v16
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -5215,13 +5214,12 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
@@ -6267,45 +6265,45 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v21, v22
; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX10-NEXT: v_cmp_u_f32_e64 s5, v20, v20
; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v18, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v16
+; GFX10-NEXT: v_cmp_u_f32_e64 s5, v20, v20
; GFX10-NEXT: v_cndmask_b32_e64 v20, v22, v21, s5
-; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v12
; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v19
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v24, v24
; GFX10-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
-; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX10-NEXT: v_cndmask_b32_e64 v17, v21, v20, s4
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v17
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v21, v21
-; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v24, v25
; GFX10-NEXT: v_cndmask_b32_e64 v21, v23, v22, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v18
-; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v24, v25
; GFX10-NEXT: v_cndmask_b32_e64 v23, v17, v20, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v21, s5
; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v21, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v22
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v17, v17
+; GFX10-NEXT: v_cndmask_b32_e64 v25, v25, v24, s5
; GFX10-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v22
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v25, v24, s5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v20
; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v10
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v25
; GFX10-NEXT: v_cndmask_b32_e32 v19, v24, v25, vcc_lo
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v25
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v19
; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v21, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
@@ -6313,14 +6311,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v18, v24
-; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v20, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v21
; GFX10-NEXT: v_cndmask_b32_e64 v24, v19, v25, s5
; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v10
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v27, v27
+; GFX10-NEXT: v_cndmask_b32_e64 v27, v29, v28, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v20, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v24
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v29, v28, s5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v21
; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v1
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v20
; GFX10-NEXT: v_cndmask_b32_e32 v19, v28, v27, vcc_lo
@@ -6335,10 +6333,10 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
; GFX10-NEXT: v_cndmask_b32_e64 v20, v19, v27, s7
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v26, v29, v28, s7
; GFX10-NEXT: v_cndmask_b32_e32 v19, v22, v21, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v29, v28, s7
; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v0
; GFX10-NEXT: v_cndmask_b32_e32 v22, v28, v26, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
@@ -6351,136 +6349,130 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v21, v24
; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v27, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v21, v22, v26, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v25, v25
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v29, v28, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v27, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v7
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v21
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v29, v28, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v14
; GFX10-NEXT: v_cndmask_b32_e32 v24, v28, v22, vcc_lo
-; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v22
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v28, v28
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v28, v28
; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v6
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v7, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v26
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v25, v27
; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v24, v24, v22, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v28, v28
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v26, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v14, s5
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v27, v25
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v7, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v29, v29
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v6, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v25
+; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v26, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v14
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v22
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v25
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v5
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v27, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v13
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v6, s7
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v25, v25
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s7
+; GFX10-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v14
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v5
; GFX10-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v25, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v26, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v5, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v15, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v4, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v25, v25
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v15
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v25, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v11
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v4, s7
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v27, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s7
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v15, v15
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v3, s7
-; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v15, v15
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s6
-; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x5040100
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v2
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v14, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v13, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v4
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v14, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v15, v15
-; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v13, v13
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v2, s6
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v2, s6
-; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v14, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v10
+; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v0
+; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v14, v13
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s6
; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v24, v15
-; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v26, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v3
+; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v26, v25
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v2, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v8
; GFX10-NEXT: s_and_b32 s5, s5, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1
@@ -6488,16 +6480,22 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v14
-; GFX10-NEXT: v_perm_b32 v3, v23, v3, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v2
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v11
; GFX10-NEXT: s_and_b32 s5, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, v1, s5
; GFX10-NEXT: s_and_b32 s5, s7, s8
+; GFX10-NEXT: v_perm_b32 v3, v23, v3, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s5
; GFX10-NEXT: s_and_b32 s5, s9, s10
; GFX10-NEXT: v_perm_b32 v1, v21, v1, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s5
+; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x5040100
; GFX10-NEXT: v_perm_b32 v0, v22, v0, 0x5040100
+; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x5040100
+; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v2, v20, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -6847,75 +6845,73 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v19
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v21, v20, s0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v21, v23, v22, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v22, v21 :: v_dual_lshlrev_b32 v25, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v25
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v24, v23, s1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v29, v28, s1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
@@ -6927,17 +6923,15 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v20, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v24, v25, s3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v27, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v26, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
@@ -6946,162 +6940,147 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v23
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v24, v26, s1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v29, v28, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v28, v23 :: v_dual_lshlrev_b32 v29, 16, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v25, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v23, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v14, s1
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v27, v25
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v23
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v13
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v14
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, v13, v5, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v25, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s3
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v10, s2
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v8, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s2
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v14, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v14, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1
@@ -7109,20 +7088,22 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s5, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v20, v2, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7531,27 +7512,27 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v19
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v22, v21, s1
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v21, v20, s0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -7560,61 +7541,62 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v18
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v22, v21 :: v_dual_lshlrev_b32 v25, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v25
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v24, v23, s1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v25, v29, v28, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v19
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v21
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v25
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v25
@@ -7622,16 +7604,15 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v20, v26
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v24, v25, s3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v27, v27
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v26, vcc_lo
@@ -7643,186 +7624,178 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v23
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v24, v26, s1
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v23, v29, v28, s1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v28, v23 :: v_dual_lshlrev_b32 v29, 16, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v6
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v26
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v25, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v23, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v23
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v14, s1
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v27, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, v7, s1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v14
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v23
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v6, s3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v14
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v14
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v26, 16, v5
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v13, v13, v5, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v25, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v11
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s3
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v4, s3
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, v3, s3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v10, s2
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX12-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v8, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v14, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v14, v13
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v14, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, v2, s3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1
@@ -7831,21 +7804,25 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX12-FAKE16-NEXT: v_perm_b32 v3, v19, v3, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s5, s6
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
+; GFX12-FAKE16-NEXT: v_perm_b32 v4, v21, v4, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v5, v17, v5, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v6, v18, v6, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v20, v2, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x bfloat> @llvm.minimumnum.v16bf16(<16 x bfloat> %x, <16 x bfloat> %y)
@@ -8066,20 +8043,20 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v13
; GFX8-NEXT: v_cndmask_b32_e32 v31, v35, v32, vcc
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
-; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX8-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
+; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc
-; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v31
+; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX8-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v32
; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v35
; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v38
; GFX8-NEXT: v_cmp_lt_f32_e64 s[6:7], v37, v39
; GFX8-NEXT: v_cndmask_b32_e64 v32, v32, v31, s[6:7]
-; GFX8-NEXT: v_cmp_lt_f32_e64 s[6:7], v36, v48
; GFX8-NEXT: s_movk_i32 s10, 0x8000
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[6:7], v36, v48
; GFX8-NEXT: v_cndmask_b32_e64 v36, v38, v35, s[6:7]
; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v32
; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, s10, v31
@@ -8625,20 +8602,20 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v13
; GFX900-NEXT: v_cndmask_b32_e32 v31, v35, v32, vcc
; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
-; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX900-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc
; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
+; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc
-; GFX900-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v31
+; GFX900-NEXT: v_cmp_u_f32_e64 s[4:5], v48, v48
; GFX900-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[4:5]
; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v32
; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v35
; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v38
; GFX900-NEXT: v_cmp_lt_f32_e64 s[6:7], v37, v39
; GFX900-NEXT: v_cndmask_b32_e64 v32, v32, v31, s[6:7]
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[6:7], v36, v48
; GFX900-NEXT: s_movk_i32 s10, 0x8000
+; GFX900-NEXT: v_cmp_lt_f32_e64 s[6:7], v36, v48
; GFX900-NEXT: v_cndmask_b32_e64 v36, v38, v35, s[6:7]
; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v32
; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s10, v31
@@ -9170,14 +9147,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX950-NEXT: v_cndmask_b32_e32 v31, v35, v32, vcc
; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX950-NEXT: v_cmp_u_f32_e64 s[0:1], v48, v48
+; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v31
; GFX950-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc
; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
-; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v31
-; GFX950-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[0:1]
+; GFX950-NEXT: v_cmp_u_f32_e64 s[0:1], v48, v48
+; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v35
; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v31, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v38, v38, v35, s[0:1]
; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v32
-; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v35
; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v38
; GFX950-NEXT: v_cmp_lt_f32_e64 s[2:3], v37, v39
; GFX950-NEXT: s_movk_i32 s6, 0x8000
@@ -9817,14 +9794,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v35, v33
; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v39
; GFX10-NEXT: v_cndmask_b32_e32 v38, v49, v31, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v31
+; GFX10-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
; GFX10-NEXT: v_cndmask_b32_e64 v33, v53, v52, s6
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v36, v37
; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v38
; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v9
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v35, v35
; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v25
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v35, v35
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v33
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v49, v50
; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v9
@@ -9832,93 +9809,93 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v36, v36
; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v25
; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v24
-; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v31, vcc_lo
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v50
; GFX10-NEXT: v_cndmask_b32_e64 v35, v49, v37, s6
; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v50
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v36, v36
+; GFX10-NEXT: v_cndmask_b32_e32 v38, v38, v31, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v53, v37, v35, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v49, v49
; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v24
-; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v7
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v49, v49
; GFX10-NEXT: v_cndmask_b32_e64 v36, v54, v52, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s7, v37, v37
+; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v7
; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v51, v55
+; GFX10-NEXT: v_cmp_u_f32_e64 s7, v37, v37
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v35
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v53
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v36
; GFX10-NEXT: v_cndmask_b32_e64 v66, v52, v36, s7
; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v23
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v49, v49
-; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v6
-; GFX10-NEXT: v_cmp_lt_f32_e64 s9, v51, v54
-; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX10-NEXT: v_cndmask_b32_e64 v37, v65, v64, s7
-; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52
+; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v22
-; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v22
-; GFX10-NEXT: v_cmp_u_f32_e64 s10, v51, v51
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v37
+; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v53
; GFX10-NEXT: v_cndmask_b32_e64 v64, v64, v37, s7
+; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v22
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v49, v49
-; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v64
; GFX10-NEXT: v_cndmask_b32_e64 v49, v67, v65, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v37
+; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v64
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v52
+; GFX10-NEXT: v_cmp_lt_f32_e64 s9, v51, v54
+; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v66
; GFX10-NEXT: v_cndmask_b32_e64 v65, v65, v49, s7
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v68, v69
; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v69, 16, v20
+; GFX10-NEXT: v_cmp_u_f32_e64 s10, v51, v51
; GFX10-NEXT: v_cndmask_b32_e64 v51, v52, v54, s10
-; GFX10-NEXT: v_cmp_lt_f32_e64 s8, v55, v67
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v36
; GFX10-NEXT: v_cmp_u_f32_e64 s10, v68, v68
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v65
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v51
; GFX10-NEXT: v_cndmask_b32_e64 v52, v70, v69, s10
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v66
; GFX10-NEXT: v_cmp_u_f32_e64 s10, v71, v71
-; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v52
; GFX10-NEXT: v_cndmask_b32_e64 v70, v54, v51, s10
; GFX10-NEXT: v_cmp_u_f32_e64 s10, v80, v80
+; GFX10-NEXT: v_cndmask_b32_e64 v69, v69, v52, s10
; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v3
+; GFX10-NEXT: v_cmp_lt_f32_e64 s8, v55, v67
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v65
+; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v19
; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v51
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v70
-; GFX10-NEXT: v_cndmask_b32_e64 v69, v69, v52, s10
-; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v54
-; GFX10-NEXT: v_cmp_lt_f32_e64 s11, v68, v81
+; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v52
; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v69
+; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v54
; GFX10-NEXT: v_cndmask_b32_e64 v54, v80, v71, s10
; GFX10-NEXT: v_cmp_lt_f32_e64 s10, v55, v67
; GFX10-NEXT: v_and_b32_e32 v67, 0xffff0000, v19
+; GFX10-NEXT: v_cmp_lt_f32_e64 s11, v68, v81
; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v2
; GFX10-NEXT: v_cmp_lt_f32_e64 s12, v82, v83
; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v18
; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX10-NEXT: v_cmp_u_f32_e64 s13, v67, v67
; GFX10-NEXT: v_and_b32_e32 v82, 0xffff0000, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v54
+; GFX10-NEXT: v_cmp_u_f32_e64 s13, v67, v67
; GFX10-NEXT: v_cndmask_b32_e64 v67, v71, v54, s13
; GFX10-NEXT: v_cmp_u_f32_e64 s13, v68, v68
-; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v67
; GFX10-NEXT: v_cndmask_b32_e64 v68, v81, v80, s13
; GFX10-NEXT: v_cmp_u_f32_e64 s13, v82, v82
+; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v17
; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v54
+; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v67
; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v68, s13
; GFX10-NEXT: v_cmp_u_f32_e64 s13, v71, v71
; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v17
; GFX10-NEXT: v_cndmask_b32_e64 v82, v82, v81, s13
-; GFX10-NEXT: v_cmp_u_f32_e64 s14, v71, v71
; GFX10-NEXT: v_cmp_lt_f32_e64 s13, v55, v83
; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v68
; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v80
-; GFX10-NEXT: v_cmp_eq_u16_e64 s22, 0x8000, v82
+; GFX10-NEXT: v_cmp_u_f32_e64 s14, v71, v71
; GFX10-NEXT: v_cndmask_b32_e64 v71, v81, v82, s14
; GFX10-NEXT: v_cndmask_b32_e64 v67, v67, v54, s13
+; GFX10-NEXT: v_cmp_eq_u16_e64 s22, 0x8000, v82
; GFX10-NEXT: v_cmp_lt_f32_e64 s14, v55, v83
; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v82
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v71
@@ -9930,9 +9907,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
; GFX10-NEXT: v_cndmask_b32_e64 v83, v83, v81, s16
; GFX10-NEXT: v_cmp_u_f32_e64 s16, v55, v55
-; GFX10-NEXT: v_cmp_eq_u16_e64 s23, 0x8000, v83
; GFX10-NEXT: v_cndmask_b32_e64 v55, v81, v83, s16
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v83
+; GFX10-NEXT: v_cmp_eq_u16_e64 s23, 0x8000, v83
; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v55
; GFX10-NEXT: v_cmp_lt_f32_e64 s16, v81, v84
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v14
@@ -9941,8 +9918,8 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v30
; GFX10-NEXT: v_cndmask_b32_e64 v84, v14, v30, s17
; GFX10-NEXT: v_cmp_u_f32_e64 s17, v81, v81
-; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v84
; GFX10-NEXT: v_cndmask_b32_e64 v81, v30, v84, s17
+; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v84
; GFX10-NEXT: v_cmp_eq_u16_e64 s24, 0x8000, v84
; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v81
; GFX10-NEXT: v_cmp_lt_f32_e64 s17, v86, v85
@@ -9962,13 +9939,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v30
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v86, s19
; GFX10-NEXT: v_cmp_u_f32_e64 s19, v13, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v14
; GFX10-NEXT: v_cndmask_b32_e64 v13, v86, v14, s19
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v14
; GFX10-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v14
; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v13
; GFX10-NEXT: v_cmp_lt_f32_e64 s19, v30, v86
-; GFX10-NEXT: v_and_b32_e32 v86, 0xffff0000, v15
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v14, s19
+; GFX10-NEXT: v_and_b32_e32 v86, 0xffff0000, v15
; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v13
; GFX10-NEXT: v_cmp_eq_f32_e64 s19, 0, v30
; GFX10-NEXT: s_and_b32 s19, s19, s20
@@ -10006,53 +9983,53 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v48
; GFX10-NEXT: v_cmp_u_f32_e64 s18, v29, v29
+; GFX10-NEXT: v_cndmask_b32_e64 v81, v12, v28, s18
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v28
-; GFX10-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v68
; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v50
-; GFX10-NEXT: v_cndmask_b32_e64 v81, v12, v28, s18
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX10-NEXT: v_cmp_u_f32_e64 s18, v29, v29
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v38, v31, s4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v53
+; GFX10-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v68
; GFX10-NEXT: v_cmp_u_f32_e64 s19, v12, v12
; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v32, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33
+; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v53
+; GFX10-NEXT: v_cmp_u_f32_e64 s18, v29, v29
+; GFX10-NEXT: v_cndmask_b32_e64 v29, v38, v31, s4
+; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v37
; GFX10-NEXT: v_cmp_eq_f32_e64 s8, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v64
-; GFX10-NEXT: v_cndmask_b32_e64 v96, v11, v27, s19
-; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v49
; GFX10-NEXT: v_cndmask_b32_e32 v30, v39, v33, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v65
; GFX10-NEXT: s_and_b32 vcc_lo, s6, s20
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v49
; GFX10-NEXT: v_cndmask_b32_e32 v31, v48, v35, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v65
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
-; GFX10-NEXT: v_cmp_eq_f32_e64 s10, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v66
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX10-NEXT: v_cndmask_b32_e64 v96, v11, v27, s19
; GFX10-NEXT: v_cndmask_b32_e64 v97, v28, v81, s18
-; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v15
+; GFX10-NEXT: v_cmp_eq_f32_e64 s10, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v66
; GFX10-NEXT: s_and_b32 vcc_lo, s7, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v51
-; GFX10-NEXT: v_cmp_eq_f32_e64 s11, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v67
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; GFX10-NEXT: v_cndmask_b32_e32 v11, v50, v36, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s8, s4
-; GFX10-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v52
+; GFX10-NEXT: v_cmp_eq_f32_e64 s11, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v67
; GFX10-NEXT: v_cndmask_b32_e32 v28, v53, v37, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s12, 0, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v69
; GFX10-NEXT: s_and_b32 vcc_lo, s9, s5
-; GFX10-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v54
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v51
; GFX10-NEXT: v_cndmask_b32_e32 v32, v64, v49, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e64 s12, 0, v34
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v69
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX10-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v52
+; GFX10-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v54
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v96
; GFX10-NEXT: v_cmp_eq_f32_e64 s13, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v70
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v96
; GFX10-NEXT: v_cmp_eq_f32_e64 s14, 0, v34
; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v55
; GFX10-NEXT: v_cmp_eq_f32_e64 s15, 0, v34
@@ -10106,12 +10083,12 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v87, v87
; GFX10-NEXT: v_cndmask_b32_e32 v37, v51, v37, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s6, s5
-; GFX10-NEXT: v_perm_b32 v14, v14, v36, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e64 v51, v27, v96, s4
; GFX10-NEXT: v_cndmask_b32_e32 v38, v49, v38, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v85
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v97
-; GFX10-NEXT: v_cndmask_b32_e64 v51, v27, v96, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v81
+; GFX10-NEXT: v_perm_b32 v14, v14, v36, 0x5040100
; GFX10-NEXT: s_and_b32 vcc_lo, s17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v27, v80, v85, vcc_lo
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v49
@@ -10128,44 +10105,44 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v10
; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v51, v51
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v25, s5
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52
; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v50
; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v26
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v25, s5
; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v52
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10
; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v54, v53
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
; GFX10-NEXT: v_cndmask_b32_e64 v26, v26, v10, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v55, v55
; GFX10-NEXT: v_cndmask_b32_e64 v51, v25, v9, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
; GFX10-NEXT: v_cndmask_b32_e32 v25, v49, v81, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v51
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_perm_b32 v12, v12, v25, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10
; GFX10-NEXT: v_cndmask_b32_e32 v50, v50, v96, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v53, v52
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v22
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v49, v51, v9, s5
-; GFX10-NEXT: v_cmp_u_f32_e64 s5, v54, v54
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v24
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_cmp_u_f32_e64 s5, v54, v54
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v24, s5
; GFX10-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v49
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v24, s5
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v49
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v22
; GFX10-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v51, v51
; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6
+; GFX10-NEXT: v_perm_b32 v12, v12, v25, 0x5040100
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v24
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52
@@ -10174,119 +10151,111 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v52, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v7
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v24, v24, v8, s5
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v49, v9, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v24
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v22, s5
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v24
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v52, v26
-; GFX10-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6
; GFX10-NEXT: v_cndmask_b32_e64 v23, v23, v7, s5
; GFX10-NEXT: v_cmp_u_f32_e64 s5, v53, v53
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v6, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v26
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v49, v9, vcc_lo
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v22
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v8
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v26
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v5
-; GFX10-NEXT: v_perm_b32 v8, v11, v8, 0x5040100
-; GFX10-NEXT: v_perm_b32 v11, v29, v50, 0x5040100
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v51, v49
; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v21
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v6, s7
; GFX10-NEXT: v_cmp_u_f32_e64 s7, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v21, s7
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v22
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v21, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v5
+; GFX10-NEXT: v_perm_b32 v8, v11, v8, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v5
+; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v5
+; GFX10-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
; GFX10-NEXT: v_perm_b32 v7, v28, v7, 0x5040100
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v23, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v20, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v26, v26
-; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v19, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v49, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v3
; GFX10-NEXT: v_cndmask_b32_e64 v21, v21, v5, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v23, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX10-NEXT: v_cndmask_b32_e64 v20, v20, v4, s4
; GFX10-NEXT: v_cmp_u_f32_e64 s4, v26, v26
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v23
; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v19
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v23
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v26, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v19
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
-; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v20, v20, v4, s7
; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v51, v49
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s7
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6
-; GFX10-NEXT: v_cmp_u_f32_e64 s6, v23, v23
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v19, v3, s7
-; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v19
+; GFX10-NEXT: v_cmp_u_f32_e64 s6, v23, v23
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v18, s6
-; GFX10-NEXT: v_perm_b32 v5, v15, v5, 0x5040100
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v2
-; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v2
-; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v21
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v2
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v22, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v17
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX10-NEXT: v_perm_b32 v6, v32, v6, 0x5040100
-; GFX10-NEXT: v_perm_b32 v15, v38, v37, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v17, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v17
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v21, v21
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v18
-; GFX10-NEXT: v_perm_b32 v4, v33, v4, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v16, s6
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v4
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v22, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v1, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v23, v23
-; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v0
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v0, s6
; GFX10-NEXT: v_cmp_u_f32_e64 s6, v21, v21
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v2, s6
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v2, s6
-; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v22, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v18
+; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v0
+; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v22, v21
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v1, s6
; GFX10-NEXT: v_cmp_lt_f32_e64 s6, v24, v23
-; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v49, v26
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v0, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v3
+; GFX10-NEXT: v_cmp_lt_f32_e64 s7, v49, v26
; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v2, s7
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v16
; GFX10-NEXT: s_and_b32 s5, s5, s6
; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1
@@ -10294,17 +10263,25 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v21
; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v22
-; GFX10-NEXT: v_perm_b32 v3, v34, v3, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v2
+; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v19
; GFX10-NEXT: s_and_b32 s5, s5, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v1, s5
; GFX10-NEXT: s_and_b32 s5, s7, s8
+; GFX10-NEXT: v_perm_b32 v3, v34, v3, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, v0, s5
; GFX10-NEXT: s_and_b32 s5, s9, s10
; GFX10-NEXT: v_perm_b32 v1, v39, v1, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s5
+; GFX10-NEXT: v_perm_b32 v4, v33, v4, 0x5040100
; GFX10-NEXT: v_perm_b32 v0, v48, v0, 0x5040100
+; GFX10-NEXT: v_perm_b32 v5, v15, v5, 0x5040100
+; GFX10-NEXT: v_perm_b32 v6, v32, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v11, v29, v50, 0x5040100
+; GFX10-NEXT: v_perm_b32 v15, v38, v37, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_minimumnum_v32bf16:
@@ -10931,7 +10908,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
@@ -10939,18 +10915,20 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v130, v144, v135, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo
@@ -10964,226 +10942,244 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v102, 16, v11
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v28 :: v_dual_and_b32 v97, 0xffff0000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v11, v27 :: v_dual_lshlrev_b32 v82, 16, v29
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s17, v49, v133
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s16, v37, v132
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s18, v53, v134
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v71, v80, s4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v54, v98
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s16, v37, v132
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s18, v53, v134
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v65, v135
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v69, v144
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v71, v145
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v99, v103, v112, s8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v117, v117
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v38, v147, v34, s13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v87
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v83, v146
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v54, v98
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v112
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v99
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v65, v135
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v86, v147
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v69, v144
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v71, v145
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v83, v146
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v86, v147
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v97, v54
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v113
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v101, v98
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v128
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v117
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v130
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v101, v98
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v103, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v48
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v103, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v115, v132
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v64
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v119, v49
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v68
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v131, v133
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v80
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v38, v38, v34, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v66, v53
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v39
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v84
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v82, v134
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v48
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v82
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v100
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s15, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v64
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s16, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v112
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v68
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s17, s1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v80
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v51, v52, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s18, s2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v84
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s19, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v68, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s20, s4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v100
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v67, v80, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s21, s5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v69, v84, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v69, v84 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s22, s6
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v70, v96, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s23, s7
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v71, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v118
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v83
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v38
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v128
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v113
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v34
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
@@ -11271,47 +11267,45 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v26
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v38, v32
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v25, s1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v38, v32
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v26, v10, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v50, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v31, v29
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v31, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v24, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v51, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8
@@ -11320,138 +11314,123 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v28, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v8, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v22, s1
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v28, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v23, v7, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v21, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v21, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v55, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v20, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v19, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v21, v21, v5, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v25, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s3
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v20
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v18, s2
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v17, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v16, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s2
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v22, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v22, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1
@@ -11459,20 +11438,22 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v17, v1, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v16, v0, s1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s5, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v49, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v18, v2, s1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v34, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v65, v2, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -12173,7 +12154,6 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
@@ -12182,20 +12162,22 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v130, v144, v135, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v13
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -12211,252 +12193,285 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v102, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v28 :: v_dual_and_b32 v97, 0xffff0000, v23
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
; GFX12-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s17, v49, v133
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s16, v37, v132
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s18, v53, v134
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v70, v71, v80, s4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v54, v98
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s16, v37, v132
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s18, v53, v134
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v65, v135
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v69, v144
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v71, v145
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v99, v103, v112, s8
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v117, v117
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v38, v147, v34, s13
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v87
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v83, v146
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v54, v98
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v112
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v99
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v65, v135
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v86, v147
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v69, v144
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v97, v54
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v113
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v71, v145
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v128
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v117
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v101, v98
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v83, v146
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v130
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v86, v147
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v97, v54
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v101, v98
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v103, v37
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v115, v132
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v119, v49
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v48
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v131, v133
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v64
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v68
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v38, v38, v34, s15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v66, v53
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v35
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v39
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v82, v134
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v80
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v53
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v48
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v82
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v84
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s15, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v64
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s16, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v68
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v39, v48, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s17, s1
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v100
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v80
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v51, v52, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s18, s2
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v84
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v64, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s19, s3
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v51, v65, v68 :: v_dual_lshlrev_b32 v50, 16, v15
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v68, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s20, s4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v100
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v52, v67, v80 :: v_dual_lshlrev_b32 v101, 16, v54
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v67, v80, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s21, s5
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v112
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v69, v84, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v69, v84 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s22, s6
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v70, v96, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s23, s7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v112
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v71, v100, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v116
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v118
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v83
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v49
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v38
@@ -12569,52 +12584,53 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v26
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v38, v32
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, v25, s1
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v31
-; GFX12-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v38, v32
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v26, v26, v10, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v50, v50
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v11
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v26
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v31, v29
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
-; GFX12-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v31, v29
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v25, v25, v9, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v24, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, v24, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23
; GFX12-FAKE16-NEXT: v_perm_b32 v10, v51, v10, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v11, v48, v11, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; GFX12-FAKE16-NEXT: v_perm_b32 v12, v39, v12, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
@@ -12625,156 +12641,150 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v28, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v24, v24, v8, s1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, v22, s1
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v28, v26
-; GFX12-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v23, v23, v7, s1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v29, v29
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v23
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v6, s3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v25, v25
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v21, s3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v22
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX12-FAKE16-NEXT: v_perm_b32 v8, v53, v8, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5
+; GFX12-FAKE16-NEXT: v_perm_b32 v9, v52, v9, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v55, v7, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v20, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v19, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v21, v21, v5, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
-; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v21
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v23
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v25, v24
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v19
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s3
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v20, v4, s3
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v27, v26
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v20
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v3, s3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v18, s2
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v17, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
-; GFX12-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v16, s2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v23, v23
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v22, v21
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v18
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v22, v21
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v1, s2
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v23
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v16, v16, v0, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v25
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v18, v18, v2, s3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1
@@ -12783,21 +12793,25 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v21
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v22
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v2
+; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
; GFX12-FAKE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v17, v1, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s3, s4
+; GFX12-FAKE16-NEXT: v_perm_b32 v3, v37, v3, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v16, v0, s1
; GFX12-FAKE16-NEXT: s_and_b32 s1, s5, s6
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v49, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v18, v2, s1
+; GFX12-FAKE16-NEXT: v_perm_b32 v4, v54, v4, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v34, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_perm_b32 v5, v33, v5, 0x5040100
+; GFX12-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v65, v2, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <32 x bfloat> @llvm.minimumnum.v32bf16(<32 x bfloat> %x, <32 x bfloat> %y)
@@ -13598,15 +13612,15 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, v6, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, v0, v2, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX10-NEXT: v_cndmask_b32_sdwa v0, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
@@ -13632,9 +13646,9 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v9, v5
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s4
; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
@@ -14215,9 +14229,9 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v2
; GFX10-NEXT: v_cmp_lt_f32_e64 s5, v7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_cmp_lt_f32_e64 s4, v8, v13
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s4
; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
@@ -14349,35 +14363,34 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
@@ -14527,40 +14540,40 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
diff --git a/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll b/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
index 9d3a84216c586..d4bc8c4b9ab5a 100644
--- a/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
@@ -125,12 +125,11 @@ define i32 @cmpxchg_private_i32(ptr addrspace(5) %ptr) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v2, v1, 1, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_waitcnt expcnt(0)
+; GCN-NEXT: buffer_store_byte v3, off, s[4:7], 0
; GCN-NEXT: v_mov_b32_e32 v0, v1
-; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = cmpxchg ptr addrspace(5) %ptr, i32 0, i32 1 acq_rel monotonic
%result.0 = extractvalue { i32, i1 } %result, 0
@@ -164,13 +163,12 @@ define i64 @cmpxchg_private_i64(ptr addrspace(5) %ptr) {
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v5, v0, 1, vcc
; GCN-NEXT: v_cndmask_b32_e64 v4, v1, 0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GCN-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
; GCN-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen
-; GCN-NEXT: v_cndmask_b32_e64 v3, v0, 1, vcc
-; GCN-NEXT: s_waitcnt expcnt(0)
-; GCN-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
-; GCN-NEXT: buffer_store_byte v4, off, s[4:7], 0
+; GCN-NEXT: buffer_store_byte v6, off, s[4:7], 0
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = cmpxchg ptr addrspace(5) %ptr, i64 0, i64 1 acq_rel monotonic
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index a482292b30c72..0be4ee6b11419 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -266,14 +266,14 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x1000, v0
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v1, vcc_lo
-; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: global_load_b64 v[10:11], v[6:7], off offset:-4096
; GFX11-NEXT: global_load_b64 v[8:9], v[8:9], off offset:2048
-; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, 0x2000, v0
; GFX11-NEXT: global_load_b64 v[6:7], v[6:7], off
+; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, 0x2000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v1, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x3000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: global_load_b64 v[12:13], v[12:13], off offset:2048
@@ -1983,19 +1983,21 @@ define amdgpu_kernel void @DiffBase(ptr addrspace(1) %buffer1,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_and_b32_e32 v12, 0xffff8000, v0
; GFX11-NEXT: v_add_co_u32 v2, s0, s36, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s37, 0, s0
; GFX11-NEXT: v_add_co_u32 v8, s0, s38, v12
+; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, s39, 0, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0x2000
-; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, s39, 0, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x2000, v8
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v9, vcc_lo
-; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x3000, v8
; GFX11-NEXT: global_load_b64 v[6:7], v[2:3], off offset:-4096
+; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x3000, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048
; GFX11-NEXT: s_clause 0x1
@@ -2314,14 +2316,14 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x3000, v0
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
-; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x2000, v0
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: global_load_b64 v[4:5], v[0:1], off
; GFX11-NEXT: global_load_b64 v[6:7], v[2:3], off offset:2048
; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off
+; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, 0x2000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v1, vcc_lo
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, 0x1000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v1, vcc_lo
; GFX11-NEXT: s_clause 0x4
; GFX11-NEXT: global_load_b64 v[12:13], v[8:9], off offset:2048
diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
index fcb08ac782e9e..15d1289ff173d 100644
--- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
@@ -60,20 +60,20 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 64, v10
; GFX9-NEXT: v_addc_co_u32_e64 v11, s[6:7], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v9, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v8, v11, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v9, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[6:7]
-; GFX9-NEXT: v_mov_b32_e32 v21, v20
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-NEXT: v_mov_b32_e32 v21, v20
; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc
; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
@@ -1494,14 +1494,14 @@ define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, 64, v11
; GFX9-NEXT: v_addc_co_u32_e64 v12, s[6:7], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v8, v9
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v10, v12, vcc
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, 0, v11, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v11, vcc
+; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll b/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
index 8c9ebf8d23d9f..5ad870325405f 100644
--- a/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
+++ b/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
@@ -363,8 +363,8 @@ define <2 x float> @v_neg_rsq_neg_v2f32(<2 x float> %val) {
; GCN-IEEE-NEXT: s_mov_b32 s4, 0x80800000
; GCN-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, vcc
-; GCN-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_ldexp_f32_e64 v0, -v0, v2
+; GCN-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, s[4:5]
; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT: v_ldexp_f32_e64 v1, -v1, v2
@@ -423,8 +423,8 @@ define <2 x float> @v_neg_rsq_neg_v2f32_foldable_user(<2 x float> %val0, <2 x fl
; GCN-IEEE-NEXT: s_mov_b32 s4, 0x80800000
; GCN-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 24, vcc
-; GCN-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_ldexp_f32_e64 v0, -v0, v4
+; GCN-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 24, s[4:5]
; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT: v_ldexp_f32_e64 v1, -v1, v4
@@ -483,8 +483,8 @@ define <2 x float> @v_neg_rsq_v2f32(<2 x float> %val) {
; GCN-IEEE-NEXT: s_mov_b32 s4, 0x800000
; GCN-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, vcc
-; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, s[4:5]
; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2
@@ -541,8 +541,8 @@ define <2 x float> @v_neg_rsq_v2f32_foldable_user(<2 x float> %val0, <2 x float>
; GCN-IEEE-NEXT: s_mov_b32 s4, 0x800000
; GCN-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 24, vcc
-; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v4
+; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v1
; GCN-IEEE-NEXT: v_cndmask_b32_e64 v4, 0, 24, s[4:5]
; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v4
diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
index e10846f41da9a..cb5542270b51a 100644
--- a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
@@ -66,11 +66,11 @@ define amdgpu_ps <2 x i32> @s_rsq_f64(double inreg %x) {
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x260
; VI-SDAG-IR-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s1
-; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, s0
; VI-SDAG-IR-NEXT: s_mov_b32 s0, 0
; VI-SDAG-IR-NEXT: s_mov_b32 s1, 0x3fd80000
; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; VI-SDAG-IR-NEXT: v_mul_f64 v[2:3], v[2:3], -v[0:1]
; VI-SDAG-IR-NEXT: v_fma_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-SDAG-IR-NEXT: v_mul_f64 v[4:5], v[2:3], v[0:1]
@@ -149,12 +149,12 @@ define amdgpu_ps <2 x i32> @s_rsq_f64(double inreg %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v0, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v1, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e32 vcc, s[0:1], v[0:1]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -247,10 +247,10 @@ define amdgpu_ps <2 x i32> @s_rsq_f64(double inreg %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
@@ -328,12 +328,12 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_fabs(double inreg %x) {
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x240
; VI-SDAG-IR-NEXT: v_cmp_class_f64_e64 vcc, |s[0:1]|, v2
; VI-SDAG-IR-NEXT: s_and_b32 s2, s1, 0x7fffffff
+; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, s0
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s2
-; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-IR-NEXT: s_mov_b32 s0, 0
; VI-SDAG-IR-NEXT: s_mov_b32 s1, 0x3fd80000
; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; VI-SDAG-IR-NEXT: v_mul_f64 v[2:3], v[2:3], -v[0:1]
; VI-SDAG-IR-NEXT: v_fma_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-SDAG-IR-NEXT: v_mul_f64 v[4:5], v[2:3], v[0:1]
@@ -348,9 +348,9 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_fabs(double inreg %x) {
; VI-GISEL-IR-NEXT: v_rsq_f64_e64 v[0:1], |s[0:1]|
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v2, 0x260
; VI-GISEL-IR-NEXT: v_cmp_class_f64_e64 vcc, |s[0:1]|, v2
+; VI-GISEL-IR-NEXT: s_and_b32 s2, s1, 0x7fffffff
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v3, s0
-; VI-GISEL-IR-NEXT: s_and_b32 s0, s1, 0x7fffffff
-; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, s2
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v5, 0x3fd80000
; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v2, v3, v0, vcc
; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc
@@ -411,12 +411,12 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_fabs(double inreg %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v0, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v1, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e64 vcc, |s[0:1]|, v[0:1]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], |s[0:1]|, v0
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -507,10 +507,10 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_fabs(double inreg %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
@@ -587,11 +587,11 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_f64(double inreg %x) {
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x260
; VI-SDAG-IR-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s1
-; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, s0
; VI-SDAG-IR-NEXT: s_mov_b32 s0, 0
; VI-SDAG-IR-NEXT: s_mov_b32 s1, 0x3fd80000
; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; VI-SDAG-IR-NEXT: v_mul_f64 v[2:3], v[2:3], -v[0:1]
; VI-SDAG-IR-NEXT: v_fma_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-SDAG-IR-NEXT: v_mul_f64 v[4:5], v[2:3], -v[0:1]
@@ -670,12 +670,12 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_f64(double inreg %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v0, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v1, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e32 vcc, s[0:1], v[0:1]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0xbff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -768,10 +768,10 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_f64(double inreg %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], -1.0
@@ -849,12 +849,12 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_neg_f64(double inreg %x) {
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x260
; VI-SDAG-IR-NEXT: v_cmp_class_f64_e64 vcc, -s[0:1], v2
; VI-SDAG-IR-NEXT: s_xor_b32 s2, s1, 0x80000000
+; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, s0
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s2
-; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-IR-NEXT: s_mov_b32 s0, 0
; VI-SDAG-IR-NEXT: s_mov_b32 s1, 0x3fd80000
; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; VI-SDAG-IR-NEXT: v_mul_f64 v[2:3], v[2:3], -v[0:1]
; VI-SDAG-IR-NEXT: v_fma_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-SDAG-IR-NEXT: v_mul_f64 v[4:5], v[2:3], -v[0:1]
@@ -869,9 +869,9 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_neg_f64(double inreg %x) {
; VI-GISEL-IR-NEXT: v_rsq_f64_e64 v[0:1], -s[0:1]
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v2, 0x260
; VI-GISEL-IR-NEXT: v_cmp_class_f64_e64 vcc, -s[0:1], v2
+; VI-GISEL-IR-NEXT: s_xor_b32 s2, s1, 0x80000000
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v3, s0
-; VI-GISEL-IR-NEXT: s_xor_b32 s0, s1, 0x80000000
-; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, s2
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v5, 0x3fd80000
; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v2, v3, v0, vcc
; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc
@@ -934,12 +934,12 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_neg_f64(double inreg %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v0, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v1, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e64 vcc, -s[0:1], v[0:1]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], -s[0:1], v0
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0xbff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -1032,10 +1032,10 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_neg_f64(double inreg %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], -1.0
@@ -1183,12 +1183,12 @@ define double @v_rsq_f64(double %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -1240,10 +1240,10 @@ define double @v_rsq_f64(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1279,10 +1279,10 @@ define double @v_rsq_f64(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1363,12 +1363,12 @@ define double @v_rsq_f64_fabs(double %x) {
; VI-GISEL-IR-NEXT: v_rsq_f64_e64 v[2:3], |v[0:1]|
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, 0x260
; VI-GISEL-IR-NEXT: v_cmp_class_f64_e64 vcc, |v[0:1]|, v4
-; VI-GISEL-IR-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; VI-GISEL-IR-NEXT: v_and_b32_e32 v5, 0x7fffffff, v1
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, 0
-; VI-GISEL-IR-NEXT: v_mov_b32_e32 v5, 0x3fd80000
; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; VI-GISEL-IR-NEXT: v_mul_f64 v[0:1], v[0:1], -v[2:3]
+; VI-GISEL-IR-NEXT: v_mov_b32_e32 v5, 0x3fd80000
; VI-GISEL-IR-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
; VI-GISEL-IR-NEXT: v_mul_f64 v[6:7], v[0:1], v[2:3]
; VI-GISEL-IR-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], 0.5
@@ -1424,12 +1424,12 @@ define double @v_rsq_f64_fabs(double %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e64 vcc, |v[0:1]|, v[2:3]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], |v[0:1]|, v2
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -1481,10 +1481,10 @@ define double @v_rsq_f64_fabs(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1520,10 +1520,10 @@ define double @v_rsq_f64_fabs(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1594,12 +1594,12 @@ define double @v_rsq_f64_missing_contract0(double %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -1651,10 +1651,10 @@ define double @v_rsq_f64_missing_contract0(double %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1690,10 +1690,10 @@ define double @v_rsq_f64_missing_contract0(double %x) {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1763,12 +1763,12 @@ define double @v_rsq_f64_missing_contract1(double %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -1820,10 +1820,10 @@ define double @v_rsq_f64_missing_contract1(double %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -1859,10 +1859,10 @@ define double @v_rsq_f64_missing_contract1(double %x) {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -2000,12 +2000,12 @@ define double @v_neg_rsq_f64(double %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0xbff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -2057,10 +2057,10 @@ define double @v_neg_rsq_f64(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], -1.0
@@ -2096,10 +2096,10 @@ define double @v_neg_rsq_f64(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], -1.0
@@ -2126,9 +2126,9 @@ define <2 x double> @v_rsq_v2f64(<2 x double> %x) {
; SI-SDAG-NEXT: s_mov_b32 s4, 0
; SI-SDAG-NEXT: s_brev_b32 s5, 8
; SI-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[2:3]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x100
; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; SI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -2150,11 +2150,11 @@ define <2 x double> @v_rsq_v2f64(<2 x double> %x) {
; SI-SDAG-NEXT: v_fma_f64 v[12:13], -v[10:11], v[10:11], v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0xffffff80
; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[12:13], v[6:7], v[10:11]
-; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
; SI-SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v14, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
-; SI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v15
+; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
; SI-SDAG-NEXT: v_fma_f64 v[16:17], -v[8:9], v[8:9], v[2:3]
+; SI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v15
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
; SI-SDAG-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[0:1], v[0:1], 1.0
@@ -2202,17 +2202,17 @@ define <2 x double> @v_rsq_v2f64(<2 x double> %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[0:1]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0xffffff80
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x260
-; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x3ff00000
; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[6:7], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[0:1], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0x3ff00000
; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[8:9], v[6:7], 0.5
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
@@ -2278,8 +2278,8 @@ define <2 x double> @v_rsq_v2f64(<2 x double> %x) {
; VI-SDAG-NEXT: s_mov_b32 s4, 0
; VI-SDAG-NEXT: s_brev_b32 s5, 8
; VI-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[2:3]
-; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x100
+; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
; VI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
@@ -2305,18 +2305,18 @@ define <2 x double> @v_rsq_v2f64(<2 x double> %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
; VI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
-; VI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
-; VI-SDAG-NEXT: v_div_scale_f64 v[5:6], s[6:7], v[0:1], v[0:1], 1.0
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v8
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; VI-SDAG-NEXT: v_div_scale_f64 v[5:6], s[4:5], v[0:1], v[0:1], 1.0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[7:8], s[4:5], v[2:3], v[2:3], 1.0
; VI-SDAG-NEXT: v_div_scale_f64 v[17:18], s[4:5], 1.0, v[2:3], 1.0
; VI-SDAG-NEXT: v_rcp_f64_e32 v[9:10], v[5:6]
@@ -2348,52 +2348,52 @@ define <2 x double> @v_rsq_v2f64(<2 x double> %x) {
; VI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; VI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
; VI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; VI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
-; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[2:3], v[6:7]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[10:11], v[6:7], 0.5
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
-; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; VI-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[6:7], v[0:1], v[0:1], 1.0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0
; VI-GISEL-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; VI-GISEL-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0
@@ -2422,9 +2422,9 @@ define <2 x double> @v_neg_rsq_v2f64(<2 x double> %x) {
; SI-SDAG-NEXT: s_mov_b32 s4, 0
; SI-SDAG-NEXT: s_brev_b32 s5, 8
; SI-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[2:3]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x100
; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; SI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -2446,11 +2446,11 @@ define <2 x double> @v_neg_rsq_v2f64(<2 x double> %x) {
; SI-SDAG-NEXT: v_fma_f64 v[12:13], -v[10:11], v[10:11], v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0xffffff80
; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[12:13], v[6:7], v[10:11]
-; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
; SI-SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v14, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
-; SI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v15
+; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
; SI-SDAG-NEXT: v_fma_f64 v[16:17], -v[8:9], v[8:9], v[2:3]
+; SI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v15
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
; SI-SDAG-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[0:1], v[0:1], -1.0
@@ -2498,17 +2498,17 @@ define <2 x double> @v_neg_rsq_v2f64(<2 x double> %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[0:1]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0xffffff80
; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x260
-; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0xbff00000
; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[6:7], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[0:1], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v18, 0xbff00000
; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[8:9], v[6:7], 0.5
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
@@ -2574,8 +2574,8 @@ define <2 x double> @v_neg_rsq_v2f64(<2 x double> %x) {
; VI-SDAG-NEXT: s_mov_b32 s4, 0
; VI-SDAG-NEXT: s_brev_b32 s5, 8
; VI-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[2:3]
-; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x100
+; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
; VI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
@@ -2601,18 +2601,18 @@ define <2 x double> @v_neg_rsq_v2f64(<2 x double> %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
; VI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
-; VI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
-; VI-SDAG-NEXT: v_div_scale_f64 v[5:6], s[6:7], v[0:1], v[0:1], -1.0
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v8
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; VI-SDAG-NEXT: v_div_scale_f64 v[5:6], s[4:5], v[0:1], v[0:1], -1.0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[7:8], s[4:5], v[2:3], v[2:3], -1.0
; VI-SDAG-NEXT: v_div_scale_f64 v[17:18], s[4:5], -1.0, v[2:3], -1.0
; VI-SDAG-NEXT: v_rcp_f64_e32 v[9:10], v[5:6]
@@ -2644,52 +2644,52 @@ define <2 x double> @v_neg_rsq_v2f64(<2 x double> %x) {
; VI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; VI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
; VI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; VI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
-; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[2:3], v[6:7]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[10:11], v[6:7], 0.5
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
-; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; VI-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[6:7], v[0:1], v[0:1], -1.0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], -1.0
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], -1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[16:17], s[4:5], -1.0, v[2:3], -1.0
; VI-GISEL-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; VI-GISEL-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[12:13], vcc, -1.0, v[0:1], -1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0
@@ -2763,12 +2763,12 @@ define <2 x double> @v_neg_rsq_v2f64_poisonelt(<2 x double> %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[0:1]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[6:7], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[0:1], v[6:7]
; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[8:9], v[6:7], 0.5
@@ -2854,10 +2854,10 @@ define <2 x double> @v_neg_rsq_v2f64_poisonelt(<2 x double> %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], -1.0
@@ -2882,52 +2882,52 @@ define <2 x double> @v_neg_rsq_v2f64_poisonelt(<2 x double> %x) {
; VI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; VI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
; VI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; VI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
-; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[2:3], v[6:7]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[10:11], v[6:7], 0.5
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
-; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; VI-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[6:7], v[0:1], v[0:1], -1.0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], -1.0
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], s[4:5]
; VI-GISEL-NEXT: v_div_scale_f64 v[16:17], s[4:5], s[4:5], v[2:3], s[4:5]
; VI-GISEL-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; VI-GISEL-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[12:13], vcc, -1.0, v[0:1], -1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0
@@ -2956,9 +2956,9 @@ define <2 x double> @v_neg_pos_rsq_v2f64(<2 x double> %x) {
; SI-SDAG-NEXT: s_mov_b32 s4, 0
; SI-SDAG-NEXT: s_brev_b32 s5, 8
; SI-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[2:3]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x100
; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; SI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
@@ -2980,11 +2980,11 @@ define <2 x double> @v_neg_pos_rsq_v2f64(<2 x double> %x) {
; SI-SDAG-NEXT: v_fma_f64 v[12:13], -v[10:11], v[10:11], v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0xffffff80
; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[12:13], v[6:7], v[10:11]
-; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
; SI-SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v14, s[4:5]
; SI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
-; SI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v15
+; SI-SDAG-NEXT: v_mov_b32_e32 v15, 0x260
; SI-SDAG-NEXT: v_fma_f64 v[16:17], -v[8:9], v[8:9], v[2:3]
+; SI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v15
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
; SI-SDAG-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[0:1], v[0:1], -1.0
@@ -3033,12 +3033,12 @@ define <2 x double> @v_neg_pos_rsq_v2f64(<2 x double> %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; SI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[0:1]
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[6:7], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[0:1], v[6:7]
; SI-GISEL-NEXT: v_fma_f64 v[10:11], -v[8:9], v[6:7], 0.5
@@ -3111,8 +3111,8 @@ define <2 x double> @v_neg_pos_rsq_v2f64(<2 x double> %x) {
; VI-SDAG-NEXT: s_mov_b32 s4, 0
; VI-SDAG-NEXT: s_brev_b32 s5, 8
; VI-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[2:3]
-; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x100
+; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[4:5]
; VI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4
@@ -3138,18 +3138,18 @@ define <2 x double> @v_neg_pos_rsq_v2f64(<2 x double> %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
; VI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
-; VI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
-; VI-SDAG-NEXT: v_div_scale_f64 v[5:6], s[6:7], v[0:1], v[0:1], -1.0
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], v8
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; VI-SDAG-NEXT: v_div_scale_f64 v[5:6], s[4:5], v[0:1], v[0:1], -1.0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[7:8], s[4:5], v[2:3], v[2:3], 1.0
; VI-SDAG-NEXT: v_div_scale_f64 v[17:18], s[4:5], 1.0, v[2:3], 1.0
; VI-SDAG-NEXT: v_rcp_f64_e32 v[9:10], v[5:6]
@@ -3181,52 +3181,52 @@ define <2 x double> @v_neg_pos_rsq_v2f64(<2 x double> %x) {
; VI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; VI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
; VI-GISEL-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[4:5]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v6
; VI-GISEL-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
-; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; VI-GISEL-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[2:3], v[6:7]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
+; VI-GISEL-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[10:11], v[6:7], 0.5
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[8:9], v[4:5], 0.5
; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[4:5]
+; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
-; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[6:7], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[12:13], v[8:9], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xffffff80
-; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
-; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x260
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v8, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v9
-; VI-GISEL-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], v9
-; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v10
; VI-GISEL-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x260
+; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v9
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[6:7], v[0:1], v[0:1], -1.0
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v8
+; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], -1.0
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0
; VI-GISEL-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; VI-GISEL-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; VI-GISEL-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
-; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; VI-GISEL-NEXT: v_div_scale_f64 v[12:13], vcc, -1.0, v[0:1], -1.0
; VI-GISEL-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; VI-GISEL-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0
@@ -3309,12 +3309,12 @@ define double @v_rsq_f64_fneg_fabs(double %x) {
; VI-GISEL-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-IR-NEXT: v_rsq_f64_e64 v[2:3], -|v[0:1]|
; VI-GISEL-IR-NEXT: v_cmp_eq_f64_e64 vcc, -|v[0:1]|, 0
-; VI-GISEL-IR-NEXT: v_or_b32_e32 v1, 0x80000000, v1
-; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-IR-NEXT: v_or_b32_e32 v4, 0x80000000, v1
; VI-GISEL-IR-NEXT: v_mov_b32_e32 v5, 0x3fd80000
; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-GISEL-IR-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; VI-GISEL-IR-NEXT: v_mul_f64 v[0:1], v[0:1], -v[2:3]
+; VI-GISEL-IR-NEXT: v_mov_b32_e32 v4, 0
; VI-GISEL-IR-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
; VI-GISEL-IR-NEXT: v_mul_f64 v[6:7], v[0:1], v[2:3]
; VI-GISEL-IR-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], 0.5
@@ -3370,12 +3370,12 @@ define double @v_rsq_f64_fneg_fabs(double %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e64 vcc, -|v[0:1]|, v[2:3]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, v2
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
@@ -3427,10 +3427,10 @@ define double @v_rsq_f64_fneg_fabs(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -3466,10 +3466,10 @@ define double @v_rsq_f64_fneg_fabs(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -3628,8 +3628,6 @@ define double @v_rsq_f64__afn_sqrt(double %x) {
; VI-SDAG-CG: ; %bb.0:
; VI-SDAG-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; VI-SDAG-CG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -3637,6 +3635,8 @@ define double @v_rsq_f64__afn_sqrt(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -3656,8 +3656,6 @@ define double @v_rsq_f64__afn_sqrt(double %x) {
; VI-GISEL-CG: ; %bb.0:
; VI-GISEL-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -3665,6 +3663,8 @@ define double @v_rsq_f64__afn_sqrt(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
@@ -3792,12 +3792,12 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v9, 0x260
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -3839,10 +3839,10 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -3872,10 +3872,10 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-GISEL-CG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4006,8 +4006,6 @@ define double @v_rsq_f64__afn(double %x) {
; VI-SDAG-CG: ; %bb.0:
; VI-SDAG-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; VI-SDAG-CG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -4015,6 +4013,8 @@ define double @v_rsq_f64__afn(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4028,8 +4028,6 @@ define double @v_rsq_f64__afn(double %x) {
; VI-GISEL-CG: ; %bb.0:
; VI-GISEL-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -4037,6 +4035,8 @@ define double @v_rsq_f64__afn(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4167,8 +4167,6 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-SDAG-CG: ; %bb.0:
; VI-SDAG-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; VI-SDAG-CG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -4176,6 +4174,8 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4189,8 +4189,6 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-GISEL-CG: ; %bb.0:
; VI-GISEL-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -4198,6 +4196,8 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4469,8 +4469,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-SDAG-CG: ; %bb.0:
; VI-SDAG-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; VI-SDAG-CG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -4478,6 +4476,8 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4491,8 +4491,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-GISEL-CG: ; %bb.0:
; VI-GISEL-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -4500,6 +4498,8 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -4896,12 +4896,12 @@ define double @v_rsq_f64__nnan_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-CG-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-CG-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-CG-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-CG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0xffffff80
; SI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-CG-NEXT: v_mov_b32_e32 v10, 0x3ff00000
; SI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -5172,8 +5172,8 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; VI-SDAG-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[4:5], v[2:3]
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[6:7], v[0:1]
-; VI-SDAG-CG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
-; VI-SDAG-CG-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[2:3]
+; VI-SDAG-CG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[2:3]
+; VI-SDAG-CG-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[0:1]
; VI-SDAG-CG-NEXT: v_mul_f64 v[8:9], v[2:3], v[4:5]
; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[4:5], 0.5
; VI-SDAG-CG-NEXT: v_mul_f64 v[10:11], v[0:1], v[6:7]
@@ -5188,10 +5188,10 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[14:15], -v[10:11], v[10:11], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[14:15], v[6:7], v[10:11]
-; VI-SDAG-CG-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
-; VI-SDAG-CG-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]
-; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; VI-SDAG-CG-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
+; VI-SDAG-CG-NEXT: v_cndmask_b32_e64 v0, v6, v0, s[4:5]
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[5:6], v[0:1]
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[7:8], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[9:10], -v[0:1], v[5:6], 1.0
@@ -5210,7 +5210,6 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[4:5], v[0:1]
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[6:7], v[2:3]
; VI-GISEL-CG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
-; VI-GISEL-CG-NEXT: v_cmp_eq_f64_e64 s[4:5], 0, v[2:3]
; VI-GISEL-CG-NEXT: v_mul_f64 v[8:9], v[4:5], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[0:1], v[4:5]
; VI-GISEL-CG-NEXT: v_mul_f64 v[10:11], v[6:7], 0.5
@@ -5227,21 +5226,22 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; VI-GISEL-CG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; VI-GISEL-CG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; VI-GISEL-CG-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[2:3]
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[4:5], v[0:1]
+; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[4:5]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[6:7]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract afn nnan ninf <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
@@ -5296,11 +5296,11 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, 0x260
; VI-SDAG-IR-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
; VI-SDAG-IR-NEXT: v_mov_b32_e32 v3, s1
-; VI-SDAG-IR-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-IR-NEXT: v_mov_b32_e32 v4, s0
; VI-SDAG-IR-NEXT: s_mov_b32 s0, 0
; VI-SDAG-IR-NEXT: s_mov_b32 s1, 0x3fd80000
; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; VI-SDAG-IR-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; VI-SDAG-IR-NEXT: v_mul_f64 v[2:3], v[2:3], -v[0:1]
; VI-SDAG-IR-NEXT: v_fma_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-SDAG-IR-NEXT: v_mul_f64 v[4:5], v[2:3], v[0:1]
@@ -5383,9 +5383,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-SDAG-CG-LABEL: s_rsq_f64_unsafe:
; VI-SDAG-CG: ; %bb.0:
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v6, 0x260
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v6
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v7, s1
; VI-SDAG-CG-NEXT: v_mul_f64 v[2:3], s[0:1], v[0:1]
; VI-SDAG-CG-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 0.5
@@ -5393,9 +5390,12 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[2:3], v[2:3], s[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v2, s0
-; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v2, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v3, s1
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, s0
+; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
@@ -5408,9 +5408,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-GISEL-CG-LABEL: s_rsq_f64_unsafe:
; VI-GISEL-CG: ; %bb.0:
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v6, 0x260
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v6
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v7, s0
; VI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[2:3], v[0:1], 0.5
@@ -5418,9 +5415,12 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[0:1], s[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v2, s1
-; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v2, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, s[0:1], v2
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v3, s0
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, s1
+; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
@@ -5558,8 +5558,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-SDAG-CG: ; %bb.0:
; VI-SDAG-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
; VI-SDAG-CG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
@@ -5567,6 +5565,8 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -5580,8 +5580,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-GISEL-CG: ; %bb.0:
; VI-GISEL-CG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-CG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_mov_b32_e32 v8, 0x260
-; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v8
; VI-GISEL-CG-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; VI-GISEL-CG-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
@@ -5589,6 +5587,8 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-GISEL-CG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
+; VI-GISEL-CG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-GISEL-CG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
@@ -5853,12 +5853,12 @@ define double @v_div_contract_sqrt_f64(double %x, double %y) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[2:3], v[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 0.5
@@ -5909,10 +5909,10 @@ define double @v_div_contract_sqrt_f64(double %x, double %y) {
; VI-SDAG-NEXT: v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v7
; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v6
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
@@ -5948,10 +5948,10 @@ define double @v_div_contract_sqrt_f64(double %x, double %y) {
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[4:5], v[4:5], v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0xffffff80
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x260
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v7
; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v6
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
@@ -6020,12 +6020,12 @@ define double @v_div_arcp_sqrt_f64(double %x, double %y) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[2:3], v[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 0.5
@@ -6076,10 +6076,10 @@ define double @v_div_arcp_sqrt_f64(double %x, double %y) {
; VI-SDAG-NEXT: v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v7
; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v6
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
@@ -6115,10 +6115,10 @@ define double @v_div_arcp_sqrt_f64(double %x, double %y) {
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[4:5], v[4:5], v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0xffffff80
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x260
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v7
; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v6
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
@@ -6187,12 +6187,12 @@ define double @v_div_contract_arcp_sqrt_f64(double %x, double %y) {
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v5, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[2:3], v[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_rsq_f64_e32 v[4:5], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 0.5
@@ -6243,10 +6243,10 @@ define double @v_div_contract_arcp_sqrt_f64(double %x, double %y) {
; VI-SDAG-NEXT: v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v7
; VI-SDAG-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v6
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
@@ -6282,10 +6282,10 @@ define double @v_div_contract_arcp_sqrt_f64(double %x, double %y) {
; VI-GISEL-NEXT: v_fma_f64 v[8:9], -v[4:5], v[4:5], v[2:3]
; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[8:9], v[6:7], v[4:5]
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0xffffff80
-; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x260
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v7
; VI-GISEL-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[2:3], v6
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-GISEL-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
@@ -6357,17 +6357,17 @@ define double @v_div_const_contract_sqrt_f64(double %x) {
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
; SI-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xffffff80
; SI-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x260
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40700000
-; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x40700000
; SI-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0x40700000
; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
@@ -6418,10 +6418,10 @@ define double @v_div_const_contract_sqrt_f64(double %x) {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
; VI-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x260
+; VI-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-NEXT: v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], s[4:5]
@@ -6457,9 +6457,9 @@ define double @v_div_const_contract_sqrt_f64(double %x) {
; VI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
; VI-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x260
+; VI-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v6
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40700000
; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
diff --git a/llvm/test/CodeGen/AMDGPU/saddo.ll b/llvm/test/CodeGen/AMDGPU/saddo.ll
index 0e9ea5430d0ea..23d8a2cada42c 100644
--- a/llvm/test/CodeGen/AMDGPU/saddo.ll
+++ b/llvm/test/CodeGen/AMDGPU/saddo.ll
@@ -185,8 +185,8 @@ define amdgpu_kernel void @s_saddo_i32(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_add_i32 s4, s6, s7
; GFX9-NEXT: v_add_i32 v1, s6, v1 clamp
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: global_store_dword v0, v2, s[0:1]
; GFX9-NEXT: global_store_byte v0, v1, s[2:3]
@@ -297,8 +297,8 @@ define amdgpu_kernel void @v_saddo_i32(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_i32 v3, v1, v2 clamp
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v1, v3
; GFX9-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v1, v3
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: global_store_byte v0, v1, s[10:11]
; GFX9-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index b690879dab99b..93d0aacf277cd 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -436,14 +436,14 @@ define amdgpu_kernel void @sdiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mul_lo_u32 v8, v6, v2
; GCN-NEXT: v_mul_lo_u32 v10, v5, v3
; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v6
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v5
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v10
-; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v5
-; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
-; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; GCN-NEXT: v_sub_i32_e32 v8, vcc, v0, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1]
; GCN-NEXT: v_sub_i32_e32 v9, vcc, v1, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1]
; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v6
@@ -507,14 +507,14 @@ define amdgpu_kernel void @sdiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_mul_lo_u32 v8, v6, v2
; TONGA-NEXT: v_mul_lo_u32 v10, v5, v3
; TONGA-NEXT: v_add_u32_e32 v9, vcc, 1, v6
+; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v5
; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v8
; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v10
-; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v5
-; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
-; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v0, v2
+; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; TONGA-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1]
; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v1, v3
+; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3]
; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v8, vcc, 1, v6
@@ -879,12 +879,12 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mul_lo_u32 v8, v4, v6
; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v1
; GCN-NEXT: v_sub_i32_e32 v10, vcc, 0, v5
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v12, s[2:3]
; GCN-NEXT: v_mul_lo_u32 v10, v10, v9
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v4
-; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v6
; GCN-NEXT: v_xor_b32_e32 v1, v1, v11
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v6
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[0:1]
; GCN-NEXT: v_sub_i32_e32 v8, vcc, v2, v6
; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v11
@@ -1006,12 +1006,12 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_mul_lo_u32 v8, v4, v6
; TONGA-NEXT: v_add_u32_e32 v12, vcc, 1, v1
; TONGA-NEXT: v_sub_u32_e32 v10, vcc, 0, v5
-; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v2, v8
; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v12, s[2:3]
; TONGA-NEXT: v_mul_lo_u32 v10, v10, v9
+; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v2, v8
; TONGA-NEXT: v_add_u32_e32 v8, vcc, 1, v4
-; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v6
; TONGA-NEXT: v_xor_b32_e32 v1, v1, v11
+; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v6
; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[0:1]
; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v2, v6
; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v11
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index 68466abf31aa0..0458272049d5f 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -350,19 +350,19 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v3
; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v2
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
; GCN-NEXT: v_cndmask_b32_e64 v9, v11, v10, s[4:5]
; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 2, v5
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
-; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
-; GCN-NEXT: v_add_i32_e64 v12, s[4:5], 1, v5
+; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
-; GCN-NEXT: v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
+; GCN-NEXT: v_add_i32_e64 v12, s[4:5], 1, v5
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
+; GCN-NEXT: v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
; GCN-NEXT: v_cndmask_b32_e64 v9, v13, v11, s[4:5]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v1, v12, v10, s[4:5]
@@ -1426,10 +1426,10 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-NEXT: v_add_i32_e64 v7, s[4:5], 2, v3
; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_add_i32_e64 v9, s[4:5], 1, v3
-; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
+; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0
@@ -1617,10 +1617,10 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-NEXT: v_add_i32_e64 v7, s[4:5], 2, v3
; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_add_i32_e64 v9, s[4:5], 1, v3
-; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
+; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
index 79fd8d59a5f67..082780468bfca 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
@@ -2046,10 +2046,10 @@ define half @select_fneg_posk_src_fma_f16(i32 %c, half %x, half %z) {
; CI-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
; CI-NEXT: v_fma_f64 v[1:2], v[3:4], 4.0, v[1:2]
; CI-NEXT: v_and_b32_e32 v3, 0x1ff, v2
-; CI-NEXT: v_or_b32_e32 v1, v3, v1
; CI-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CI-NEXT: v_or_b32_e32 v1, v3, v1
; CI-NEXT: v_and_b32_e32 v3, 0xffe, v4
+; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CI-NEXT: v_bfe_u32 v4, v2, 20, 11
; CI-NEXT: v_or_b32_e32 v1, v3, v1
@@ -2140,10 +2140,10 @@ define half @select_fneg_posk_src_fma_f16_nsz(i32 %c, half %x, half %z) {
; CI-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
; CI-NEXT: v_fma_f64 v[1:2], v[3:4], -4.0, v[1:2]
; CI-NEXT: v_and_b32_e32 v3, 0x1ff, v2
-; CI-NEXT: v_or_b32_e32 v1, v3, v1
; CI-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CI-NEXT: v_or_b32_e32 v1, v3, v1
; CI-NEXT: v_and_b32_e32 v3, 0xffe, v4
+; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CI-NEXT: v_bfe_u32 v4, v2, 20, 11
; CI-NEXT: v_or_b32_e32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
index c026a42993d48..d295ba1ffdf20 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
@@ -3595,8 +3595,8 @@ define <2 x half> @select_fneg_posk_src_fma_v2f16(<2 x i32> %c, <2 x half> %x, <
; CI-NEXT: v_cvt_f32_f16_e32 v10, v2
; CI-NEXT: v_and_b32_e32 v6, 0x1ff, v5
; CI-NEXT: v_or_b32_e32 v4, v6, v4
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CI-NEXT: v_lshrrev_b32_e32 v6, 8, v5
+; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CI-NEXT: v_and_b32_e32 v6, 0xffe, v6
; CI-NEXT: v_bfe_u32 v7, v5, 20, 11
@@ -3640,8 +3640,8 @@ define <2 x half> @select_fneg_posk_src_fma_v2f16(<2 x i32> %c, <2 x half> %x, <
; CI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; CI-NEXT: v_and_b32_e32 v5, 0x1ff, v3
; CI-NEXT: v_or_b32_e32 v2, v5, v2
-; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CI-NEXT: v_lshrrev_b32_e32 v5, 8, v3
+; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CI-NEXT: v_and_b32_e32 v5, 0xffe, v5
; CI-NEXT: v_bfe_u32 v6, v3, 20, 11
diff --git a/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
index 70cca738d4f00..522ac92cc31ae 100644
--- a/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
@@ -822,22 +822,22 @@ define <2 x double> @v_max_pat_v2f64_oge(<2 x double> nofpclass(nan) %a, <2 x do
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_ge_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX7-NEXT: v_cmp_ge_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_max_pat_v2f64_oge:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-NEXT: v_cmp_ge_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX900-NEXT: v_cmp_ge_f64_e32 vcc, v[2:3], v[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_max_pat_v2f64_oge:
@@ -857,11 +857,9 @@ define <2 x double> @v_max_pat_v2f64_oge(<2 x double> nofpclass(nan) %a, <2 x do
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_ge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_ge_f64_e64 s0, v[2:3], v[6:7]
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-NEXT: v_cmp_ge_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_max_pat_v2f64_oge:
@@ -872,13 +870,11 @@ define <2 x double> @v_max_pat_v2f64_oge(<2 x double> nofpclass(nan) %a, <2 x do
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_cmp_ge_f64_e64 s0, v[2:3], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-NEXT: v_cmp_ge_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp oge <2 x double> %a, %b
%select = select nsz <2 x i1> %cmp, <2 x double> %a, <2 x double> %b
@@ -890,22 +886,22 @@ define <2 x double> @v_min_pat_v2f64_olt(<2 x double> nofpclass(nan) %a, <2 x do
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX7-NEXT: v_cmp_lt_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_min_pat_v2f64_olt:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[4:5]
-; GFX900-NEXT: v_cmp_lt_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5]
+; GFX900-NEXT: v_cmp_lt_f64_e32 vcc, v[2:3], v[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_min_pat_v2f64_olt:
@@ -925,11 +921,9 @@ define <2 x double> @v_min_pat_v2f64_olt(<2 x double> nofpclass(nan) %a, <2 x do
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_lt_f64_e64 s0, v[2:3], v[6:7]
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_min_pat_v2f64_olt:
@@ -940,13 +934,11 @@ define <2 x double> @v_min_pat_v2f64_olt(<2 x double> nofpclass(nan) %a, <2 x do
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_cmp_lt_f64_e64 s0, v[2:3], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp olt <2 x double> %a, %b
%select = select nsz <2 x i1> %cmp, <2 x double> %a, <2 x double> %b
diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll
index 36f073054031a..fad4de088016d 100644
--- a/llvm/test/CodeGen/AMDGPU/select.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll
@@ -1914,9 +1914,9 @@ define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32>
; SI-LABEL: v_vselect_v16f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v26
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v28
; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v29
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v26
; SI-NEXT: v_cndmask_b32_e64 v26, v14, v6, s[6:7]
; SI-NEXT: v_cndmask_b32_e64 v6, v14, v6, s[4:5]
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v27
@@ -1968,10 +1968,9 @@ define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32>
; VI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v24
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v14
-; VI-NEXT: v_cmp_eq_u32_e64 s[20:21], 0, v29
; VI-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v26
-; VI-NEXT: v_cmp_eq_u32_e64 s[14:15], 0, v28
; VI-NEXT: v_cmp_eq_u32_e64 s[18:19], 0, v27
+; VI-NEXT: v_cmp_eq_u32_e64 s[20:21], 0, v29
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v12
; VI-NEXT: v_cndmask_b32_e64 v22, v24, v22, s[20:21]
@@ -1980,6 +1979,7 @@ define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32>
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v25
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
; VI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v20
+; VI-NEXT: v_cmp_eq_u32_e64 s[14:15], 0, v28
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v13
; VI-NEXT: v_cndmask_b32_e64 v6, v14, v6, s[14:15]
@@ -2000,33 +2000,33 @@ define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32>
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; VI-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v19
-; VI-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
-; VI-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v11
-; VI-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v30
; VI-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc
-; VI-NEXT: v_or_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; VI-NEXT: v_or_b32_sdwa v1, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; VI-NEXT: v_or_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v13
; VI-NEXT: v_cndmask_b32_e64 v18, v20, v18, s[18:19]
+; VI-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
+; VI-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v30
; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v7
; VI-NEXT: v_cndmask_b32_e64 v7, v15, v7, s[16:17]
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_sdwa v3, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v25
-; VI-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v4, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v18
-; VI-NEXT: v_or_b32_sdwa v5, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; VI-NEXT: v_or_b32_sdwa v6, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
+; VI-NEXT: v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; VI-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
-; VI-NEXT: v_cndmask_b32_e32 v8, v15, v20, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_cndmask_b32_e32 v10, v15, v20, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2223,29 +2223,29 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:108
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:116
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:124
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:128
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:120
; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:100
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:96
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v32
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:84
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v33
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:80
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v34
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:76
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v35
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
@@ -2266,36 +2266,37 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v48
; SI-NEXT: v_cndmask_b32_e64 v48, v29, v13, s[10:11]
+; SI-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[8:9]
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v49
-; SI-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[10:11]
+; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v49
+; SI-NEXT: v_cndmask_b32_e64 v29, v28, v12, s[8:9]
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v50
-; SI-NEXT: v_cndmask_b32_e64 v50, v28, v12, s[10:11]
+; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v50
; SI-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[8:9]
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v51
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:44
-; SI-NEXT: v_cndmask_b32_e64 v28, v27, v11, s[8:9]
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v32
-; SI-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[8:9]
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v33
-; SI-NEXT: v_cndmask_b32_e64 v27, v26, v10, s[8:9]
-; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v31
-; SI-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[8:9]
+; SI-NEXT: v_cndmask_b32_e64 v51, v27, v11, s[8:9]
+; SI-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[6:7]
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v31
+; SI-NEXT: v_cndmask_b32_e64 v27, v26, v10, s[6:7]
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v32
+; SI-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[6:7]
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:32
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:16
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v34
-; SI-NEXT: v_cndmask_b32_e64 v34, v25, v9, s[8:9]
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v33
+; SI-NEXT: v_cndmask_b32_e64 v31, v25, v9, s[6:7]
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v34
; SI-NEXT: v_cndmask_b32_e64 v9, v25, v9, s[6:7]
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v35
; SI-NEXT: v_cndmask_b32_e64 v35, v24, v8, s[6:7]
@@ -2318,34 +2319,35 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; SI-NEXT: v_bfi_b32 v6, s4, v6, v23
; SI-NEXT: v_bfi_b32 v7, s4, v7, v38
; SI-NEXT: v_bfi_b32 v8, s4, v8, v35
-; SI-NEXT: v_bfi_b32 v9, s4, v9, v34
+; SI-NEXT: v_bfi_b32 v9, s4, v9, v31
; SI-NEXT: v_bfi_b32 v10, s4, v10, v27
-; SI-NEXT: v_bfi_b32 v11, s4, v11, v28
-; SI-NEXT: v_bfi_b32 v12, s4, v12, v50
+; SI-NEXT: v_bfi_b32 v11, s4, v11, v51
+; SI-NEXT: v_bfi_b32 v12, s4, v12, v29
; SI-NEXT: v_bfi_b32 v13, s4, v13, v48
; SI-NEXT: v_bfi_b32 v14, s4, v14, v39
; SI-NEXT: v_bfi_b32 v15, s4, v15, v37
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v26
; SI-NEXT: v_cndmask_b32_e32 v26, v21, v5, vcc
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v49
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v50
; SI-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v32
; SI-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v29
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v49
; SI-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
-; SI-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v25
+; SI-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v28
; SI-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v33
; SI-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v36
; SI-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v51
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v34
; SI-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24
; SI-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
@@ -2387,14 +2389,14 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
; VI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:72
; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:128
-; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:64
-; VI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
-; VI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
-; VI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
-; VI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:32
-; VI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:24
-; VI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16
+; VI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:128
+; VI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:64
+; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
+; VI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:48
+; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:40
+; VI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:32
+; VI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:24
+; VI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:16
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:124
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:116
@@ -2433,48 +2435,48 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; VI-NEXT: s_waitcnt vmcnt(11)
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v37
; VI-NEXT: s_waitcnt vmcnt(10)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v55
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v48
; VI-NEXT: v_cndmask_b32_e32 v31, v31, v45, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v23
; VI-NEXT: s_waitcnt vmcnt(9)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v50
-; VI-NEXT: v_cndmask_b32_e32 v50, v43, v55, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v6
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v49
+; VI-NEXT: v_cndmask_b32_e32 v48, v43, v48, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v22
; VI-NEXT: s_waitcnt vmcnt(8)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v53
-; VI-NEXT: v_cndmask_b32_e32 v53, v43, v55, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v5
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v50
+; VI-NEXT: v_cndmask_b32_e32 v49, v43, v49, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v21
; VI-NEXT: s_waitcnt vmcnt(7)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v54
-; VI-NEXT: v_cndmask_b32_e32 v54, v43, v55, vcc
-; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v4
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v51
+; VI-NEXT: v_cndmask_b32_e32 v50, v43, v50, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v20
; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v52
-; VI-NEXT: v_cndmask_b32_e32 v52, v43, v55, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v55
+; VI-NEXT: v_cndmask_b32_e32 v51, v43, v51, vcc
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v19
; VI-NEXT: s_waitcnt vmcnt(5)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v51
-; VI-NEXT: v_cndmask_b32_e32 v51, v43, v55, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v53
+; VI-NEXT: v_cndmask_b32_e32 v53, v43, v55, vcc
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v18
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:108
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:92
; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v49
-; VI-NEXT: v_cndmask_b32_e32 v49, v43, v55, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v54
+; VI-NEXT: v_cndmask_b32_e32 v54, v43, v55, vcc
; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:100
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:84
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:76
; VI-NEXT: s_waitcnt vmcnt(8)
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v48
-; VI-NEXT: v_cndmask_b32_e32 v48, v46, v43, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v52
+; VI-NEXT: v_cndmask_b32_e32 v52, v46, v43, vcc
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:68
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:60
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:52
@@ -2551,19 +2553,19 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: v_or_b32_sdwa v0, v0, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v48
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
; VI-NEXT: v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v49
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v54
; VI-NEXT: v_or_b32_sdwa v2, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v51
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v53
; VI-NEXT: v_or_b32_sdwa v3, v3, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v51
; VI-NEXT: v_or_b32_sdwa v4, v4, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v54
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
; VI-NEXT: v_or_b32_sdwa v5, v5, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v53
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v49
; VI-NEXT: v_or_b32_sdwa v6, v6, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v48
; VI-NEXT: v_or_b32_sdwa v7, v7, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v39
; VI-NEXT: v_or_b32_sdwa v8, v8, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -2791,10 +2793,11 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(31)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v32
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v97, v98, v97, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v99, v100, v99, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v34
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v97, v98, v97, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v33
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v102, v101, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/shift-i128.ll b/llvm/test/CodeGen/AMDGPU/shift-i128.ll
index 942ad6f5f6390..cad6255f81c0e 100644
--- a/llvm/test/CodeGen/AMDGPU/shift-i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/shift-i128.ll
@@ -301,11 +301,11 @@ define <2 x i128> @v_shl_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-NEXT: v_subrev_i32_e64 v9, s[6:7], 64, v8
; GCN-NEXT: v_or_b32_e32 v19, v19, v17
; GCN-NEXT: v_or_b32_e32 v18, v18, v16
-; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_lshl_b64 v[16:17], v[0:1], v9
; GCN-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
+; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_cndmask_b32_e32 v9, v16, v18, vcc
+; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
; GCN-NEXT: v_cndmask_b32_e64 v2, v9, v2, s[4:5]
; GCN-NEXT: v_sub_i32_e64 v9, s[6:7], 64, v12
; GCN-NEXT: v_cndmask_b32_e32 v11, v17, v19, vcc
@@ -318,13 +318,13 @@ define <2 x i128> @v_shl_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-NEXT: v_subrev_i32_e64 v9, s[8:9], 64, v12
; GCN-NEXT: v_or_b32_e32 v11, v17, v10
; GCN-NEXT: v_lshl_b64 v[9:10], v[4:5], v9
-; GCN-NEXT: v_or_b32_e32 v15, v13, v15
-; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
-; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5]
+; GCN-NEXT: v_or_b32_e32 v15, v13, v15
+; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v8
; GCN-NEXT: v_lshl_b64 v[4:5], v[4:5], v12
+; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
; GCN-NEXT: v_cndmask_b32_e64 v6, v9, v6, s[6:7]
; GCN-NEXT: v_cndmask_b32_e64 v9, v10, v11, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[6:7]
@@ -350,11 +350,11 @@ define <2 x i128> @v_lshr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-NEXT: v_subrev_i32_e64 v9, s[6:7], 64, v8
; GCN-NEXT: v_or_b32_e32 v19, v19, v17
; GCN-NEXT: v_or_b32_e32 v18, v18, v16
-; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_lshr_b64 v[16:17], v[2:3], v9
; GCN-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
+; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_cndmask_b32_e32 v9, v16, v18, vcc
+; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
; GCN-NEXT: v_cndmask_b32_e64 v0, v9, v0, s[4:5]
; GCN-NEXT: v_sub_i32_e64 v9, s[6:7], 64, v12
; GCN-NEXT: v_cndmask_b32_e32 v11, v17, v19, vcc
@@ -367,13 +367,13 @@ define <2 x i128> @v_lshr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-NEXT: v_subrev_i32_e64 v9, s[8:9], 64, v12
; GCN-NEXT: v_or_b32_e32 v11, v17, v10
; GCN-NEXT: v_lshr_b64 v[9:10], v[6:7], v9
-; GCN-NEXT: v_or_b32_e32 v15, v13, v15
-; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
-; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5]
+; GCN-NEXT: v_or_b32_e32 v15, v13, v15
+; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v8
; GCN-NEXT: v_lshr_b64 v[6:7], v[6:7], v12
+; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
; GCN-NEXT: v_cndmask_b32_e64 v4, v9, v4, s[6:7]
; GCN-NEXT: v_cndmask_b32_e64 v9, v10, v11, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
@@ -399,11 +399,11 @@ define <2 x i128> @v_ashr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-NEXT: v_subrev_i32_e64 v9, s[6:7], 64, v8
; GCN-NEXT: v_or_b32_e32 v19, v19, v17
; GCN-NEXT: v_or_b32_e32 v18, v18, v16
-; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_ashr_i64 v[16:17], v[2:3], v9
; GCN-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
+; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_cndmask_b32_e32 v9, v16, v18, vcc
+; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
; GCN-NEXT: v_cndmask_b32_e64 v0, v9, v0, s[4:5]
; GCN-NEXT: v_sub_i32_e64 v9, s[6:7], 64, v12
; GCN-NEXT: v_cndmask_b32_e32 v11, v17, v19, vcc
@@ -416,11 +416,11 @@ define <2 x i128> @v_ashr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-NEXT: v_subrev_i32_e64 v9, s[8:9], 64, v12
; GCN-NEXT: v_or_b32_e32 v11, v17, v10
; GCN-NEXT: v_ashr_i64 v[9:10], v[6:7], v9
+; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
+; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5]
; GCN-NEXT: v_or_b32_e32 v15, v13, v15
; GCN-NEXT: v_or_b32_e32 v14, v12, v14
-; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
-; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v4, v9, v4, s[6:7]
; GCN-NEXT: v_cndmask_b32_e64 v9, v10, v11, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
index 101787abf8ea7..5661ab9e06ec6 100644
--- a/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
@@ -513,8 +513,8 @@ define void @v_swap_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v4, 0xbff00000
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -524,9 +524,9 @@ define void @v_swap_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v3, 0xbff00000
-; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_cndmask_b32_e64 v5, v3, 0, vcc
; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index 76f8f484fc763..4810bdf9e98e5 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -861,25 +861,25 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0
-; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v4, v3, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX9-NEXT: global_store_dword v0, v4, s[8:9]
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v6
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 1, v5
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v4
+; GFX9-NEXT: global_store_dword v0, v1, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX9-NEXT: global_store_dword v0, v2, s[10:11]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 3, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v7, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 3, v0
; GFX9-NEXT: global_store_byte v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
@@ -910,21 +910,21 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; VI-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc
; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], v6, v7
; VI-NEXT: v_cndmask_b32_e64 v6, v5, v4, s[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; VI-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; VI-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
-; VI-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; VI-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; VI-NEXT: v_lshlrev_b32_e32 v5, 1, v5
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_sdwa v6, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v5, v7, v5
+; VI-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: flat_store_dword v[0:1], v6
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v0, v9, v5
-; VI-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_and_b32_e32 v0, 3, v0
; VI-NEXT: flat_store_dword v[2:3], v4
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_and_b32_e32 v0, 3, v5
; VI-NEXT: flat_store_byte v[0:1], v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
@@ -956,13 +956,13 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; CI-NEXT: s_mov_b32 s12, s10
; CI-NEXT: s_mov_b32 s13, s11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, v0, v2
-; CI-NEXT: v_cmp_gt_i32_e64 s[0:1], v1, v3
; CI-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc
-; CI-NEXT: v_cndmask_b32_e64 v5, v3, v1, s[0:1]
; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; CI-NEXT: v_cmp_gt_i32_e64 s[0:1], v1, v3
+; CI-NEXT: v_cndmask_b32_e64 v2, v3, v1, s[0:1]
; CI-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; CI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; CI-NEXT: buffer_store_short v5, off, s[4:7], 0 offset:2
+; CI-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
+; CI-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:2
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_store_short v4, off, s[4:7], 0
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -970,7 +970,7 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_store_short v0, off, s[12:15], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_lshlrev_b32_e32 v0, 1, v2
+; CI-NEXT: v_lshlrev_b32_e32 v0, 1, v3
; CI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CI-NEXT: v_or_b32_e32 v0, v1, v0
; CI-NEXT: v_and_b32_e32 v0, 3, v0
diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll
index c870d651eb1aa..37e66edbda7a2 100644
--- a/llvm/test/CodeGen/AMDGPU/srem.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem.ll
@@ -1762,23 +1762,23 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in)
; TAHITI-NEXT: v_subb_u32_e64 v8, s[0:1], v9, v3, vcc
; TAHITI-NEXT: v_sub_i32_e64 v9, s[0:1], v5, v4
; TAHITI-NEXT: v_subbrev_u32_e64 v10, s[2:3], 0, v8, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v10, v3
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; TAHITI-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v9, v4
-; TAHITI-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v10, v3
; TAHITI-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v3, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; TAHITI-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v12, s[0:1], v9, v4
; TAHITI-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v4
-; TAHITI-NEXT: v_subbrev_u32_e64 v8, s[0:1], 0, v8, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v10, v3
+; TAHITI-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v12, s[0:1], v9, v4
; TAHITI-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
+; TAHITI-NEXT: v_subbrev_u32_e64 v8, s[0:1], 0, v8, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; TAHITI-NEXT: v_cndmask_b32_e64 v9, v9, v12, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; TAHITI-NEXT: v_cndmask_b32_e64 v8, v10, v8, s[0:1]
@@ -3119,23 +3119,23 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_subb_u32_e64 v12, s[0:1], v13, v1, vcc
; TAHITI-NEXT: v_sub_i32_e64 v13, s[0:1], v9, v8
; TAHITI-NEXT: v_subbrev_u32_e64 v14, s[2:3], 0, v12, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v5, vcc, v5, v10, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v14, v1
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
; TAHITI-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v13, v8
-; TAHITI-NEXT: v_subb_u32_e32 v5, vcc, v5, v10, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v14, v1
; TAHITI-NEXT: v_subb_u32_e64 v12, s[0:1], v12, v1, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
-; TAHITI-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v16, s[0:1], v13, v8
; TAHITI-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v9, v8
-; TAHITI-NEXT: v_subbrev_u32_e64 v12, s[0:1], 0, v12, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v14, v1
+; TAHITI-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v16, s[0:1], v13, v8
; TAHITI-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v15
+; TAHITI-NEXT: v_subbrev_u32_e64 v12, s[0:1], 0, v12, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v15
; TAHITI-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e64 v12, v14, v12, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
@@ -3261,23 +3261,23 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_subb_u32_e64 v10, s[0:1], v11, v0, vcc
; TAHITI-NEXT: v_sub_i32_e64 v11, s[0:1], v3, v1
; TAHITI-NEXT: v_subbrev_u32_e64 v12, s[2:3], 0, v10, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v4, vcc, v7, v4, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v12, v0
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
; TAHITI-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v11, v1
-; TAHITI-NEXT: v_subb_u32_e32 v4, vcc, v7, v4, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v12, v0
; TAHITI-NEXT: v_subb_u32_e64 v10, s[0:1], v10, v0, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
-; TAHITI-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v14, s[0:1], v11, v1
; TAHITI-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
-; TAHITI-NEXT: v_subbrev_u32_e64 v10, s[0:1], 0, v10, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v12, v0
+; TAHITI-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v14, s[0:1], v11, v1
; TAHITI-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v4, v0
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v13
+; TAHITI-NEXT: v_subbrev_u32_e64 v10, s[0:1], 0, v10, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v13
; TAHITI-NEXT: v_cndmask_b32_e64 v11, v11, v14, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; TAHITI-NEXT: v_cndmask_b32_e64 v10, v12, v10, s[0:1]
@@ -3573,14 +3573,14 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3]
; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v4, v5
; TONGA-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[2:3]
-; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v7, v12
; TONGA-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v12, s[0:1]
+; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v7, v12
; TONGA-NEXT: v_cndmask_b32_e64 v10, v10, v13, s[2:3]
; TONGA-NEXT: v_sub_u32_e64 v13, s[0:1], v4, v5
-; TONGA-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; TONGA-NEXT: v_subb_u32_e32 v1, vcc, v14, v1, vcc
-; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10
+; TONGA-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v12
+; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10
; TONGA-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
@@ -5608,23 +5608,23 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_subb_u32_e64 v20, s[0:1], v21, v8, vcc
; TAHITI-NEXT: v_sub_i32_e64 v21, s[0:1], v11, v9
; TAHITI-NEXT: v_subbrev_u32_e64 v22, s[2:3], 0, v20, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v15, vcc, v15, v18, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v22, v8
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v15, v8
; TAHITI-NEXT: v_cndmask_b32_e64 v23, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v21, v9
-; TAHITI-NEXT: v_subb_u32_e32 v15, vcc, v15, v18, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v24, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v22, v8
; TAHITI-NEXT: v_subb_u32_e64 v20, s[0:1], v20, v8, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v15, v8
-; TAHITI-NEXT: v_cndmask_b32_e64 v23, v23, v24, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v24, s[0:1], v21, v9
; TAHITI-NEXT: v_cndmask_b32_e64 v18, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v11, v9
-; TAHITI-NEXT: v_subbrev_u32_e64 v20, s[0:1], 0, v20, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v22, v8
+; TAHITI-NEXT: v_cndmask_b32_e64 v23, v23, v24, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v24, s[0:1], v21, v9
; TAHITI-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v15, v8
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v23
+; TAHITI-NEXT: v_subbrev_u32_e64 v20, s[0:1], 0, v20, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v8, v18, v9, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v23
; TAHITI-NEXT: v_cndmask_b32_e64 v21, v21, v24, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; TAHITI-NEXT: v_cndmask_b32_e64 v20, v22, v20, s[0:1]
@@ -5750,23 +5750,23 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_subb_u32_e64 v18, s[0:1], v19, v10, vcc
; TAHITI-NEXT: v_sub_i32_e64 v19, s[0:1], v13, v11
; TAHITI-NEXT: v_subbrev_u32_e64 v20, s[2:3], 0, v18, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v14, vcc, v17, v14, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v20, v10
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v14, v10
; TAHITI-NEXT: v_cndmask_b32_e64 v21, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v19, v11
-; TAHITI-NEXT: v_subb_u32_e32 v14, vcc, v17, v14, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v22, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v20, v10
; TAHITI-NEXT: v_subb_u32_e64 v18, s[0:1], v18, v10, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v14, v10
-; TAHITI-NEXT: v_cndmask_b32_e64 v21, v21, v22, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v22, s[0:1], v19, v11
; TAHITI-NEXT: v_cndmask_b32_e64 v17, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v13, v11
-; TAHITI-NEXT: v_subbrev_u32_e64 v18, s[0:1], 0, v18, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v20, v10
+; TAHITI-NEXT: v_cndmask_b32_e64 v21, v21, v22, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v22, s[0:1], v19, v11
; TAHITI-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v14, v10
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v21
+; TAHITI-NEXT: v_subbrev_u32_e64 v18, s[0:1], 0, v18, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v10, v17, v11, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v21
; TAHITI-NEXT: v_cndmask_b32_e64 v19, v19, v22, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; TAHITI-NEXT: v_cndmask_b32_e64 v18, v20, v18, s[0:1]
@@ -5893,23 +5893,23 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_subb_u32_e64 v16, s[0:1], v17, v1, vcc
; TAHITI-NEXT: v_sub_i32_e64 v17, s[0:1], v13, v12
; TAHITI-NEXT: v_subbrev_u32_e64 v18, s[2:3], 0, v16, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v5, vcc, v5, v14, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v18, v1
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
; TAHITI-NEXT: v_cndmask_b32_e64 v19, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v17, v12
-; TAHITI-NEXT: v_subb_u32_e32 v5, vcc, v5, v14, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v20, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v18, v1
; TAHITI-NEXT: v_subb_u32_e64 v16, s[0:1], v16, v1, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
-; TAHITI-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v20, s[0:1], v17, v12
; TAHITI-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v13, v12
-; TAHITI-NEXT: v_subbrev_u32_e64 v16, s[0:1], 0, v16, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v18, v1
+; TAHITI-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v20, s[0:1], v17, v12
; TAHITI-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v19
+; TAHITI-NEXT: v_subbrev_u32_e64 v16, s[0:1], 0, v16, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v1, v14, v12, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v19
; TAHITI-NEXT: v_cndmask_b32_e64 v17, v17, v20, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e64 v16, v18, v16, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
@@ -6035,23 +6035,23 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_subb_u32_e64 v14, s[0:1], v15, v0, vcc
; TAHITI-NEXT: v_sub_i32_e64 v15, s[0:1], v3, v1
; TAHITI-NEXT: v_subbrev_u32_e64 v16, s[2:3], 0, v14, s[0:1]
+; TAHITI-NEXT: v_subb_u32_e32 v4, vcc, v7, v4, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v16, v0
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
; TAHITI-NEXT: v_cndmask_b32_e64 v17, 0, -1, s[2:3]
; TAHITI-NEXT: v_cmp_ge_u32_e64 s[2:3], v15, v1
-; TAHITI-NEXT: v_subb_u32_e32 v4, vcc, v7, v4, vcc
; TAHITI-NEXT: v_cndmask_b32_e64 v18, 0, -1, s[2:3]
-; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v16, v0
; TAHITI-NEXT: v_subb_u32_e64 v14, s[0:1], v14, v0, s[0:1]
-; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
-; TAHITI-NEXT: v_cndmask_b32_e64 v17, v17, v18, s[2:3]
-; TAHITI-NEXT: v_sub_i32_e64 v18, s[0:1], v15, v1
; TAHITI-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
-; TAHITI-NEXT: v_subbrev_u32_e64 v14, s[0:1], 0, v14, s[0:1]
+; TAHITI-NEXT: v_cmp_eq_u32_e64 s[2:3], v16, v0
+; TAHITI-NEXT: v_cndmask_b32_e64 v17, v17, v18, s[2:3]
+; TAHITI-NEXT: v_sub_i32_e64 v18, s[0:1], v15, v1
; TAHITI-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; TAHITI-NEXT: v_cmp_eq_u32_e32 vcc, v4, v0
-; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v17
+; TAHITI-NEXT: v_subbrev_u32_e64 v14, s[0:1], 0, v14, s[0:1]
; TAHITI-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
+; TAHITI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v17
; TAHITI-NEXT: v_cndmask_b32_e64 v15, v15, v18, s[0:1]
; TAHITI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; TAHITI-NEXT: v_cndmask_b32_e64 v14, v16, v14, s[0:1]
@@ -6363,14 +6363,14 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_cndmask_b32_e64 v19, 0, -1, s[2:3]
; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v17, v11
; TONGA-NEXT: v_cndmask_b32_e64 v21, 0, -1, s[2:3]
-; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v18, v10
; TONGA-NEXT: v_subb_u32_e64 v15, s[0:1], v15, v10, s[0:1]
+; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v18, v10
; TONGA-NEXT: v_cndmask_b32_e64 v19, v19, v21, s[2:3]
; TONGA-NEXT: v_sub_u32_e64 v21, s[0:1], v17, v11
-; TONGA-NEXT: v_subbrev_u32_e64 v15, s[0:1], 0, v15, s[0:1]
; TONGA-NEXT: v_subb_u32_e32 v14, vcc, v23, v14, vcc
-; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v19
+; TONGA-NEXT: v_subbrev_u32_e64 v15, s[0:1], 0, v15, s[0:1]
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v14, v10
+; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v19
; TONGA-NEXT: v_cndmask_b32_e64 v15, v18, v15, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v18, 0, -1, vcc
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v13, v11
@@ -6494,16 +6494,16 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_cndmask_b32_e64 v18, 0, -1, s[2:3]
; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v15, v19
; TONGA-NEXT: v_cndmask_b32_e64 v20, 0, -1, s[2:3]
-; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v16, v1
; TONGA-NEXT: v_subb_u32_e64 v14, s[0:1], v14, v1, s[0:1]
+; TONGA-NEXT: v_subb_u32_e32 v5, vcc, v5, v13, vcc
+; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v16, v1
; TONGA-NEXT: v_cndmask_b32_e64 v18, v18, v20, s[2:3]
; TONGA-NEXT: v_sub_u32_e64 v20, s[0:1], v15, v19
-; TONGA-NEXT: v_subb_u32_e32 v5, vcc, v5, v13, vcc
-; TONGA-NEXT: v_subbrev_u32_e64 v14, s[0:1], 0, v14, s[0:1]
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
-; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v18
+; TONGA-NEXT: v_subbrev_u32_e64 v14, s[0:1], 0, v14, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v12, v19
+; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v18
; TONGA-NEXT: v_cndmask_b32_e64 v14, v16, v14, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v16, 0, -1, vcc
; TONGA-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
@@ -6624,14 +6624,14 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[2:3]
; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v4, v5
; TONGA-NEXT: v_cndmask_b32_e64 v17, 0, -1, s[2:3]
-; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v7, v16
; TONGA-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v16, s[0:1]
+; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v7, v16
; TONGA-NEXT: v_cndmask_b32_e64 v14, v14, v17, s[2:3]
; TONGA-NEXT: v_sub_u32_e64 v17, s[0:1], v4, v5
-; TONGA-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; TONGA-NEXT: v_subb_u32_e32 v1, vcc, v18, v1, vcc
-; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v14
+; TONGA-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v16
+; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v14
; TONGA-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index 82196b73b66e4..eafce4ea066ef 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -329,23 +329,23 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v7, v2, vcc
; GCN-NEXT: v_sub_i32_e64 v7, s[4:5], v0, v3
; GCN-NEXT: v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v8, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[6:7]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v8, v2
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v2, s[4:5]
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
-; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[6:7]
-; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v7, v3
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
-; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v8, v2
+; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[6:7]
+; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v7, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
+; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v10, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5]
@@ -1576,8 +1576,8 @@ define i64 @v_test_srem_k_num_i64(i64 %x) {
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v5, v0
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
@@ -1765,8 +1765,8 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v5, v0
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/ssubo.ll b/llvm/test/CodeGen/AMDGPU/ssubo.ll
index 1891857cd7a0c..5280ebb36d078 100644
--- a/llvm/test/CodeGen/AMDGPU/ssubo.ll
+++ b/llvm/test/CodeGen/AMDGPU/ssubo.ll
@@ -183,8 +183,8 @@ define amdgpu_kernel void @s_ssubo_i32(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_sub_i32 s4, s6, s7
; GFX9-NEXT: v_sub_i32 v1, s6, v1 clamp
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: global_store_dword v0, v2, s[0:1]
; GFX9-NEXT: global_store_byte v0, v1, s[2:3]
@@ -295,8 +295,8 @@ define amdgpu_kernel void @v_ssubo_i32(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_i32 v3, v1, v2 clamp
; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v1, v3
; GFX9-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v1, v3
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: global_store_byte v0, v1, s[10:11]
; GFX9-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/uaddo.ll b/llvm/test/CodeGen/AMDGPU/uaddo.ll
index b000fae124ede..1b2044b88105a 100644
--- a/llvm/test/CodeGen/AMDGPU/uaddo.ll
+++ b/llvm/test/CodeGen/AMDGPU/uaddo.ll
@@ -541,10 +541,9 @@ define amdgpu_kernel void @v_uaddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; SI-NEXT: buffer_store_byte v2, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: v_uaddo_i64:
@@ -564,9 +563,9 @@ define amdgpu_kernel void @v_uaddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
-; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-NEXT: flat_store_byte v[6:7], v0
+; VI-NEXT: flat_store_byte v[6:7], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: v_uaddo_i64:
@@ -579,9 +578,9 @@ define amdgpu_kernel void @v_uaddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-NEXT: global_store_byte v4, v0, s[10:11]
+; GFX9-NEXT: global_store_byte v4, v2, s[10:11]
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: v_uaddo_i64:
@@ -654,8 +653,8 @@ define amdgpu_kernel void @v_uaddo_i16(ptr addrspace(1) %out, ptr addrspace(1) %
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, v1, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, v1, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
@@ -679,8 +678,8 @@ define amdgpu_kernel void @v_uaddo_i16(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: v_add_u32_e32 v5, vcc, v4, v5
; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-NEXT: v_and_b32_e32 v6, 0xffff, v5
-; VI-NEXT: v_cmp_lt_u32_e32 vcc, v6, v4
; VI-NEXT: flat_store_short v[0:1], v5
+; VI-NEXT: v_cmp_lt_u32_e32 vcc, v6, v4
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: flat_store_byte v[2:3], v0
; VI-NEXT: s_endpgm
@@ -1152,14 +1151,14 @@ define amdgpu_cs void @sv_uaddo_i128(ptr addrspace(1) %out, i128 inreg %a, i128
; SI-NEXT: v_mov_b32_e32 v6, s3
; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[2:3]
-; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[4:5]
-; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5]
-; SI-NEXT: s_mov_b32 s4, s6
+; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s6
; SI-NEXT: v_and_b32_e32 v2, 1, v2
; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
@@ -1225,14 +1224,14 @@ define amdgpu_cs void @sv_uaddo_i128(ptr addrspace(1) %out, i128 inreg %a, i128
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v4, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[4:5]
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX11-NEXT: v_mov_b16_e32 v2.l, v6.l
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, v6.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, vcc_lo
; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-NEXT: global_store_b32 v[0:1], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index c0918dd78be5f..0bc2880d6f947 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -383,14 +383,14 @@ define amdgpu_kernel void @udiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_mul_lo_u32 v6, v4, v2
; SI-NEXT: v_mul_lo_u32 v8, v5, v3
; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v4
+; SI-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; SI-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 1, v5
-; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
-; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; SI-NEXT: v_sub_i32_e32 v6, vcc, v0, v2
+; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; SI-NEXT: v_sub_i32_e32 v7, vcc, v1, v3
+; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; SI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3]
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; SI-NEXT: v_add_i32_e32 v6, vcc, 1, v4
@@ -438,14 +438,14 @@ define amdgpu_kernel void @udiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_mul_lo_u32 v6, v4, v2
; VI-NEXT: v_mul_lo_u32 v8, v5, v3
; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v4
+; VI-NEXT: v_add_u32_e32 v9, vcc, 1, v5
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_sub_u32_e32 v1, vcc, v1, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, 1, v5
-; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
-; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; VI-NEXT: v_sub_u32_e32 v6, vcc, v0, v2
+; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; VI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; VI-NEXT: v_sub_u32_e32 v7, vcc, v1, v3
+; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; VI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3]
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v4
@@ -492,14 +492,14 @@ define amdgpu_kernel void @udiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mul_lo_u32 v8, v6, v2
; GCN-NEXT: v_add_u32_e32 v9, vcc, 1, v6
; GCN-NEXT: v_mul_lo_u32 v10, v7, v3
-; GCN-NEXT: v_sub_u32_e32 v0, vcc, v0, v8
; GCN-NEXT: v_add_u32_e32 v11, vcc, 1, v7
+; GCN-NEXT: v_sub_u32_e32 v0, vcc, v0, v8
; GCN-NEXT: v_sub_u32_e32 v1, vcc, v1, v10
-; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
-; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; GCN-NEXT: v_sub_u32_e32 v8, vcc, v0, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1]
; GCN-NEXT: v_sub_u32_e32 v9, vcc, v1, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[2:3]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1]
; GCN-NEXT: v_add_u32_e32 v8, vcc, 1, v6
@@ -680,25 +680,25 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_mul_lo_u32 v14, v9, v1
; SI-NEXT: v_mul_lo_u32 v16, v10, v2
; SI-NEXT: v_mul_lo_u32 v18, v11, v3
-; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v12
-; SI-NEXT: v_sub_i32_e32 v5, vcc, v5, v14
-; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v16
-; SI-NEXT: v_sub_i32_e32 v7, vcc, v7, v18
; SI-NEXT: v_add_i32_e32 v13, vcc, 1, v8
; SI-NEXT: v_add_i32_e32 v15, vcc, 1, v9
; SI-NEXT: v_add_i32_e32 v17, vcc, 1, v10
; SI-NEXT: v_add_i32_e32 v19, vcc, 1, v11
-; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
-; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
-; SI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
-; SI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
+; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v12
+; SI-NEXT: v_sub_i32_e32 v5, vcc, v5, v14
+; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v16
+; SI-NEXT: v_sub_i32_e32 v7, vcc, v7, v18
; SI-NEXT: v_sub_i32_e32 v12, vcc, v4, v0
+; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
; SI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1]
; SI-NEXT: v_sub_i32_e32 v13, vcc, v5, v1
+; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
; SI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3]
; SI-NEXT: v_sub_i32_e32 v14, vcc, v6, v2
+; SI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
; SI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5]
; SI-NEXT: v_sub_i32_e32 v15, vcc, v7, v3
+; SI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
; SI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7]
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v12, s[0:1]
; SI-NEXT: v_add_i32_e32 v12, vcc, 1, v8
@@ -775,25 +775,25 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_mul_lo_u32 v14, v9, v1
; VI-NEXT: v_mul_lo_u32 v16, v10, v2
; VI-NEXT: v_mul_lo_u32 v18, v11, v3
-; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v12
-; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v14
-; VI-NEXT: v_sub_u32_e32 v6, vcc, v6, v16
-; VI-NEXT: v_sub_u32_e32 v7, vcc, v7, v18
; VI-NEXT: v_add_u32_e32 v13, vcc, 1, v8
; VI-NEXT: v_add_u32_e32 v15, vcc, 1, v9
; VI-NEXT: v_add_u32_e32 v17, vcc, 1, v10
; VI-NEXT: v_add_u32_e32 v19, vcc, 1, v11
-; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
-; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
-; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
-; VI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
+; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v12
+; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v14
+; VI-NEXT: v_sub_u32_e32 v6, vcc, v6, v16
+; VI-NEXT: v_sub_u32_e32 v7, vcc, v7, v18
; VI-NEXT: v_sub_u32_e32 v12, vcc, v4, v0
+; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0
; VI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1]
; VI-NEXT: v_sub_u32_e32 v13, vcc, v5, v1
+; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1
; VI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3]
; VI-NEXT: v_sub_u32_e32 v14, vcc, v6, v2
+; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
; VI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5]
; VI-NEXT: v_sub_u32_e32 v15, vcc, v7, v3
+; VI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
; VI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7]
; VI-NEXT: v_cndmask_b32_e64 v4, v4, v12, s[0:1]
; VI-NEXT: v_add_u32_e32 v12, vcc, 1, v8
@@ -873,25 +873,25 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mul_lo_u32 v16, v11, v1
; GCN-NEXT: v_mul_lo_u32 v18, v12, v2
; GCN-NEXT: v_mul_lo_u32 v19, v13, v3
+; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10
+; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11
; GCN-NEXT: v_sub_u32_e32 v6, vcc, v6, v14
; GCN-NEXT: v_sub_u32_e32 v7, vcc, v7, v16
; GCN-NEXT: v_sub_u32_e32 v8, vcc, v8, v18
; GCN-NEXT: v_sub_u32_e32 v9, vcc, v9, v19
-; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10
-; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11
; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v12
; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v13
-; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v6, v0
-; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v7, v1
-; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
-; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v9, v3
; GCN-NEXT: v_sub_u32_e32 v18, vcc, v6, v0
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v6, v0
; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v15, s[0:1]
; GCN-NEXT: v_sub_u32_e32 v15, vcc, v7, v1
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v7, v1
; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[2:3]
; GCN-NEXT: v_sub_u32_e32 v17, vcc, v8, v2
+; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
; GCN-NEXT: v_cndmask_b32_e64 v12, v12, v14, s[4:5]
; GCN-NEXT: v_sub_u32_e32 v14, vcc, v9, v3
+; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v9, v3
; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[6:7]
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v18, s[0:1]
; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v10
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index edd84a5f09e5e..60da5d3d97056 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -287,19 +287,19 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5]
; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v4
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v4
+; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
+; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v4
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
; GCN-NEXT: v_cndmask_b32_e64 v7, v10, v8, s[4:5]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v1, v11, v9, s[4:5]
@@ -1056,10 +1056,10 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
; GCN-NEXT: v_add_i32_e64 v6, s[4:5], 2, v2
; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 1, v2
-; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v6, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
index 983acfc2c0699..64c99a70d6f4b 100644
--- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
@@ -824,8 +824,8 @@ define void @v_swap_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v4, 0x3ff00000
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -835,9 +835,9 @@ define void @v_swap_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v3, 0x3ff00000
-; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_cndmask_b32_e64 v5, v3, 0, vcc
; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index 3bb489c654535..1d35d0cb6008d 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -319,23 +319,23 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) {
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
; GCN-NEXT: v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
+; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v2
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]
-; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v6, v2
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3
+; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]
+; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v6, v2
; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
+; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v4, s[4:5]
@@ -1188,8 +1188,8 @@ define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v5, v0
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/usubo.ll b/llvm/test/CodeGen/AMDGPU/usubo.ll
index 8a54ad301f48a..24e5d8277c084 100644
--- a/llvm/test/CodeGen/AMDGPU/usubo.ll
+++ b/llvm/test/CodeGen/AMDGPU/usubo.ll
@@ -540,10 +540,9 @@ define amdgpu_kernel void @v_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; SI-NEXT: buffer_store_byte v2, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: v_usubo_i64:
@@ -563,9 +562,9 @@ define amdgpu_kernel void @v_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
-; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-NEXT: flat_store_byte v[6:7], v0
+; VI-NEXT: flat_store_byte v[6:7], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: v_usubo_i64:
@@ -578,9 +577,9 @@ define amdgpu_kernel void @v_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-NEXT: global_store_byte v4, v0, s[10:11]
+; GFX9-NEXT: global_store_byte v4, v2, s[10:11]
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: v_usubo_i64:
@@ -653,8 +652,8 @@ define amdgpu_kernel void @v_usubo_i16(ptr addrspace(1) %out, ptr addrspace(1) %
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, v1, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, v1, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
@@ -678,8 +677,8 @@ define amdgpu_kernel void @v_usubo_i16(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: v_sub_u32_e32 v5, vcc, v4, v5
; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-NEXT: v_and_b32_e32 v6, 0xffff, v5
-; VI-NEXT: v_cmp_gt_u32_e32 vcc, v6, v4
; VI-NEXT: flat_store_short v[0:1], v5
+; VI-NEXT: v_cmp_gt_u32_e32 vcc, v6, v4
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-NEXT: flat_store_byte v[2:3], v0
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index c7d6f7cd97d1e..c8fa62cd693e0 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -1917,9 +1917,9 @@ define double @test_vector_reduce_fmaximum_v2double(<2 x double> %v) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v2double:
@@ -1927,9 +1927,9 @@ define double @test_vector_reduce_fmaximum_v2double(<2 x double> %v) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v2double:
@@ -1989,8 +1989,8 @@ define double @test_vector_reduce_fmaximum_v3double(<3 x double> %v) {
; GFX7-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2003,8 +2003,8 @@ define double @test_vector_reduce_fmaximum_v3double(<3 x double> %v) {
; GFX8-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2087,12 +2087,12 @@ define double @test_vector_reduce_fmaximum_v4double(<4 x double> %v) {
; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2105,12 +2105,12 @@ define double @test_vector_reduce_fmaximum_v4double(<4 x double> %v) {
; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2209,28 +2209,28 @@ define double @test_vector_reduce_fmaximum_v8double(<8 x double> %v) {
; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2243,28 +2243,28 @@ define double @test_vector_reduce_fmaximum_v8double(<8 x double> %v) {
; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2433,61 +2433,61 @@ define double @test_vector_reduce_fmaximum_v16double(<16 x double> %v) {
; GFX7-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
@@ -2501,61 +2501,61 @@ define double @test_vector_reduce_fmaximum_v16double(<16 x double> %v) {
; GFX8-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 4197d0fcdb814..8a7ffc6a2664f 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -2359,9 +2359,9 @@ define double @test_vector_reduce_fminimum_v2double(<2 x double> %v) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v2double:
@@ -2369,9 +2369,9 @@ define double @test_vector_reduce_fminimum_v2double(<2 x double> %v) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v2double:
@@ -2431,8 +2431,8 @@ define double @test_vector_reduce_fminimum_v3double(<3 x double> %v) {
; GFX7-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2445,8 +2445,8 @@ define double @test_vector_reduce_fminimum_v3double(<3 x double> %v) {
; GFX8-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2529,12 +2529,12 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2547,12 +2547,12 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2673,28 +2673,28 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2707,28 +2707,28 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
@@ -2929,61 +2929,61 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX7-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
@@ -2997,61 +2997,61 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX8-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 8ca36d4b9a5fa..37a331dd5222c 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -3466,11 +3466,11 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3480,11 +3480,11 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3494,11 +3494,10 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -3507,11 +3506,10 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3524,13 +3522,12 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3544,13 +3541,12 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3735,23 +3731,23 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[6:7], v[14:15]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s5, v[2:3], v[10:11]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s5
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3761,23 +3757,23 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3787,22 +3783,18 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[6:7], v[14:15]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[2:3], v[10:11]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3812,22 +3804,18 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3841,27 +3829,25 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[2:3], v[10:11]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3875,27 +3861,25 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3911,35 +3895,35 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX7-SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX7-SDAG-NEXT: v_cmp_gt_i64_e64 s[6:7], v[0:1], v[8:9]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX7-SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], v[4:5], v[12:13]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[10:11]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[8:9]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -3963,35 +3947,35 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX7-GISEL-NEXT: v_cmp_gt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX7-GISEL-NEXT: v_cmp_gt_i64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[8:9]
-; GFX7-GISEL-NEXT: v_cmp_gt_i64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -4015,35 +3999,35 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX8-SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX8-SDAG-NEXT: v_cmp_gt_i64_e64 s[6:7], v[0:1], v[8:9]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX8-SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], v[4:5], v[12:13]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[10:11]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[8:9]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -4067,35 +4051,35 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX8-GISEL-NEXT: v_cmp_gt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX8-GISEL-NEXT: v_cmp_gt_i64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[8:9]
-; GFX8-GISEL-NEXT: v_cmp_gt_i64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -4119,48 +4103,58 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: scratch_load_dword v31, off, s32
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[0:1], v[0:1], v[16:17]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[2:3], v[12:13], v[28:29]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], v[4:5], v[20:21]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[6:7], v[6:7], v[22:23]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[8:9], v[10:11], v[26:27]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[10:11], v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v17, v21, v5, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v23, v7, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v27, v11, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[10:11]
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v16, v20, v4, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v22, v6, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v26, v10, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[10:11]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[6:7]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[0:1], v[16:17], v[12:13]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e64 s[2:3], v[0:1], v[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v17, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, v16, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[2:3]
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[6:7]
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[16:17]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[12:13], v[28:29]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[20:21]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[22:23]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[8:9]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[14:15], v[30:31]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v31, v15, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v30, v14, vcc
-; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[6:7]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -4176,40 +4170,52 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: scratch_load_dword v31, off, s32
; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[2:3], v[4:5], v[20:21]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[6:7], v[8:9], v[24:25]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[10:11], v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[10:11]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[10:11]
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[20:21]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[22:23]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[8:9], v[24:25]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[8:9]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[0:1], v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[2:3]
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[4:5]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[4:5], v[6:7], v[22:23]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[8:9], v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v22, v6, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[8:9]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v23, v7, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[8:9]
-; GFX9-GISEL-NEXT: v_cmp_gt_i64_e64 s[0:1], v[2:3], v[10:11]
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[14:15], v[30:31]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[0:1]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
; GFX9-GISEL-NEXT: v_cmp_gt_i64_e32 vcc, v[6:7], v[4:5]
@@ -4231,48 +4237,48 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[0:1], v[16:17]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s5, v[12:13], v[28:29]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s6, v[6:7], v[22:23]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s4
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s4
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[18:19]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s5, v[4:5], v[20:21]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s6
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s6
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s5, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[10:11]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s5
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[6:7], v[14:15]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[14:15], v[30:31]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4283,48 +4289,48 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[18:19]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s5, v[4:5], v[20:21]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[8:9], v[24:25]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s4
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s5, v[12:13], v[28:29]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s4
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[14:15], v[30:31]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s4
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s4
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4335,48 +4341,40 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[16:17]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[12:13], v[28:29]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s2, v[6:7], v[22:23]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[18:19]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[20:21]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[6:7], v[14:15]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[14:15], v[30:31]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4386,48 +4384,37 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[18:19]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[20:21]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[8:9], v[24:25]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[12:13], v[28:29]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[14:15], v[30:31]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -4441,57 +4428,54 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[16:17]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[12:13], v[28:29]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[10:11], v[26:27]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[18:19]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[20:21]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -4506,60 +4490,51 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[18:19]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[20:21]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[8:9], v[24:25]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[12:13], v[28:29]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[14:15], v[30:31]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[8:9]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 2107f2d6dd587..f52eae62100f1 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -3465,11 +3465,11 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3479,11 +3479,11 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3493,11 +3493,10 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -3506,11 +3505,10 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3523,13 +3521,12 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3543,13 +3540,12 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3734,23 +3730,23 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[6:7], v[14:15]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s5, v[2:3], v[10:11]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s5
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3760,23 +3756,23 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3786,22 +3782,18 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[6:7], v[14:15]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[2:3], v[10:11]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3811,22 +3803,18 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3840,27 +3828,25 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[2:3], v[10:11]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3874,27 +3860,25 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3910,35 +3894,35 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX7-SDAG-NEXT: v_cmp_lt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX7-SDAG-NEXT: v_cmp_lt_i64_e64 s[6:7], v[0:1], v[8:9]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX7-SDAG-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[12:13]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[8:9]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -3962,35 +3946,35 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX7-GISEL-NEXT: v_cmp_lt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX7-GISEL-NEXT: v_cmp_lt_i64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[8:9]
-; GFX7-GISEL-NEXT: v_cmp_lt_i64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -4014,35 +3998,35 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX8-SDAG-NEXT: v_cmp_lt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX8-SDAG-NEXT: v_cmp_lt_i64_e64 s[6:7], v[0:1], v[8:9]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX8-SDAG-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[12:13]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[8:9]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -4066,35 +4050,35 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX8-GISEL-NEXT: v_cmp_lt_i64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[18:19]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[20:21]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[22:23]
-; GFX8-GISEL-NEXT: v_cmp_lt_i64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[12:13], v[28:29]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[8:9]
-; GFX8-GISEL-NEXT: v_cmp_lt_i64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -4118,48 +4102,58 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: scratch_load_dword v31, off, s32
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[24:25]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[0:1], v[0:1], v[16:17]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[2:3], v[12:13], v[28:29]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[20:21]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[6:7], v[6:7], v[22:23]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[8:9], v[10:11], v[26:27]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[10:11], v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v17, v21, v5, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v23, v7, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v27, v11, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[10:11]
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v16, v20, v4, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v22, v6, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v26, v10, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[10:11]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[6:7]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[0:1], v[16:17], v[12:13]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e64 s[2:3], v[0:1], v[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v17, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, v16, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[2:3]
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[6:7]
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[16:17]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[12:13], v[28:29]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[20:21]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[22:23]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[8:9]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[14:15], v[30:31]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v31, v15, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v30, v14, vcc
-; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[6:7]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -4175,40 +4169,52 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: scratch_load_dword v31, off, s32
; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[16:17]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[2:3], v[4:5], v[20:21]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[6:7], v[8:9], v[24:25]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[10:11], v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[10:11]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[10:11]
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[20:21]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[22:23]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[24:25]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[8:9]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[2:3]
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[4:5], v[6:7], v[22:23]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[8:9], v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v22, v6, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[8:9]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v23, v7, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[8:9]
-; GFX9-GISEL-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[10:11]
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[14:15], v[30:31]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[0:1]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
; GFX9-GISEL-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[4:5]
@@ -4230,48 +4236,48 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[0:1], v[16:17]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s5, v[12:13], v[28:29]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s6, v[6:7], v[22:23]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s4
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s4
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[18:19]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s5, v[4:5], v[20:21]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s6
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s6
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s5, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[10:11]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s5
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[6:7], v[14:15]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[14:15], v[30:31]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4282,48 +4288,48 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[18:19]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s5, v[4:5], v[20:21]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[8:9], v[24:25]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s4
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s5, v[12:13], v[28:29]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s4
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[14:15], v[30:31]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s4
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s4
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4334,48 +4340,40 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[16:17]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[28:29]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s2, v[6:7], v[22:23]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[18:19]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[20:21]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[6:7], v[14:15]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[14:15], v[30:31]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4385,48 +4383,37 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[18:19]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[20:21]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[8:9], v[24:25]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[28:29]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[14:15], v[30:31]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -4440,57 +4427,54 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[16:17]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[28:29]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[10:11], v[26:27]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[18:19]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[20:21]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -4505,60 +4489,51 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[18:19]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[20:21]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[8:9], v[24:25]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[28:29]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[14:15], v[30:31]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[8:9]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 78a8ec8d408d0..379e849622b3c 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -3341,11 +3341,11 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3355,11 +3355,11 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3369,11 +3369,10 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -3382,11 +3381,10 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3399,13 +3397,12 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3419,13 +3416,12 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3610,23 +3606,23 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[6:7], v[14:15]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s5, v[2:3], v[10:11]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s5
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3636,23 +3632,23 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3662,22 +3658,18 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[6:7], v[14:15]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[2:3], v[10:11]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3687,22 +3679,18 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3716,27 +3704,25 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[2:3], v[10:11]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3750,27 +3736,25 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3786,35 +3770,35 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX7-SDAG-NEXT: v_cmp_gt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX7-SDAG-NEXT: v_cmp_gt_u64_e64 s[6:7], v[0:1], v[8:9]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX7-SDAG-NEXT: v_cmp_gt_u64_e64 s[4:5], v[4:5], v[12:13]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[10:11]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -3838,35 +3822,35 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX7-GISEL-NEXT: v_cmp_gt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX7-GISEL-NEXT: v_cmp_gt_u64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9]
-; GFX7-GISEL-NEXT: v_cmp_gt_u64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -3890,35 +3874,35 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX8-SDAG-NEXT: v_cmp_gt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX8-SDAG-NEXT: v_cmp_gt_u64_e64 s[6:7], v[0:1], v[8:9]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX8-SDAG-NEXT: v_cmp_gt_u64_e64 s[4:5], v[4:5], v[12:13]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[10:11]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -3942,35 +3926,35 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX8-GISEL-NEXT: v_cmp_gt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX8-GISEL-NEXT: v_cmp_gt_u64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9]
-; GFX8-GISEL-NEXT: v_cmp_gt_u64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -3994,48 +3978,58 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: scratch_load_dword v31, off, s32
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[0:1], v[0:1], v[16:17]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[2:3], v[12:13], v[28:29]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[4:5], v[4:5], v[20:21]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[6:7], v[6:7], v[22:23]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[8:9], v[10:11], v[26:27]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[10:11], v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v17, v21, v5, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v23, v7, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v27, v11, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[10:11]
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v16, v20, v4, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v22, v6, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v26, v10, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[10:11]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[6:7]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[0:1], v[16:17], v[12:13]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e64 s[2:3], v[0:1], v[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v17, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, v16, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[2:3]
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[6:7]
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[16:17]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[28:29]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[20:21]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[22:23]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[14:15], v[30:31]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v31, v15, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v30, v14, vcc
-; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[6:7]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
+; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -4051,40 +4045,52 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: scratch_load_dword v31, off, s32
; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[2:3], v[4:5], v[20:21]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[6:7], v[8:9], v[24:25]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[10:11], v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[10:11]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[10:11]
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[20:21]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[22:23]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[8:9], v[24:25]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[0:1], v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[2:3]
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[4:5], v[6:7], v[22:23]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[8:9], v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v22, v6, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[8:9]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v23, v7, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[8:9]
-; GFX9-GISEL-NEXT: v_cmp_gt_u64_e64 s[0:1], v[2:3], v[10:11]
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[14:15], v[30:31]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[0:1]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
; GFX9-GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[6:7], v[4:5]
@@ -4106,48 +4112,48 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[0:1], v[16:17]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s5, v[12:13], v[28:29]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s6, v[6:7], v[22:23]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s4
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s4
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[18:19]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s5, v[4:5], v[20:21]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s6
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s6
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s5, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[10:11]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s5
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[6:7], v[14:15]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[14:15], v[30:31]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4158,48 +4164,48 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[18:19]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s5, v[4:5], v[20:21]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[8:9], v[24:25]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s4
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s5, v[12:13], v[28:29]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s4
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[14:15], v[30:31]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s4
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s4
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4210,48 +4216,40 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[16:17]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[12:13], v[28:29]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s2, v[6:7], v[22:23]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[18:19]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[20:21]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[6:7], v[14:15]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[14:15], v[30:31]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4261,48 +4259,37 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[18:19]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[20:21]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[8:9], v[24:25]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[12:13], v[28:29]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[14:15], v[30:31]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -4316,57 +4303,54 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[16:17]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[12:13], v[28:29]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[10:11], v[26:27]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[18:19]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[20:21]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -4381,60 +4365,51 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[18:19]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[20:21]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[8:9], v[24:25]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[12:13], v[28:29]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[14:15], v[30:31]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[8:9]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 5b2c1c3134acd..27d1c2ea005da 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -3072,11 +3072,11 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3086,11 +3086,11 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3100,11 +3100,10 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -3113,11 +3112,10 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3130,13 +3128,12 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3150,13 +3147,12 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3341,23 +3337,23 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[6:7], v[14:15]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s5, v[2:3], v[10:11]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s5
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[0:1], v[4:5]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3367,23 +3363,23 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3393,22 +3389,18 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[6:7], v[14:15]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[2:3], v[10:11]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3418,22 +3410,18 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3447,27 +3435,25 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[2:3], v[10:11]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v6, v14, v6
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3481,27 +3467,25 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -3517,35 +3501,35 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX7-SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX7-SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], v[0:1], v[8:9]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX7-SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], v[4:5], v[12:13]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[10:11]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[4:5]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -3569,35 +3553,35 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX7-GISEL-NEXT: v_cmp_lt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX7-GISEL-NEXT: v_cmp_lt_u64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
-; GFX7-GISEL-NEXT: v_cmp_lt_u64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX7-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[4:5]
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -3621,35 +3605,35 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX8-SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX8-SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], v[0:1], v[8:9]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX8-SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], v[4:5], v[12:13]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[10:11]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[6:7]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[6:7]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[4:5]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
@@ -3673,35 +3657,35 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX8-GISEL-NEXT: v_cmp_lt_u64_e64 s[4:5], v[10:11], v[26:27]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[18:19]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[20:21]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[22:23]
-; GFX8-GISEL-NEXT: v_cmp_lt_u64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[28:29]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
-; GFX8-GISEL-NEXT: v_cmp_lt_u64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[6:7]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[6:7]
+; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX8-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[4:5]
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
@@ -3725,48 +3709,58 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: scratch_load_dword v31, off, s32
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[24:25]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[0:1], v[0:1], v[16:17]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[2:3], v[12:13], v[28:29]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], v[4:5], v[20:21]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], v[6:7], v[22:23]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[8:9], v[10:11], v[26:27]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[10:11], v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v17, v21, v5, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v23, v7, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v27, v11, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[10:11]
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v16, v20, v4, s[4:5]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v22, v6, s[6:7]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v26, v10, s[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[10:11]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[6:7]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[0:1], v[16:17], v[12:13]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e64 s[2:3], v[0:1], v[8:9]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v17, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, v16, s[0:1]
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[2:3]
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[6:7]
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[16:17]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[28:29]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[20:21]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[22:23]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[18:19]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
+; GFX9-SDAG-NEXT: s_nop 1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[30:31]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v7, v31, v15, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v30, v14, vcc
-; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[6:7]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -3782,40 +3776,52 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: scratch_load_dword v31, off, s32
; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[16:17]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[2:3], v[4:5], v[20:21]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[6:7], v[8:9], v[24:25]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[10:11], v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s[10:11]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s[2:3]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s[6:7]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s[10:11]
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[20:21]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[22:23]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[24:25]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[28:29]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[2:3], v[4:5], v[12:13]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[0:1], v[2:3], v[18:19]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[2:3]
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[2:3]
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[10:11]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
+; GFX9-GISEL-NEXT: s_nop 1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[4:5]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[4:5], v[6:7], v[22:23]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[8:9], v[10:11], v[26:27]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v22, v6, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v10, v26, v10, s[8:9]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v23, v7, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v11, v27, v11, s[8:9]
-; GFX9-GISEL-NEXT: v_cmp_lt_u64_e64 s[0:1], v[2:3], v[10:11]
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[30:31]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[0:1]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[0:1]
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v30, v14, vcc
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v5, v31, v15, vcc
; GFX9-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[4:5]
@@ -3837,48 +3843,48 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[0:1], v[16:17]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s5, v[12:13], v[28:29]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s6, v[6:7], v[22:23]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s4
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[10:11], v[26:27]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s4
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[18:19]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s5, v[4:5], v[20:21]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s6
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s6
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s5, v[0:1], v[8:9]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[10:11]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s5
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s5
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[6:7], v[14:15]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[14:15], v[30:31]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3889,48 +3895,48 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[18:19]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s5, v[4:5], v[20:21]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s4
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[24:25]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s4
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s5, v[12:13], v[28:29]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s4
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s5
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s5, v[4:5], v[12:13]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s5
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s5
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[14:15], v[30:31]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s4
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[10:11]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s4
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-GISEL-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3941,48 +3947,40 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[16:17]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[12:13], v[28:29]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s2, v[6:7], v[22:23]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[10:11], v[26:27]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[18:19]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[20:21]
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[0:1], v[8:9]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[6:7], v[14:15]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[14:15], v[30:31]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -3992,48 +3990,37 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[18:19]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[20:21]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[8:9], v[24:25]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[12:13], v[28:29]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[14:15], v[30:31]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[8:9]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX11-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -4047,57 +4034,54 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[24:25]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[16:17]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[12:13], v[28:29]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[10:11], v[26:27]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v27, v11, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v26, v10, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[18:19]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[20:21]
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v17, v1 :: v_dual_cndmask_b32 v0, v16, v0
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_cndmask_b32 v12, v28, v12
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v21, v5 :: v_dual_cndmask_b32 v4, v20, v4
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_cndmask_b32 v6, v22, v6
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v11, v3 :: v_dual_cndmask_b32 v2, v10, v2
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[14:15], v[30:31]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v11, v31, v15, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v10, v30, v14, s0
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[10:11]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
@@ -4112,60 +4096,51 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[18:19]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[20:21]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[18:19]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[20:21]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[8:9], v[24:25]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[12:13], v[28:29]
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[28:29]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[14:15], v[30:31]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v30, v14, s0
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v31, v15, s0
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[8:9]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
>From 9f3ca8f93e5808a0210f29b27ffd4e563f894d8b Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 10 Jun 2026 17:02:00 +0100
Subject: [PATCH 2/2] Use a named predicate function
---
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 2 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 0ebf582e6ad8f..4eec0ff6315ba 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -838,7 +838,7 @@ void GCNSubtarget::adjustSchedDependency(
case AMDGPU::V_ADDC_U32_e64:
case AMDGPU::V_SUBB_U32_e64:
case AMDGPU::V_SUBBREV_U32_e64:
- if (getGeneration() < GFX10)
+ if (!hasCarryOutCarryInFastForward())
break;
[[fallthrough]];
case AMDGPU::V_CNDMASK_B32_e64:
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index af47a8725c2d0..6b9923a5d7873 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -755,6 +755,14 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasFmaLegacy32Insts() const { return hasGFX10_3Insts(); }
+ /// \returns true if the VALU has a fast-forward path from v_add/sub with
+ /// carry-out -> v_add/sub with carry-in instructions.
+ bool hasCarryOutCarryInFastForward() const {
+ // GFX10 onwards definitely does. For GFX9 and earlier the documentation is
+ // inconclusive.
+ return HasGFX10Insts;
+ }
+
/// \returns SGPR allocation granularity supported by the subtarget.
unsigned getSGPRAllocGranule() const {
return AMDGPU::IsaInfo::getSGPRAllocGranule(*this);
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