[llvm] [PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC (PR #199733)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 08:49:09 PDT 2026
https://github.com/diggerlin updated https://github.com/llvm/llvm-project/pull/199733
>From 70ee11760d6c191c9217ff059a8b4c701a5b4ccd Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Tue, 26 May 2026 17:24:13 +0000
Subject: [PATCH 1/3] fix combine to ADDC i8 or ADDC i16 for
PPCTargetLowering::combineSignExtendSetCC
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 ++++++++---
llvm/test/CodeGen/PowerPC/testComparesieqsc.ll | 4 ++--
llvm/test/CodeGen/PowerPC/testComparesieqss.ll | 4 ++--
llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll | 4 ++--
llvm/test/CodeGen/PowerPC/testCompareslleqss.ll | 4 ++--
5 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 407093fd2b849..754b04e8c1049 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15873,7 +15873,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
return SDValue();
SDValue N0 = N->getOperand(0);
- if (N0.getOpcode() != ISD::SETCC)
+ if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse())
return SDValue();
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
@@ -15889,16 +15889,21 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
+ if (XVT != MVT::i32 && XVT != MVT::i64)
+ return SDValue();
+
if ((XVT == MVT::i64 || VT == MVT::i64) && !Subtarget.isPPC64())
return SDValue();
// On PPC64, i32 carry operations use the full 64-bit XER register,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
- if (XVT != MVT::i64 && Subtarget.isPPC64())
+ if (XVT != MVT::i64 && Subtarget.isPPC64()) {
+ if (!X.hasOneUse())
+ return SDValue();
// Zero-extend if input type is not 64bits.
X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);
-
+ }
EVT OpVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
// Generate: SUBFE(ADDC(X, -1)).
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
index 541aebb055347..094bbd458bedc 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 56
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
index 67e1729f2488e..eaf251077273e 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
@@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 48
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 48
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
index 75f3017ac0c4f..c920a64764f00 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -100,14 +100,14 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 56
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
index 0670168426a8a..84ef41ea2a817 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -99,14 +99,14 @@ define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 48
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 48
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
>From 872fdeb80f4caf3467a2b574e7744f0fdaa6e84b Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Wed, 10 Jun 2026 14:35:28 +0000
Subject: [PATCH 2/3] address comment
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 754b04e8c1049..f3487504a2438 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15873,7 +15873,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
return SDValue();
SDValue N0 = N->getOperand(0);
- if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse())
+ if (N0.getOpcode() != ISD::SETCC)
return SDValue();
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
@@ -15899,8 +15899,6 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
if (XVT != MVT::i64 && Subtarget.isPPC64()) {
- if (!X.hasOneUse())
- return SDValue();
// Zero-extend if input type is not 64bits.
X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);
}
>From 3e54682bf1680e2b4f4221f0dac367fb49d1a087 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Wed, 10 Jun 2026 16:04:07 +0000
Subject: [PATCH 3/3] add test case
---
llvm/test/CodeGen/PowerPC/issue-203012.ll | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/issue-203012.ll
diff --git a/llvm/test/CodeGen/PowerPC/issue-203012.ll b/llvm/test/CodeGen/PowerPC/issue-203012.ll
new file mode 100644
index 0000000000000..15fe2eca2e671
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/issue-203012.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
+
+define i32 @main(i8 %0) {
+; CHECK-LABEL: main:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: clrlwi r3, r3, 24
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp2.not.i.4 = icmp eq i8 %0, 0
+ %1 = sext i1 %cmp2.not.i.4 to i32
+ ret i32 %1
+}
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