[llvm] f281b02 - [SPIR-V] Fix result type deduction for sub-byte G_TRUNC (#202717)

[via llvm-commits]

Author: Arseniy Obolenskiy
Date: 2026-06-10T16:56:41+02:00
New Revision: f281b029ab91e65fd482405aab08cfe8954993b8

URL: https://github.com/llvm/llvm-project/commit/f281b029ab91e65fd482405aab08cfe8954993b8
DIFF: https://github.com/llvm/llvm-project/commit/f281b029ab91e65fd482405aab08cfe8954993b8.diff

LOG: [SPIR-V] Fix result type deduction for sub-byte G_TRUNC (#202717)

G_TRUNC fell through to the default operand-based deduction, so a
sub-byte truncation inherited its wider source type and fed an ill-typed
value into i32 consumers

Added: 
    

Modified: 
    llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
    llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index 8fe59ba4f8e9c..2b33dabde4612 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -277,6 +277,7 @@ static SPIRVTypeInst deduceResultTypeFromOperands(MachineInstr *I,
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
+  case TargetOpcode::G_TRUNC:
     return deduceIntTypeFromResult(ResVReg, MIB, GR);
   case TargetOpcode::G_BUILD_VECTOR:
     return deduceTypeFromOperandRange(I, MIB, GR, 1, I->getNumOperands());

diff  --git a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
index e3b2f48ceead3..b34c69733bdbf 100644
--- a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
+++ b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
@@ -137,3 +137,20 @@ define spir_kernel void @trunc_v2i50_to_v2i32(ptr addrspace(1) %arg, <2 x i50> %
   store <2 x i32> %tr, ptr addrspace(1) %arg
   ret void
 }
+
+; CHECK: OpFunction
+; CHECK: %[[#TArg:]] = OpFunctionParameter
+; CHECK-EXT: %[[#TTr:]] = OpUConvert %[[#ExtInt32]] %[[#TArg]]
+; CHECK-EXT: %[[#TZext:]] = OpBitwiseAnd %[[#ExtInt32]] %[[#TTr]] %[[#]]
+; CHECK-EXT: %[[#]] = OpIAdd %[[#ExtInt32]] %[[#TZext]] %[[#]]
+; CHECK-NOEXT: %[[#TAnd:]] = OpBitwiseAnd %[[#Int64]] %[[#TArg]] %[[#]]
+; CHECK-NOEXT: %[[#TConv:]] = OpUConvert %[[#Int32]] %[[#TAnd]]
+; CHECK-NOEXT: %[[#TZext:]] = OpBitwiseAnd %[[#Int32]] %[[#TConv]] %[[#]]
+; CHECK-NOEXT: %[[#]] = OpIAdd %[[#Int32]] %[[#TZext]] %[[#]]
+define spir_kernel void @trunc_i64_to_i5_zext_to_i32(i64 %val, ptr addrspace(1) %out) {
+  %tr = trunc i64 %val to i5
+  %z = zext i5 %tr to i32
+  %r = add i32 %z, 1
+  store i32 %r, ptr addrspace(1) %out
+  ret void
+}