[llvm] [AArch64][TableGen] Define ZA, ZT0 and FPMR memory defvars (PR #154144)

[via llvm-commits]

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@@ -3132,8 +3169,8 @@ let TargetPrefix = "aarch64" in {
           LLVMMatchType<0>,
           llvm_nxv16i8_ty,
           llvm_i32_ty],
-         [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<5>>,
-          IntrInaccessibleMemOnly]>;
+         [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<5>>, IntrRead<[ZA]>,
+          IntrWrite<[ZA]>]>;
 
   def int_aarch64_sme_ftmopa_za16 : SME_OuterProduct_TMOP_Intrinsic;
   def int_aarch64_sme_ftmopa_za32 : SME_OuterProduct_TMOP_Intrinsic;
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Lukacma wrote:

These intrinsics are also used for fp8 operations so you need to split them and define a variant with FPMR read.

https://github.com/llvm/llvm-project/pull/154144