[llvm] [AMDGPU][NFC] New tests for uncovered cases in SIInstrInfo.cpp (PR #200414)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 04:05:01 PDT 2026
https://github.com/ambergorzynski updated https://github.com/llvm/llvm-project/pull/200414
>From 84d4587b784014ace546d23beaf6ed8d703452d3 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Fri, 29 May 2026 09:06:22 -0500
Subject: [PATCH 01/11] [AMDGPU][NFC] Add aborts to demonstrate tests
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ef9d184555bd6..c03f37d44bb9a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6196,16 +6196,16 @@ unsigned SIInstrInfo::getVALUOp(unsigned Opc) const {
case AMDGPU::S_FMAAK_F32: return AMDGPU::V_FMAAK_F32;
case AMDGPU::S_CMP_LT_F32: return AMDGPU::V_CMP_LT_F32_e64;
case AMDGPU::S_CMP_EQ_F32: return AMDGPU::V_CMP_EQ_F32_e64;
- case AMDGPU::S_CMP_LE_F32: return AMDGPU::V_CMP_LE_F32_e64;
- case AMDGPU::S_CMP_GT_F32: return AMDGPU::V_CMP_GT_F32_e64;
+ case AMDGPU::S_CMP_LE_F32: {abort(); return AMDGPU::V_CMP_LE_F32_e64;}
+ case AMDGPU::S_CMP_GT_F32: {abort(); return AMDGPU::V_CMP_GT_F32_e64;}
case AMDGPU::S_CMP_LG_F32: return AMDGPU::V_CMP_LG_F32_e64;
case AMDGPU::S_CMP_GE_F32: return AMDGPU::V_CMP_GE_F32_e64;
case AMDGPU::S_CMP_O_F32: return AMDGPU::V_CMP_O_F32_e64;
case AMDGPU::S_CMP_U_F32: return AMDGPU::V_CMP_U_F32_e64;
case AMDGPU::S_CMP_NGE_F32: return AMDGPU::V_CMP_NGE_F32_e64;
- case AMDGPU::S_CMP_NLG_F32: return AMDGPU::V_CMP_NLG_F32_e64;
+ case AMDGPU::S_CMP_NLG_F32: {abort(); return AMDGPU::V_CMP_NLG_F32_e64;}
case AMDGPU::S_CMP_NGT_F32: return AMDGPU::V_CMP_NGT_F32_e64;
- case AMDGPU::S_CMP_NLE_F32: return AMDGPU::V_CMP_NLE_F32_e64;
+ case AMDGPU::S_CMP_NLE_F32: {abort(); return AMDGPU::V_CMP_NLE_F32_e64;}
case AMDGPU::S_CMP_NEQ_F32: return AMDGPU::V_CMP_NEQ_F32_e64;
case AMDGPU::S_CMP_NLT_F32: return AMDGPU::V_CMP_NLT_F32_e64;
case AMDGPU::S_CMP_LT_F16:
>From 3fd9c535c4581c36be8750bb929a009197a2d772 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Fri, 29 May 2026 09:07:43 -0500
Subject: [PATCH 02/11] [AMDGPU][NFC] New tests targeting SIInstrInfo.cpp
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 246 ++++++++++++++++++++
1 file changed, 246 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
new file mode 100644
index 0000000000000..d9c3b781beef1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
+
+define <8 x i1> @siinstrinfo_vector_f32_ole() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ole:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <8 x float>, ptr addrspace(1) null, align 32
+ %C = fcmp ole <8 x float> %LGV, zeroinitializer
+ ret <8 x i1> %C
+}
+
+define <4 x i1> @siinstrinfo_vector_f32_ogt() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ogt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ogt <4 x float> %LGV, zeroinitializer
+ ret <4 x i1> %C
+}
+
+define <32 x i1> @siinstrinfo_vector_f32_ueq() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ueq:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
+; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
+; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
+; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-NEXT: s_clause 0x2
+; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
+; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
+; CHECK-NEXT: s_wait_loadcnt 0x7
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x6
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x5
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x4
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x3
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x2
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <32 x float>, ptr addrspace(1) null, align 128
+ %C = fcmp ueq <32 x float> %LGV, zeroinitializer
+ ret <32 x i1> %C
+}
+
+define <4 x i1> @siinstrinfo_vector_f32_ugt() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ugt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
+ ret <4 x i1> %C
+}
+
>From 49b70687f25bb2547c17977cbca8f2328963faac Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Mon, 8 Jun 2026 09:47:38 -0500
Subject: [PATCH 03/11] [AMDGPU][NFC] Shorten test names
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
index d9c3b781beef1..50cb6127041d6 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
-define <8 x i1> @siinstrinfo_vector_f32_ole() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ole:
+define <8 x i1> @vector_f32_ole() {
+; CHECK-LABEL: vector_f32_ole:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
@@ -47,8 +47,8 @@ entry:
ret <8 x i1> %C
}
-define <4 x i1> @siinstrinfo_vector_f32_ogt() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ogt:
+define <4 x i1> @vector_f32_ogt() {
+; CHECK-LABEL: vector_f32_ogt:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
@@ -77,8 +77,8 @@ entry:
ret <4 x i1> %C
}
-define <32 x i1> @siinstrinfo_vector_f32_ueq() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ueq:
+define <32 x i1> @vector_f32_ueq() {
+; CHECK-LABEL: vector_f32_ueq:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
@@ -214,8 +214,8 @@ entry:
ret <32 x i1> %C
}
-define <4 x i1> @siinstrinfo_vector_f32_ugt() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ugt:
+define <4 x i1> @vector_f32_ugt() {
+; CHECK-LABEL: vector_f32_ugt:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
>From ccc4b6e013817783a8c37cf657fe80e13219ca91 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Mon, 8 Jun 2026 12:18:21 -0500
Subject: [PATCH 04/11] [AMDGPU][NFC] Update test checks
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 33 ++++++++++++---------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
index 50cb6127041d6..bf7d66d5d83c3 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -9,8 +9,9 @@ define <8 x i1> @vector_f32_ole() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
+; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
@@ -55,7 +56,8 @@ define <4 x i1> @vector_f32_ogt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
@@ -85,22 +87,24 @@ define <32 x i1> @vector_f32_ueq() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
+; CHECK-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 32
+; CHECK-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v12, 48
; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: v_mov_b32_e32 v13, 0
; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-NEXT: v_mov_b32_e32 v16, 64
+; CHECK-NEXT: v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v20, 0x50
; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
-; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-NEXT: v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, 0x60
; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
-; CHECK-NEXT: s_clause 0x2
+; CHECK-NEXT: v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v28, 0x70
; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-NEXT: v_mov_b32_e32 v29, 0
+; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
; CHECK-NEXT: s_wait_loadcnt 0x7
@@ -222,7 +226,8 @@ define <4 x i1> @vector_f32_ugt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
>From 777eeb3f2c2d063ce50a1505368796a1c853c611 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Mon, 8 Jun 2026 12:19:44 -0500
Subject: [PATCH 05/11] [AMDGPU][NFC] Remove aborts
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c03f37d44bb9a..ef9d184555bd6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6196,16 +6196,16 @@ unsigned SIInstrInfo::getVALUOp(unsigned Opc) const {
case AMDGPU::S_FMAAK_F32: return AMDGPU::V_FMAAK_F32;
case AMDGPU::S_CMP_LT_F32: return AMDGPU::V_CMP_LT_F32_e64;
case AMDGPU::S_CMP_EQ_F32: return AMDGPU::V_CMP_EQ_F32_e64;
- case AMDGPU::S_CMP_LE_F32: {abort(); return AMDGPU::V_CMP_LE_F32_e64;}
- case AMDGPU::S_CMP_GT_F32: {abort(); return AMDGPU::V_CMP_GT_F32_e64;}
+ case AMDGPU::S_CMP_LE_F32: return AMDGPU::V_CMP_LE_F32_e64;
+ case AMDGPU::S_CMP_GT_F32: return AMDGPU::V_CMP_GT_F32_e64;
case AMDGPU::S_CMP_LG_F32: return AMDGPU::V_CMP_LG_F32_e64;
case AMDGPU::S_CMP_GE_F32: return AMDGPU::V_CMP_GE_F32_e64;
case AMDGPU::S_CMP_O_F32: return AMDGPU::V_CMP_O_F32_e64;
case AMDGPU::S_CMP_U_F32: return AMDGPU::V_CMP_U_F32_e64;
case AMDGPU::S_CMP_NGE_F32: return AMDGPU::V_CMP_NGE_F32_e64;
- case AMDGPU::S_CMP_NLG_F32: {abort(); return AMDGPU::V_CMP_NLG_F32_e64;}
+ case AMDGPU::S_CMP_NLG_F32: return AMDGPU::V_CMP_NLG_F32_e64;
case AMDGPU::S_CMP_NGT_F32: return AMDGPU::V_CMP_NGT_F32_e64;
- case AMDGPU::S_CMP_NLE_F32: {abort(); return AMDGPU::V_CMP_NLE_F32_e64;}
+ case AMDGPU::S_CMP_NLE_F32: return AMDGPU::V_CMP_NLE_F32_e64;
case AMDGPU::S_CMP_NEQ_F32: return AMDGPU::V_CMP_NEQ_F32_e64;
case AMDGPU::S_CMP_NLT_F32: return AMDGPU::V_CMP_NLT_F32_e64;
case AMDGPU::S_CMP_LT_F16:
>From 736cf342ae3c55b70ef2ca9195afe771f19b08ce Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Tue, 9 Jun 2026 03:21:21 -0500
Subject: [PATCH 06/11] [AMDGPU][NFC] Update autogenerated test checks
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 33 +++++++++------------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
index bf7d66d5d83c3..50cb6127041d6 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -9,9 +9,8 @@ define <8 x i1> @vector_f32_ole() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
-; CHECK-NEXT: v_mov_b32_e32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
@@ -56,8 +55,7 @@ define <4 x i1> @vector_f32_ogt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
@@ -87,24 +85,22 @@ define <32 x i1> @vector_f32_ueq() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
-; CHECK-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 32
-; CHECK-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v12, 48
-; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: v_mov_b32_e32 v13, 0
; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_mov_b32_e32 v16, 64
-; CHECK-NEXT: v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v20, 0x50
+; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, 0x60
+; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v28, 0x70
+; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-NEXT: s_clause 0x2
; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
-; CHECK-NEXT: v_mov_b32_e32 v29, 0
-; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
; CHECK-NEXT: s_wait_loadcnt 0x7
@@ -226,8 +222,7 @@ define <4 x i1> @vector_f32_ugt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
>From adc6f69d6b85a22c7ee0ad3c533dd2b0a1f24b98 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Tue, 9 Jun 2026 05:16:17 -0500
Subject: [PATCH 07/11] [AMDGPU][NFC] Added new tests to existing fcmp test
file
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 246 --------------
llvm/test/CodeGen/AMDGPU/fcmp.ll | 343 +++++++++++++++++++-
2 files changed, 336 insertions(+), 253 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
deleted file mode 100644
index 50cb6127041d6..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ /dev/null
@@ -1,246 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
-
-define <8 x i1> @vector_f32_ole() {
-; CHECK-LABEL: vector_f32_ole:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: s_wait_loadcnt 0x1
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <8 x float>, ptr addrspace(1) null, align 32
- %C = fcmp ole <8 x float> %LGV, zeroinitializer
- ret <8 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ogt() {
-; CHECK-LABEL: vector_f32_ogt:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ogt <4 x float> %LGV, zeroinitializer
- ret <4 x i1> %C
-}
-
-define <32 x i1> @vector_f32_ueq() {
-; CHECK-LABEL: vector_f32_ueq:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
-; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
-; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
-; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
-; CHECK-NEXT: s_clause 0x2
-; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
-; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
-; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
-; CHECK-NEXT: s_wait_loadcnt 0x7
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x6
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x5
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x4
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x3
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x2
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x1
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <32 x float>, ptr addrspace(1) null, align 128
- %C = fcmp ueq <32 x float> %LGV, zeroinitializer
- ret <32 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ugt() {
-; CHECK-LABEL: vector_f32_ugt:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
- ret <4 x i1> %C
-}
-
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.ll b/llvm/test/CodeGen/AMDGPU/fcmp.ll
index 5f6d5d22c61a9..ad03591ac084f 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.ll
@@ -1,9 +1,38 @@
-; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}fcmp_sext:
-; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck -check-prefix=CHECK-REDWOOD %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK-GFX1201 %s
define amdgpu_kernel void @fcmp_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; CHECK-REDWOOD-LABEL: fcmp_sext:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; CHECK-REDWOOD-NEXT: TEX 0 @6
+; CHECK-REDWOOD-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+; CHECK-REDWOOD-NEXT: Fetch clause starting at 6:
+; CHECK-REDWOOD-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; CHECK-REDWOOD-NEXT: ALU clause starting at 8:
+; CHECK-REDWOOD-NEXT: MOV * T0.X, KC0[2].Z,
+; CHECK-REDWOOD-NEXT: ALU clause starting at 9:
+; CHECK-REDWOOD-NEXT: SETE_DX10 T0.X, T0.X, T0.Y,
+; CHECK-REDWOOD-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; CHECK-GFX1201-LABEL: fcmp_sext:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: s_cmp_eq_f32 s2, s3
+; CHECK-GFX1201-NEXT: s_cselect_b32 s2, -1, 0
+; CHECK-GFX1201-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
+; CHECK-GFX1201-NEXT: global_store_b32 v0, v1, s[0:1]
+; CHECK-GFX1201-NEXT: s_endpgm
entry:
%0 = load float, ptr addrspace(1) %in
%arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %in, i32 1
@@ -18,11 +47,46 @@ entry:
; SET*_DX10 instruction. Previously we were lowering this to:
; SET* + FP_TO_SINT
-; CHECK: {{^}}fcmp_br:
-; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
-; CHECK-NEXT: {{[0-9]+\(5.0}}
define amdgpu_kernel void @fcmp_br(ptr addrspace(1) %out, float %in) {
+; CHECK-REDWOOD-LABEL: fcmp_br:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: ALU_PUSH_BEFORE 4, @8, KC0[CB0:0-32], KC1[]
+; CHECK-REDWOOD-NEXT: JUMP @5 POP:1
+; CHECK-REDWOOD-NEXT: ALU 3, @13, KC0[], KC1[]
+; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 0
+; CHECK-REDWOOD-NEXT: POP @5 POP:1
+; CHECK-REDWOOD-NEXT: ALU 1, @17, KC0[], KC1[]
+; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: ALU clause starting at 8:
+; CHECK-REDWOOD-NEXT: MOV T0.X, literal.x,
+; CHECK-REDWOOD-NEXT: MOV T0.W, KC0[2].Y,
+; CHECK-REDWOOD-NEXT: SETNE_DX10 * T1.W, KC0[2].Z, literal.y,
+; CHECK-REDWOOD-NEXT: 0(0.000000e+00), 1084227584(5.000000e+00)
+; CHECK-REDWOOD-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
+; CHECK-REDWOOD-NEXT: ALU clause starting at 13:
+; CHECK-REDWOOD-NEXT: ADD_INT * T1.W, T0.W, literal.x,
+; CHECK-REDWOOD-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; CHECK-REDWOOD-NEXT: LSHR * T1.X, PV.W, literal.x,
+; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; CHECK-REDWOOD-NEXT: ALU clause starting at 17:
+; CHECK-REDWOOD-NEXT: LSHR * T1.X, T0.W, literal.x,
+; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; CHECK-GFX1201-LABEL: fcmp_br:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: s_cmp_neq_f32 s2, 0x40a00000
+; CHECK-GFX1201-NEXT: s_cbranch_scc1 .LBB1_2
+; CHECK-GFX1201-NEXT: ; %bb.1: ; %IF
+; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GFX1201-NEXT: global_store_b32 v0, v0, s[0:1] offset:4
+; CHECK-GFX1201-NEXT: .LBB1_2: ; %ENDIF
+; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GFX1201-NEXT: global_store_b32 v0, v0, s[0:1]
+; CHECK-GFX1201-NEXT: s_endpgm
entry:
%0 = fcmp oeq float %in, 5.0
br i1 %0, label %IF, label %ENDIF
@@ -36,3 +100,268 @@ ENDIF:
store i32 0, ptr addrspace(1) %out
ret void
}
+
+
+define <8 x i1> @vector_f32_ole() {
+; CHECK-REDWOOD-LABEL: vector_f32_ole:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ole:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-GFX1201-NEXT: s_clause 0x1
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x1
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <8 x float>, ptr addrspace(1) null, align 32
+ %C = fcmp ole <8 x float> %LGV, zeroinitializer
+ ret <8 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ogt() {
+; CHECK-REDWOOD-LABEL: vector_f32_ogt:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ogt:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ogt <4 x float> %LGV, zeroinitializer
+ ret <4 x i1> %C
+}
+
+define <32 x i1> @vector_f32_ueq() {
+; CHECK-REDWOOD-LABEL: vector_f32_ueq:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ueq:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-GFX1201-NEXT: s_clause 0x1
+; CHECK-GFX1201-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[8:11], v[8:9], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[12:15], v[12:13], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[16:19], v[16:17], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-GFX1201-NEXT: s_clause 0x2
+; CHECK-GFX1201-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[24:27], v[24:25], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[28:31], v[28:29], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x7
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x6
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x5
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x4
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x3
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x2
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x1
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <32 x float>, ptr addrspace(1) null, align 128
+ %C = fcmp ueq <32 x float> %LGV, zeroinitializer
+ ret <32 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ugt() {
+; CHECK-REDWOOD-LABEL: vector_f32_ugt:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ugt:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
+ ret <4 x i1> %C
+}
+
>From 2e7ec964bf51b1a00a521ce5b2e3642809ef3841 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Wed, 10 Jun 2026 05:25:10 -0500
Subject: [PATCH 08/11] Revert "[AMDGPU][NFC] Added new tests to existing fcmp
test file"
This reverts commit adc6f69d6b85a22c7ee0ad3c533dd2b0a1f24b98.
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 246 ++++++++++++++
llvm/test/CodeGen/AMDGPU/fcmp.ll | 343 +-------------------
2 files changed, 253 insertions(+), 336 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
new file mode 100644
index 0000000000000..50cb6127041d6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
+
+define <8 x i1> @vector_f32_ole() {
+; CHECK-LABEL: vector_f32_ole:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <8 x float>, ptr addrspace(1) null, align 32
+ %C = fcmp ole <8 x float> %LGV, zeroinitializer
+ ret <8 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ogt() {
+; CHECK-LABEL: vector_f32_ogt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ogt <4 x float> %LGV, zeroinitializer
+ ret <4 x i1> %C
+}
+
+define <32 x i1> @vector_f32_ueq() {
+; CHECK-LABEL: vector_f32_ueq:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
+; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
+; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
+; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-NEXT: s_clause 0x2
+; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
+; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
+; CHECK-NEXT: s_wait_loadcnt 0x7
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x6
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x5
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x4
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x3
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x2
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <32 x float>, ptr addrspace(1) null, align 128
+ %C = fcmp ueq <32 x float> %LGV, zeroinitializer
+ ret <32 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ugt() {
+; CHECK-LABEL: vector_f32_ugt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
+ ret <4 x i1> %C
+}
+
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.ll b/llvm/test/CodeGen/AMDGPU/fcmp.ll
index ad03591ac084f..5f6d5d22c61a9 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.ll
@@ -1,38 +1,9 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck -check-prefix=CHECK-REDWOOD %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK-GFX1201 %s
+; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: {{^}}fcmp_sext:
+; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define amdgpu_kernel void @fcmp_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
-; CHECK-REDWOOD-LABEL: fcmp_sext:
-; CHECK-REDWOOD: ; %bb.0: ; %entry
-; CHECK-REDWOOD-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
-; CHECK-REDWOOD-NEXT: TEX 0 @6
-; CHECK-REDWOOD-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
-; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
-; CHECK-REDWOOD-NEXT: CF_END
-; CHECK-REDWOOD-NEXT: PAD
-; CHECK-REDWOOD-NEXT: Fetch clause starting at 6:
-; CHECK-REDWOOD-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
-; CHECK-REDWOOD-NEXT: ALU clause starting at 8:
-; CHECK-REDWOOD-NEXT: MOV * T0.X, KC0[2].Z,
-; CHECK-REDWOOD-NEXT: ALU clause starting at 9:
-; CHECK-REDWOOD-NEXT: SETE_DX10 T0.X, T0.X, T0.Y,
-; CHECK-REDWOOD-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
-;
-; CHECK-GFX1201-LABEL: fcmp_sext:
-; CHECK-GFX1201: ; %bb.0: ; %entry
-; CHECK-GFX1201-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: s_cmp_eq_f32 s2, s3
-; CHECK-GFX1201-NEXT: s_cselect_b32 s2, -1, 0
-; CHECK-GFX1201-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
-; CHECK-GFX1201-NEXT: global_store_b32 v0, v1, s[0:1]
-; CHECK-GFX1201-NEXT: s_endpgm
entry:
%0 = load float, ptr addrspace(1) %in
%arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %in, i32 1
@@ -47,46 +18,11 @@ entry:
; SET*_DX10 instruction. Previously we were lowering this to:
; SET* + FP_TO_SINT
+; CHECK: {{^}}fcmp_br:
+; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
+; CHECK-NEXT: {{[0-9]+\(5.0}}
define amdgpu_kernel void @fcmp_br(ptr addrspace(1) %out, float %in) {
-; CHECK-REDWOOD-LABEL: fcmp_br:
-; CHECK-REDWOOD: ; %bb.0: ; %entry
-; CHECK-REDWOOD-NEXT: ALU_PUSH_BEFORE 4, @8, KC0[CB0:0-32], KC1[]
-; CHECK-REDWOOD-NEXT: JUMP @5 POP:1
-; CHECK-REDWOOD-NEXT: ALU 3, @13, KC0[], KC1[]
-; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 0
-; CHECK-REDWOOD-NEXT: POP @5 POP:1
-; CHECK-REDWOOD-NEXT: ALU 1, @17, KC0[], KC1[]
-; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
-; CHECK-REDWOOD-NEXT: CF_END
-; CHECK-REDWOOD-NEXT: ALU clause starting at 8:
-; CHECK-REDWOOD-NEXT: MOV T0.X, literal.x,
-; CHECK-REDWOOD-NEXT: MOV T0.W, KC0[2].Y,
-; CHECK-REDWOOD-NEXT: SETNE_DX10 * T1.W, KC0[2].Z, literal.y,
-; CHECK-REDWOOD-NEXT: 0(0.000000e+00), 1084227584(5.000000e+00)
-; CHECK-REDWOOD-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
-; CHECK-REDWOOD-NEXT: ALU clause starting at 13:
-; CHECK-REDWOOD-NEXT: ADD_INT * T1.W, T0.W, literal.x,
-; CHECK-REDWOOD-NEXT: 4(5.605194e-45), 0(0.000000e+00)
-; CHECK-REDWOOD-NEXT: LSHR * T1.X, PV.W, literal.x,
-; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
-; CHECK-REDWOOD-NEXT: ALU clause starting at 17:
-; CHECK-REDWOOD-NEXT: LSHR * T1.X, T0.W, literal.x,
-; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
-;
-; CHECK-GFX1201-LABEL: fcmp_br:
-; CHECK-GFX1201: ; %bb.0: ; %entry
-; CHECK-GFX1201-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: s_cmp_neq_f32 s2, 0x40a00000
-; CHECK-GFX1201-NEXT: s_cbranch_scc1 .LBB1_2
-; CHECK-GFX1201-NEXT: ; %bb.1: ; %IF
-; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-GFX1201-NEXT: global_store_b32 v0, v0, s[0:1] offset:4
-; CHECK-GFX1201-NEXT: .LBB1_2: ; %ENDIF
-; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-GFX1201-NEXT: global_store_b32 v0, v0, s[0:1]
-; CHECK-GFX1201-NEXT: s_endpgm
entry:
%0 = fcmp oeq float %in, 5.0
br i1 %0, label %IF, label %ENDIF
@@ -100,268 +36,3 @@ ENDIF:
store i32 0, ptr addrspace(1) %out
ret void
}
-
-
-define <8 x i1> @vector_f32_ole() {
-; CHECK-REDWOOD-LABEL: vector_f32_ole:
-; CHECK-REDWOOD: ; %bb.0: ; %entry
-; CHECK-REDWOOD-NEXT: CF_END
-; CHECK-REDWOOD-NEXT: PAD
-;
-; CHECK-GFX1201-LABEL: vector_f32_ole:
-; CHECK-GFX1201: ; %bb.0: ; %entry
-; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-GFX1201-NEXT: s_clause 0x1
-; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-GFX1201-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x1
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <8 x float>, ptr addrspace(1) null, align 32
- %C = fcmp ole <8 x float> %LGV, zeroinitializer
- ret <8 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ogt() {
-; CHECK-REDWOOD-LABEL: vector_f32_ogt:
-; CHECK-REDWOOD: ; %bb.0: ; %entry
-; CHECK-REDWOOD-NEXT: CF_END
-; CHECK-REDWOOD-NEXT: PAD
-;
-; CHECK-GFX1201-LABEL: vector_f32_ogt:
-; CHECK-GFX1201: ; %bb.0: ; %entry
-; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
-; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ogt <4 x float> %LGV, zeroinitializer
- ret <4 x i1> %C
-}
-
-define <32 x i1> @vector_f32_ueq() {
-; CHECK-REDWOOD-LABEL: vector_f32_ueq:
-; CHECK-REDWOOD: ; %bb.0: ; %entry
-; CHECK-REDWOOD-NEXT: CF_END
-; CHECK-REDWOOD-NEXT: PAD
-;
-; CHECK-GFX1201-LABEL: vector_f32_ueq:
-; CHECK-GFX1201: ; %bb.0: ; %entry
-; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
-; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
-; CHECK-GFX1201-NEXT: s_clause 0x1
-; CHECK-GFX1201-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-GFX1201-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
-; CHECK-GFX1201-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
-; CHECK-GFX1201-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
-; CHECK-GFX1201-NEXT: s_clause 0x2
-; CHECK-GFX1201-NEXT: global_load_b128 v[20:23], v[20:21], off
-; CHECK-GFX1201-NEXT: global_load_b128 v[24:27], v[24:25], off
-; CHECK-GFX1201-NEXT: global_load_b128 v[28:31], v[28:29], off
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x7
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x6
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x5
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x4
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x3
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x2
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x1
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <32 x float>, ptr addrspace(1) null, align 128
- %C = fcmp ueq <32 x float> %LGV, zeroinitializer
- ret <32 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ugt() {
-; CHECK-REDWOOD-LABEL: vector_f32_ugt:
-; CHECK-REDWOOD: ; %bb.0: ; %entry
-; CHECK-REDWOOD-NEXT: CF_END
-; CHECK-REDWOOD-NEXT: PAD
-;
-; CHECK-GFX1201-LABEL: vector_f32_ugt:
-; CHECK-GFX1201: ; %bb.0: ; %entry
-; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
-; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
-; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
-; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
-; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
- ret <4 x i1> %C
-}
-
>From 7b5f5e1d9456076c1a9f958dc5ae2cec655a6e57 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Wed, 10 Jun 2026 05:26:08 -0500
Subject: [PATCH 09/11] [AMDGPU][NFC] Remove new test file
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 246 --------------------
1 file changed, 246 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
deleted file mode 100644
index 50cb6127041d6..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ /dev/null
@@ -1,246 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
-
-define <8 x i1> @vector_f32_ole() {
-; CHECK-LABEL: vector_f32_ole:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: s_wait_loadcnt 0x1
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <8 x float>, ptr addrspace(1) null, align 32
- %C = fcmp ole <8 x float> %LGV, zeroinitializer
- ret <8 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ogt() {
-; CHECK-LABEL: vector_f32_ogt:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ogt <4 x float> %LGV, zeroinitializer
- ret <4 x i1> %C
-}
-
-define <32 x i1> @vector_f32_ueq() {
-; CHECK-LABEL: vector_f32_ueq:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
-; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
-; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
-; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
-; CHECK-NEXT: s_clause 0x2
-; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
-; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
-; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
-; CHECK-NEXT: s_wait_loadcnt 0x7
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x6
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x5
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x4
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x3
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x2
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x1
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <32 x float>, ptr addrspace(1) null, align 128
- %C = fcmp ueq <32 x float> %LGV, zeroinitializer
- ret <32 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ugt() {
-; CHECK-LABEL: vector_f32_ugt:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
- ret <4 x i1> %C
-}
-
>From cf5111973751e6bd75025aa100cea4f476869ec7 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Wed, 10 Jun 2026 05:31:20 -0500
Subject: [PATCH 10/11] [AMDGPU][NFC] Add tests in mir form to existing file
---
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir | 36 ++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
index fc82faa0d91a7..0499c38329e4d 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
@@ -249,5 +249,41 @@ body: |
S_CMP_EQ_U32 %2, 0, implicit-def $scc
%4:sreg_64 = S_CSELECT_B64 %3, 0, implicit $scc
...
+
+---
+name: cmp_f32_gt
+body: |
+ bb.0:
+ %29:vreg_128 = IMPLICIT_DEF
+ %10:sgpr_32 = COPY %29.sub0
+ S_CMP_GT_F32 0, %10, implicit-def $scc, implicit $mode
+...
+
+---
+name: cmp_f32_le
+body: |
+ bb.0:
+ %46:vreg_128 = IMPLICIT_DEF
+ %16:sgpr_32 = COPY %46.sub0
+ S_CMP_LE_F32 %16, 7, implicit-def $scc, implicit $mode
+...
+
+---
+name: cmp_f32_nlg
+body: |
+ bb.0:
+ %130:vreg_128 = IMPLICIT_DEF
+ %53:sgpr_32 = COPY %130.sub1
+ S_CMP_NLG_F32 %53, 1, implicit-def $scc, implicit $mode
+...
+
+---
+name: cmp_f32_nle
+body: |
+ bb.0:
+ %29:vreg_128 = IMPLICIT_DEF
+ %10:sgpr_32 = COPY %29.sub0
+ S_CMP_NLE_F32 0, %10, implicit-def $scc, implicit $mode
+...
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
# GCN: {{.*}}
>From ac7b426467a2758dff7597ec3cf9dc1a21572af7 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Wed, 10 Jun 2026 05:54:42 -0500
Subject: [PATCH 11/11] [AMDGPU][NFC] Re-generate test checks using
update_mir_test_checks.py
---
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir | 218 +++++++++++++++----
1 file changed, 173 insertions(+), 45 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
index 0499c38329e4d..34323cbd5b1cf 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
@@ -1,13 +1,20 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
-# GCN-LABEL: name: fix-sgpr-copies
-# GCN: V_ADD_CO_U32_e32
-# GCN: V_ADDC_U32_e32
---
name: fix-sgpr-copies
body: |
bb.0:
+ ; GCN-LABEL: name: fix-sgpr-copies
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[DEF2]], [[V_CVT_U32_F32_e64_]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF3]]
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF1]]
+ ; GCN-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 [[COPY]], [[COPY1]], implicit-def $vcc, implicit $vcc, implicit $exec
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:sreg_32 = IMPLICIT_DEF
@@ -20,13 +27,64 @@ body: |
# Test to ensure i1 phi copies from scalar registers through another phi won't
# be promoted into vector ones.
-# GCN-LABEL: name: fix-sgpr-i1-phi-copies
-# GCN: .8:
-# GCN-NOT: vreg_64 = PHI
---
name: fix-sgpr-i1-phi-copies
tracksRegLiveness: true
body: |
+ ; GCN-LABEL: name: fix-sgpr-i1-phi-copies
+ ; GCN: bb.0:
+ ; GCN-NEXT: successors: %bb.5(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: S_BRANCH %bb.5
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.1:
+ ; GCN-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_1 = COPY %2, implicit $exec
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.3, implicit undef $scc
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.2:
+ ; GCN-NEXT: successors: %bb.3(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:vreg_1 = IMPLICIT_DEF
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.3:
+ ; GCN-NEXT: successors: %bb.4(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_1 = PHI [[COPY]], %bb.1, [[DEF]], %bb.2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.4:
+ ; GCN-NEXT: successors: %bb.9(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[PHI1:%[0-9]+]]:vreg_1 = PHI %7, %bb.8, [[PHI]], %bb.3
+ ; GCN-NEXT: S_BRANCH %bb.9
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.5:
+ ; GCN-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.7, implicit undef $scc
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.6:
+ ; GCN-NEXT: successors: %bb.8(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
+ ; GCN-NEXT: S_BRANCH %bb.8
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.7:
+ ; GCN-NEXT: successors: %bb.8(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -1
+ ; GCN-NEXT: S_BRANCH %bb.8
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.8:
+ ; GCN-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[PHI2:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.6, [[S_MOV_B64_1]], %bb.7
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_1 = COPY [[PHI2]], implicit $exec
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.4, implicit undef $scc
+ ; GCN-NEXT: S_BRANCH %bb.1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.9:
bb.9:
S_BRANCH %bb.0
@@ -63,12 +121,30 @@ body: |
...
# Avoid infinite loop in SIInstrInfo::legalizeGenericOperand when checking for ImpDef.
-# GCN-LABEL: name: legalize-operand-search-each-def-once
-# GCN-NOT: sreg_64 PHI
+
---
name: legalize-operand-search-each-def-once
tracksRegLiveness: true
body: |
+ ; GCN-LABEL: name: legalize-operand-search-each-def-once
+ ; GCN: bb.0:
+ ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN-NEXT: liveins: $sgpr0_sgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]], implicit $exec
+ ; GCN-NEXT: S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
+ ; GCN-NEXT: S_BRANCH %bb.1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.1:
+ ; GCN-NEXT: successors: %bb.2(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GCN-NEXT: S_BRANCH %bb.2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.2:
+ ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY1]], %bb.0, [[DEF]], %bb.1
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[COPY]]
bb.0:
successors: %bb.1, %bb.2
liveins: $sgpr0_sgpr1
@@ -88,12 +164,31 @@ body: |
# A REG_SEQUENCE that uses registers defined by both a PHI and a COPY could
# result in an endless search.
-# GCN-LABEL: name: process-phi-search-each-use-once
-# GCN-NOT: sreg_32 PHI
+
---
name: process-phi-search-each-use-once
tracksRegLiveness: true
body: |
+ ; GCN-LABEL: name: process-phi-search-each-use-once
+ ; GCN: bb.0:
+ ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN-NEXT: liveins: $vgpr3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN-NEXT: S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
+ ; GCN-NEXT: S_BRANCH %bb.1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.1:
+ ; GCN-NEXT: successors: %bb.2(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; GCN-NEXT: S_BRANCH %bb.2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.2:
+ ; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[PHI]], %subreg.sub0, [[COPY]], %subreg.sub1
+ ; GCN-NEXT: $vgpr3 = COPY [[REG_SEQUENCE]].sub0
bb.0:
successors: %bb.1, %bb.2
liveins: $vgpr3
@@ -113,15 +208,19 @@ body: |
...
# Test to ensure that undef SCC gets properly propagated.
-# GCN-LABEL: name: scc_undef
-# GCN: S_CSELECT_B64 -1, 0, implicit undef $scc
-# GCN: V_CNDMASK
+
---
name: scc_undef
tracksRegLiveness: true
body: |
bb.0:
+ ; GCN-LABEL: name: scc_undef
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+ ; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit undef $scc
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_]]
+ ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[DEF]], 0, [[COPY]], [[S_CSELECT_B64_]], implicit $exec
%1:vgpr_32 = IMPLICIT_DEF
%2:sreg_32 = S_MOV_B32 1
%3:sreg_32 = COPY %1:vgpr_32
@@ -130,14 +229,16 @@ body: |
---
# Test that the VGPR immediate is replaced with an SGPR one.
-# GCN-LABEL: name: reg_sequence_vgpr_immediate
-# GCN: [[A_SGPR:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-# GCN-NEXT: [[VGPR_CONST:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 37
-# GCN-NEXT: [[SGPR_CONST:%[0-9]+]]:sgpr_32 = S_MOV_B32 37
-# GCN-NEXT: {{%[0-9]+}}:sreg_64 = REG_SEQUENCE [[SGPR_CONST]], %subreg.sub0, [[A_SGPR]], %subreg.sub1
+
name: reg_sequence_vgpr_immediate
body: |
bb.0:
+ ; GCN-LABEL: name: reg_sequence_vgpr_immediate
+ ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 37, implicit $exec
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 37
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
%0:sreg_32 = IMPLICIT_DEF
%1:vgpr_32 = V_MOV_B32_e32 37, implicit $exec
%2:sreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, %0:sreg_32, %subreg.sub1
@@ -146,29 +247,44 @@ body: |
...
---
-# GCN-LABEL: name: insert_subreg_vgpr_immediate
-# GCN: [[DST:%[0-9]+]]:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
-# GCN-NEXT: [[SGPR_CONST:%[0-9]+]]:sgpr_32 = S_MOV_B32 43
-# GCN-NEXT: {{%[0-9]+}}:sgpr_128 = INSERT_SUBREG [[DST]], [[SGPR_CONST]], %subreg.sub3
+
name: insert_subreg_vgpr_immediate
body: |
bb.0:
+ ; GCN-LABEL: name: insert_subreg_vgpr_immediate
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 43
+ ; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[REG_SEQUENCE]], [[S_MOV_B32_]], %subreg.sub3
%0:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
%1:vgpr_32 = V_MOV_B32_e32 43, implicit $exec
%2:sgpr_128 = INSERT_SUBREG %0, %1, %subreg.sub3
...
---
-# GCN-LABEL: name: phi_vgpr_immediate
-# GCN: bb.1:
-# GCN: [[SGPR:%[0-9]+]]:sgpr_32 = S_MOV_B32 51
-# GCN: bb.2:
-# GCN: IMPLICIT_DEF
-# GCN: bb.3:
-# GCN: sreg_32 = PHI [[SGPR]], %bb.1
+
name: phi_vgpr_immediate
tracksRegLiveness: true
body: |
+ ; GCN-LABEL: name: phi_vgpr_immediate
+ ; GCN: bb.0:
+ ; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.1:
+ ; GCN-NEXT: successors: %bb.3(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 51
+ ; GCN-NEXT: S_BRANCH %bb.3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.2:
+ ; GCN-NEXT: successors: %bb.3(0x80000000)
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: S_BRANCH %bb.3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: bb.3:
+ ; GCN-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.1, [[DEF]], %bb.2
bb.0:
S_CBRANCH_SCC1 %bb.2, implicit undef $scc
@@ -187,12 +303,6 @@ body: |
name: cmp_f32
body: |
bb.0:
- ; GCN-LABEL: name: cmp_f32
- ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: %6:sreg_64_xexec = nofpexcept V_CMP_LT_F32_e64 0, [[V_CVT_F32_U32_e64_]], 0, [[DEF1]], 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %6, implicit $exec
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec
@@ -213,7 +323,7 @@ body: |
; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]
- ; GCN-NEXT: %6:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[V_CVT_F32_U32_e64_]], 0, [[DEF1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+ ; GCN-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[V_CVT_F32_U32_e64_]], 0, [[DEF1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:sreg_32 = IMPLICIT_DEF
@@ -223,25 +333,27 @@ body: |
...
---
-# GCN-LABEL: name: moveimm_subreg_input
-# GCN: %0:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
-# GCN: :vgpr_32 = COPY %0.sub0
+
name: moveimm_subreg_input
body: |
bb.0:
+ ; GCN-LABEL: name: moveimm_subreg_input
+ ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B]].sub0
%0:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
%1:sreg_32 = COPY %0.sub0
...
---
-# GCN-LABEL: name: s_cselect_b64
-# GCN: %0:vgpr_32 = IMPLICIT_DEF
-# GCN: %1:vreg_64 = IMPLICIT_DEF
-# GCN: %7:sreg_64_xexec = V_CMP_EQ_U32_e64 %0, 0, implicit $exec
-# GCN: %6:vreg_64 = V_CNDMASK_B64_PSEUDO 0, %1, %7, implicit $exec
+
name: s_cselect_b64
body: |
bb.0:
+ ; GCN-LABEL: name: s_cselect_b64
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[DEF]], 0, implicit $exec
+ ; GCN-NEXT: [[V_CNDMA:%[0-9]+]]:vreg_64 = V_CNDMASK_B64_PSEUDO 0, [[DEF1]], [[V_CMP_EQ_U32_e64_]], implicit $exec
%0:vgpr_32 = IMPLICIT_DEF
%1:vreg_64 = IMPLICIT_DEF
%2:sreg_32 = COPY %0
@@ -254,6 +366,10 @@ body: |
name: cmp_f32_gt
body: |
bb.0:
+ ; GCN-LABEL: name: cmp_f32_gt
+ ; GCN: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
+ ; GCN-NEXT: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_F32_e64 0, 0, 0, [[COPY]], 0, implicit $mode, implicit $exec
%29:vreg_128 = IMPLICIT_DEF
%10:sgpr_32 = COPY %29.sub0
S_CMP_GT_F32 0, %10, implicit-def $scc, implicit $mode
@@ -263,6 +379,10 @@ body: |
name: cmp_f32_le
body: |
bb.0:
+ ; GCN-LABEL: name: cmp_f32_le
+ ; GCN: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
+ ; GCN-NEXT: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_F32_e64 0, [[COPY]], 0, 7, 0, implicit $mode, implicit $exec
%46:vreg_128 = IMPLICIT_DEF
%16:sgpr_32 = COPY %46.sub0
S_CMP_LE_F32 %16, 7, implicit-def $scc, implicit $mode
@@ -272,6 +392,10 @@ body: |
name: cmp_f32_nlg
body: |
bb.0:
+ ; GCN-LABEL: name: cmp_f32_nlg
+ ; GCN: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
+ ; GCN-NEXT: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NLG_F32_e64 0, [[COPY]], 0, 1, 0, implicit $mode, implicit $exec
%130:vreg_128 = IMPLICIT_DEF
%53:sgpr_32 = COPY %130.sub1
S_CMP_NLG_F32 %53, 1, implicit-def $scc, implicit $mode
@@ -281,6 +405,10 @@ body: |
name: cmp_f32_nle
body: |
bb.0:
+ ; GCN-LABEL: name: cmp_f32_nle
+ ; GCN: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
+ ; GCN-NEXT: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NLE_F32_e64 0, 0, 0, [[COPY]], 0, implicit $mode, implicit $exec
%29:vreg_128 = IMPLICIT_DEF
%10:sgpr_32 = COPY %29.sub0
S_CMP_NLE_F32 0, %10, implicit-def $scc, implicit $mode
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