[llvm] [Uniformity] Implement per-output machine uniformity analysis (PR #179275)

[Pankaj Dwivedi via llvm-commits]

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@@ -62,24 +82,51 @@ void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::initialize() {
     }
   }
 
-  const auto &InstrInfo = *F.getSubtarget().getInstrInfo();
+  const TargetInstrInfo &InstrInfo = *F.getSubtarget().getInstrInfo();
+  const MachineRegisterInfo &MRI = F.getRegInfo();
+  const RegisterBankInfo &RBI = *F.getSubtarget().getRegBankInfo();
+  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
 
   for (const MachineBasicBlock &MBB : F) {
     for (const MachineInstr &MI : MBB) {
-      ValueUniformity VU = InstrInfo.getValueUniformity(MI);
-
-      switch (VU) {
-      case ValueUniformity::AlwaysUniform:
-        addUniformOverride(MI);
-        break;
-      case ValueUniformity::NeverUniform:
-        markDivergent(MI);
-        break;
-      case ValueUniformity::Custom:
-        break;
-      case ValueUniformity::Default:
-        break;
+      // A terminator is a source of control divergence rather than a value;
+      // seed only the unconditionally divergent ones as divergent term blocks.
+      if (MI.isTerminator()) {
+        if (InstrInfo.isTerminatorDivergent(MI))
+          markDivergent(MI);
+        continue;
+      }
+
+      // Seed divergence per def, so an instruction with several outputs (e.g.
+      // inline asm) can mix uniform and divergent results.
+      unsigned DefIdx = 0;
+      bool HasDivergentDef = false;
+      for (const MachineOperand &Op : MI.all_defs()) {
+        Register Reg = Op.getReg();
+        if (!Reg.isVirtual()) {
+          ++DefIdx;
+          continue;
+        }
+        switch (InstrInfo.getValueUniformity(MI, DefIdx++)) {
+        case ValueUniformity::AlwaysUniform:
+          addUniformOverride(Reg);
+          break;
+        case ValueUniformity::NeverUniform:
+          // Inherently uniform registers (e.g. SGPRs) stay uniform even when
+          // the def is reported as a divergence source.
+          if (!TRI.isUniformReg(MRI, RBI, Reg))
+            HasDivergentDef |= markDivergent(Reg);
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PankajDwivedi-25 wrote:

After moving this part its no longer required.

https://github.com/llvm/llvm-project/pull/179275