[llvm] [AArch64] Reserve `W30_HI` and `[BHSDQ]31_HI` (PR #202929)

[Nathan Corbyn via llvm-commits]

https://github.com/cofibrant created https://github.com/llvm/llvm-project/pull/202929

The compiler currently doesn't reserve the artificial registers `W30_HI` or `[BHSDQ]31_HI` due to a family of off-by-one errors in `AArch64RegisterInfo.cpp`. This patch repairs this issue.

>From 2d0acd362c412733950c46fb5f0a07fd901298c2 Mon Sep 17 00:00:00 2001
From: Nathan Corbyn <n_corbyn at apple.com>
Date: Wed, 10 Jun 2026 11:55:58 +0100
Subject: [PATCH] [AArch64] Reserve W30_HI and [BHSDQ]31_HI

---
 .../Target/AArch64/AArch64RegisterInfo.cpp    | 12 +++----
 .../AArch64/AArch64RegisterInfoTest.cpp       | 32 +++++++++++++++++++
 2 files changed, 38 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 106676c67c94b..9e55b29426dd2 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -499,22 +499,22 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
   Reserved.set(AArch64::WZR_HI);
   static_assert(AArch64::W30_HI - AArch64::W0_HI == 30,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::W0_HI, AArch64::W30_HI);
+  Reserved.set(AArch64::W0_HI, AArch64::W30_HI + 1);
   static_assert(AArch64::B31_HI - AArch64::B0_HI == 31,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::B0_HI, AArch64::B31_HI);
+  Reserved.set(AArch64::B0_HI, AArch64::B31_HI + 1);
   static_assert(AArch64::H31_HI - AArch64::H0_HI == 31,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::H0_HI, AArch64::H31_HI);
+  Reserved.set(AArch64::H0_HI, AArch64::H31_HI + 1);
   static_assert(AArch64::S31_HI - AArch64::S0_HI == 31,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::S0_HI, AArch64::S31_HI);
+  Reserved.set(AArch64::S0_HI, AArch64::S31_HI + 1);
   static_assert(AArch64::D31_HI - AArch64::D0_HI == 31,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::D0_HI, AArch64::D31_HI);
+  Reserved.set(AArch64::D0_HI, AArch64::D31_HI + 1);
   static_assert(AArch64::Q31_HI - AArch64::Q0_HI == 31,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::Q0_HI, AArch64::Q31_HI);
+  Reserved.set(AArch64::Q0_HI, AArch64::Q31_HI + 1);
 
   return Reserved;
 }
diff --git a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
index 9efe97567331b..8b58098436375 100644
--- a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
@@ -149,4 +149,36 @@ TEST(AArch64LaneBitmasks, SubRegs) {
             AArch64::W1);
 }
 
+TEST(AArch64ReservedRegs, ArtificialHIRegistersAreReserved) {
+  std::unique_ptr<TargetMachine> TM = createTargetMachine("");
+  ASSERT_TRUE(TM);
+
+  std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
+  ASSERT_TRUE(II);
+
+  const AArch64RegisterInfo &TRI = II->getRegisterInfo();
+
+  // Create an empty machine function
+  LLVMContext Context;
+  Module M("", Context);
+  M.setDataLayout(TM->createDataLayout());
+  Function *F = Function::Create(
+      FunctionType::get(Type::getVoidTy(Context), /*isVarArg=*/false),
+      GlobalValue::ExternalLinkage, "f", &M);
+
+  MachineModuleInfo MMI(TM.get());
+  const TargetSubtargetInfo *STI = TM->getSubtargetImpl(*F);
+  MachineFunction MF(*F, *TM, *STI, MMI.getContext(), /*FunctionNum=*/0);
+  MF.initTargetMachineFunctionInfo(*STI);
+
+  BitVector Reserved = TRI.getReservedRegs(MF);
+
+  EXPECT_TRUE(Reserved.test(AArch64::W30_HI));
+  EXPECT_TRUE(Reserved.test(AArch64::B31_HI));
+  EXPECT_TRUE(Reserved.test(AArch64::H31_HI));
+  EXPECT_TRUE(Reserved.test(AArch64::S31_HI));
+  EXPECT_TRUE(Reserved.test(AArch64::D31_HI));
+  EXPECT_TRUE(Reserved.test(AArch64::Q31_HI));
+}
+
 } // namespace