[llvm] [AMDGPU] Adjust amdgpu fmax/fmin legalization (PR #202917)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 03:23:28 PDT 2026
https://github.com/Shoreshen created https://github.com/llvm/llvm-project/pull/202917
None
>From 103c553f00d7470dc7efec287f57544b644989c0 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Wed, 10 Jun 2026 18:22:13 +0800
Subject: [PATCH] adjust amdgpu fmax/fmin legalization
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 9 +-
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 20 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 53 +-
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 14 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 35 +-
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 23 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 109 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 117 +
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 +
.../AMDGPU/GlobalISel/atomicrmw_fmax.ll | 82 +-
.../AMDGPU/GlobalISel/atomicrmw_fmin.ll | 82 +-
.../GlobalISel/clamp-fmed3-const-combine.ll | 8 -
.../GlobalISel/fmed3-min-max-const-combine.ll | 18 -
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 48 +-
.../GlobalISel/llvm.amdgcn.rsq.clamp.ll | 9 +-
.../CodeGen/AMDGPU/atomics-system-scope.ll | 192 +-
.../buffer-fat-pointer-atomicrmw-fmax.ll | 288 +-
.../buffer-fat-pointer-atomicrmw-fmin.ll | 288 +-
llvm/test/CodeGen/AMDGPU/clamp.ll | 9 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 711 ++--
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 711 ++--
.../test/CodeGen/AMDGPU/flat-saddr-atomics.ll | 98 +-
llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll | 60 +-
llvm/test/CodeGen/AMDGPU/fmaxnum.ll | 634 +---
llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll | 60 +-
llvm/test/CodeGen/AMDGPU/fmin3.ll | 74 +-
llvm/test/CodeGen/AMDGPU/fminnum.ll | 595 +---
.../CodeGen/AMDGPU/global-atomicrmw-fmax.ll | 575 ++-
.../CodeGen/AMDGPU/global-atomicrmw-fmin.ll | 575 ++-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 96 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 96 +-
llvm/test/CodeGen/AMDGPU/maximumnum.ll | 3168 ++++-------------
llvm/test/CodeGen/AMDGPU/minimumnum.ll | 3054 ++++------------
llvm/test/CodeGen/AMDGPU/minmax.ll | 246 +-
.../CodeGen/AMDGPU/minmax3-tree-reduction.ll | 34 +-
.../CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll | 159 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 1065 ++----
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 1061 ++----
38 files changed, 4458 insertions(+), 10020 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index db375bc8803a1..26ce9e8d8e09a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -177,12 +177,13 @@ defm FmaMixBF16Insts : AMDGPUSubtargetFeature<"fma-mix-bf16-insts",
>;
defm IEEEMinimumMaximumInsts : AMDGPUSubtargetFeature<"ieee-minimum-maximum-insts",
- "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32 and"
- "v_pk_minimum/maximum_f16 instructions"
+ "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32,"
+ "v_pk_minmax/maxmin_num_f16, v_min/max_num_f16/f32/f64,"
+ "and v_pk_min/max_num_f16 instructions"
>;
defm SALUMinimumMaximumInsts : AMDGPUSubtargetFeature<"salu-minimum-maximum-insts",
- "Has s_minimum/maximum_f16/f32 instructions"
+ "Has s_minimum/maximum_f16/f32 and s_max/min_num_f16/f32 instructions"
>;
defm Minimum3Maximum3F32 : AMDGPUSubtargetFeature<"minimum3-maximum3-f32",
@@ -2075,7 +2076,6 @@ def FeatureISAVersion12 : FeatureSet<
FeatureFP8ConversionInsts,
FeatureWMMA128bInsts,
FeatureSWMMACGfx1200Insts,
- FeatureIEEEMinimumMaximumInsts,
FeaturePackedTID,
FeatureVcmpxPermlaneHazard,
FeatureSALUFloatInsts,
@@ -2287,7 +2287,6 @@ def FeatureISAVersion13 : FeatureSet<
FeatureGloballyAddressableScratch,
FeatureCvtPkF16F32Inst,
FeatureF16BF16ToFP6BF6ConversionScaleInsts,
- FeatureIEEEMinimumMaximumInsts,
FeatureSWakeupBarrier,
FeatureClusters,
FeatureCubeInsts,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 11d8aef61c858..f34dbfe4a5b46 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -249,6 +249,8 @@ def umin_oneuse : HasOneUseBinOp<umin>;
def fminnum_oneuse : HasOneUseBinOp<fminnum>;
def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>;
+def fminimumnum_oneuse : HasOneUseBinOp<fminimumnum>;
+def fmaximumnum_oneuse : HasOneUseBinOp<fmaximumnum>;
def fminimum_oneuse : HasOneUseBinOp<fminimum>;
def fmaximum_oneuse : HasOneUseBinOp<fmaximum>;
@@ -847,13 +849,15 @@ class RcpPat<Instruction RcpInst, ValueType vt> : AMDGPUPat <
// Instructions which select to the same v_min_f*
def fminnum_like : PatFrags<(ops node:$src0, node:$src1),
[(fminnum_ieee node:$src0, node:$src1),
- (fminnum node:$src0, node:$src1)]
+ (fminnum node:$src0, node:$src1),
+ (fminimumnum node:$src0, node:$src1)]
>;
// Instructions which select to the same v_max_f*
def fmaxnum_like : PatFrags<(ops node:$src0, node:$src1),
[(fmaxnum_ieee node:$src0, node:$src1),
- (fmaxnum node:$src0, node:$src1)]
+ (fmaxnum node:$src0, node:$src1),
+ (fmaximumnum node:$src0, node:$src1)]
>;
class NeverNaNPats<dag ops, list<dag> frags> : PatFrags<ops, frags> {
@@ -867,22 +871,26 @@ class NeverNaNPats<dag ops, list<dag> frags> : PatFrags<ops, frags> {
def fminnum_like_nnan : NeverNaNPats<(ops node:$src0, node:$src1),
[(fminnum_ieee node:$src0, node:$src1),
- (fminnum node:$src0, node:$src1)]
+ (fminnum node:$src0, node:$src1),
+ (fminimumnum node:$src0, node:$src1)]
>;
def fmaxnum_like_nnan : NeverNaNPats<(ops node:$src0, node:$src1),
[(fmaxnum_ieee node:$src0, node:$src1),
- (fmaxnum node:$src0, node:$src1)]
+ (fmaxnum node:$src0, node:$src1),
+ (fmaximumnum node:$src0, node:$src1)]
>;
def fminnum_like_oneuse : PatFrags<(ops node:$src0, node:$src1),
[(fminnum_ieee_oneuse node:$src0, node:$src1),
- (fminnum_oneuse node:$src0, node:$src1)]
+ (fminnum_oneuse node:$src0, node:$src1),
+ (fminimumnum_oneuse node:$src0, node:$src1)]
>;
def fmaxnum_like_oneuse : PatFrags<(ops node:$src0, node:$src1),
[(fmaxnum_ieee_oneuse node:$src0, node:$src1),
- (fmaxnum_oneuse node:$src0, node:$src1)]
+ (fmaxnum_oneuse node:$src0, node:$src1),
+ (fmaximumnum_oneuse node:$src0, node:$src1)]
>;
def any_fmad : PatFrags<(ops node:$src0, node:$src1, node:$src2),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index e341392ae068a..40896d3af7580 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -983,38 +983,40 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
auto &MinNumMaxNumIeee =
getActionDefinitionsBuilder({G_FMINNUM_IEEE, G_FMAXNUM_IEEE});
+ auto &MinNumMaxNum = getActionDefinitionsBuilder(
+ {G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM});
+ bool HasMinnumMaxnum =
+ ST.hasIEEEMinimumMaximumInsts() || ST.hasSALUMinimumMaximumInsts();
if (ST.hasVOP3PInsts()) {
- MinNumMaxNumIeee.legalFor(FPTypesPK16)
+ MinNumMaxNumIeee.legalFor(!HasMinnumMaxnum, FPTypesPK16)
+ .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
+ .clampMaxNumElements(0, S16, 2)
+ .clampScalar(0, S16, S64)
+ .scalarize(0);
+
+ MinNumMaxNum.legalFor(HasMinnumMaxnum, FPTypesPK16)
+ .customFor(!HasMinnumMaxnum, FPTypesPK16)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
.clampMaxNumElements(0, S16, 2)
.clampScalar(0, S16, S64)
.scalarize(0);
} else if (ST.has16BitInsts()) {
- MinNumMaxNumIeee.legalFor(FPTypes16).clampScalar(0, S16, S64).scalarize(0);
+ MinNumMaxNumIeee.legalFor(!HasMinnumMaxnum, FPTypes16)
+ .clampScalar(0, S16, S64)
+ .scalarize(0);
+ MinNumMaxNum.legalFor(HasMinnumMaxnum, FPTypes16)
+ .customFor(!HasMinnumMaxnum, FPTypes16)
+ .clampScalar(0, S16, S64)
+ .scalarize(0);
} else {
- MinNumMaxNumIeee.legalFor(FPTypesBase)
+ MinNumMaxNumIeee.legalFor(!HasMinnumMaxnum, FPTypesBase)
+ .clampScalar(0, S32, S64)
+ .scalarize(0);
+ MinNumMaxNum.legalFor(HasMinnumMaxnum, FPTypesBase)
+ .customFor(!HasMinnumMaxnum, FPTypesBase)
.clampScalar(0, S32, S64)
.scalarize(0);
- }
-
- auto &MinNumMaxNum = getActionDefinitionsBuilder(
- {G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM});
-
- if (ST.hasVOP3PInsts()) {
- MinNumMaxNum.customFor(FPTypesPK16)
- .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampScalar(0, S16, S64)
- .scalarize(0);
- } else if (ST.has16BitInsts()) {
- MinNumMaxNum.customFor(FPTypes16)
- .clampScalar(0, S16, S64)
- .scalarize(0);
- } else {
- MinNumMaxNum.customFor(FPTypesBase)
- .clampScalar(0, S32, S64)
- .scalarize(0);
}
if (ST.hasVOP3PInsts())
@@ -4336,7 +4338,8 @@ bool AMDGPULegalizerInfo::legalizeFFloor(MachineInstr &MI,
// We don't need to concern ourselves with the snan handling difference, so
// use the one which will directly select.
const SIMachineFunctionInfo *MFI = B.getMF().getInfo<SIMachineFunctionInfo>();
- if (MFI->getMode().IEEE)
+ if (MFI->getMode().IEEE && !ST.hasIEEEMinimumMaximumInsts() &&
+ !ST.hasSALUMinimumMaximumInsts())
B.buildFMinNumIEEE(Min, Fract, Const, Flags);
else
B.buildFMinNum(Min, Fract, Const, Flags);
@@ -6133,7 +6136,9 @@ bool AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(MachineInstr &MI,
// We don't need to concern ourselves with the snan handling difference, since
// the rsq quieted (or not) so use the one which will directly select.
const SIMachineFunctionInfo *MFI = B.getMF().getInfo<SIMachineFunctionInfo>();
- const bool UseIEEE = MFI->getMode().IEEE;
+ const bool UseIEEE = MFI->getMode().IEEE &&
+ !ST.hasIEEEMinimumMaximumInsts() &&
+ !ST.hasSALUMinimumMaximumInsts();
auto MaxFlt = B.buildFConstant(Ty, APFloat::getLargest(*FltSemantics));
auto ClampMax = UseIEEE ? B.buildFMinNumIEEE(Ty, Rsq, MaxFlt, Flags) :
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 74184333e5b69..2eb9fecffcbbd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -108,6 +108,8 @@ class AMDGPURegBankCombinerImpl : public Combiner {
bool getIEEE() const;
bool getDX10Clamp() const;
bool isFminnumIeee(const MachineInstr &MI) const;
+ bool isFminnum(const MachineInstr &MI) const;
+ bool isFminnumLike(const MachineInstr &MI) const;
bool isFCst(MachineInstr *MI) const;
bool isClampZeroToOne(MachineInstr *K0, MachineInstr *K1) const;
@@ -275,7 +277,7 @@ bool AMDGPURegBankCombinerImpl::matchFPMinMaxToMed3(
// nodes(max/min) have same behavior when one input is NaN and other isn't.
// Don't consider max(min(SNaN, K1), K0) since there is no isKnownNeverQNaN,
// also post-legalizer inputs to min/max are fcanonicalized (never SNaN).
- if ((getIEEE() && isFminnumIeee(MI)) || VT->isKnownNeverNaN(Dst)) {
+ if ((getIEEE() && isFminnumLike(MI)) || VT->isKnownNeverNaN(Dst)) {
// Don't fold single use constant that can't be inlined.
if ((!MRI.hasOneNonDBGUse(K0->VReg) || TII.isInlineConstant(K0->Value)) &&
(!MRI.hasOneNonDBGUse(K1->VReg) || TII.isInlineConstant(K1->Value))) {
@@ -304,7 +306,7 @@ bool AMDGPURegBankCombinerImpl::matchFPMinMaxToClamp(MachineInstr &MI,
// no NaN inputs. Most often MI is marked with nnan fast math flag.
// For IEEE=true consider NaN inputs. Only min(max(QNaN, 0.0), 1.0) evaluates
// to 0.0 requires dx10_clamp = true.
- if ((getIEEE() && getDX10Clamp() && isFminnumIeee(MI) &&
+ if ((getIEEE() && getDX10Clamp() && isFminnumLike(MI) &&
VT->isKnownNeverSNaN(Val)) ||
VT->isKnownNeverNaN(MI.getOperand(0).getReg())) {
Reg = Val;
@@ -587,6 +589,14 @@ bool AMDGPURegBankCombinerImpl::isFminnumIeee(const MachineInstr &MI) const {
return MI.getOpcode() == AMDGPU::G_FMINNUM_IEEE;
}
+bool AMDGPURegBankCombinerImpl::isFminnum(const MachineInstr &MI) const {
+ return MI.getOpcode() == AMDGPU::G_FMINNUM;
+}
+
+bool AMDGPURegBankCombinerImpl::isFminnumLike(const MachineInstr &MI) const {
+ return isFminnumIeee(MI) || isFminnum(MI);
+}
+
bool AMDGPURegBankCombinerImpl::isFCst(MachineInstr *MI) const {
return MI->getOpcode() == AMDGPU::G_FCONSTANT;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index f23524ee1fc6b..7d62ce2d63585 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -16,6 +16,7 @@
#include "AMDGPURegBankLegalizeRules.h"
#include "AMDGPUInstrInfo.h"
#include "GCNSubtarget.h"
+#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
@@ -1546,9 +1547,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
- addRulesForGOpcs({G_FMINNUM_IEEE, G_FMAXNUM_IEEE, G_FMINNUM, G_FMAXNUM,
- G_FMINIMUMNUM, G_FMAXIMUMNUM},
- Standard)
+ // FMINNUM_IEEE/FMAXNUM_IEEE select to the IEEE scalar min/max (e.g.
+ // s_min_f32/s_max_f32), which is available whenever the target has the SALU
+ // float instructions, so a uniform value may map to SGPR.
+ addRulesForGOpcs({G_FMINNUM_IEEE, G_FMAXNUM_IEEE}, Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
@@ -1560,6 +1562,33 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
+ auto ScalarNumIsSafe = [=](const MachineInstr &MI) {
+ const SIMachineFunctionInfo *MFI =
+ MI.getMF()->getInfo<SIMachineFunctionInfo>();
+ return hasSALUFloat && (!MFI->getMode().IEEE || hasSALUMinimumMaximumInsts);
+ };
+ auto ScalarNumIsNotSafe = [=](const MachineInstr &MI) {
+ return !ScalarNumIsSafe(MI);
+ };
+
+ // The _num_ min/max can use the mode-dependent scalar min/max outside IEEE
+ // mode. In IEEE mode, they only have a scalar form (e.g. s_max_num_f32) when
+ // the target has the SALU min/max-num instructions. Otherwise a uniform value
+ // must use the self-canonicalizing vector v_*_num form.
+ addRulesForGOpcs({G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM},
+ NoFastRules)
+ .Any({{DivS16}, {{Vgpr16}, {Vgpr16, Vgpr16}}})
+ .Any({{DivS32}, {{Vgpr32}, {Vgpr32, Vgpr32}}})
+ .Any({{UniS64}, {{UniInVgprS64}, {Vgpr64, Vgpr64}}})
+ .Any({{DivS64}, {{Vgpr64}, {Vgpr64, Vgpr64}}})
+ .Any({{UniV2S16}, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}}})
+ .Any({{DivV2S16}, {{VgprV2S16}, {VgprV2S16, VgprV2S16}}})
+ .Any({{{UniS16}, ScalarNumIsSafe}, {{Sgpr16}, {Sgpr16, Sgpr16}}})
+ .Any({{{UniS16}, ScalarNumIsNotSafe}, {{UniInVgprS16}, {Vgpr16, Vgpr16}}})
+ .Any({{{UniS32}, ScalarNumIsSafe}, {{Sgpr32}, {Sgpr32, Sgpr32}}})
+ .Any(
+ {{{UniS32}, ScalarNumIsNotSafe}, {{UniInVgprS32}, {Vgpr32, Vgpr32}}});
+
addRulesForGOpcs({G_FPTRUNC})
.Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
.Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index cc1f2d0664484..9967592950683 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4085,10 +4085,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_FFLOOR:
case AMDGPU::G_FCEIL:
case AMDGPU::G_INTRINSIC_ROUNDEVEN:
- case AMDGPU::G_FMINNUM:
- case AMDGPU::G_FMAXNUM:
- case AMDGPU::G_FMINIMUMNUM:
- case AMDGPU::G_FMAXIMUMNUM:
case AMDGPU::G_INTRINSIC_TRUNC:
case AMDGPU::G_STRICT_FADD:
case AMDGPU::G_STRICT_FSUB:
@@ -4101,6 +4097,25 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
return getDefaultMappingSOP(MI);
return getDefaultMappingVOP(MI);
}
+ case AMDGPU::G_FMINNUM:
+ case AMDGPU::G_FMAXNUM:
+ case AMDGPU::G_FMINIMUMNUM:
+ case AMDGPU::G_FMAXIMUMNUM: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ unsigned Size = Ty.getSizeInBits();
+ // Outside IEEE mode the mode-dependent scalar min/max (e.g. s_max_f32) has
+ // the correct numeric behavior, so a uniform op can map to SGPR. In IEEE
+ // mode those scalar ops would require explicit input canonicalization, so
+ // only map to SGPR when a scalar _num_ min/max (e.g. s_max_num_f32) exists;
+ // otherwise force VGPR to use the self-canonicalizing v_*_num_f* form.
+ const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+ bool ScalarNumIsSafe =
+ !MFI->getMode().IEEE || Subtarget.hasSALUMinimumMaximumInsts();
+ if (Subtarget.hasSALUFloatInsts() && Ty.isScalar() &&
+ (Size == 32 || Size == 16) && isSALUMapping(MI) && ScalarNumIsSafe)
+ return getDefaultMappingSOP(MI);
+ return getDefaultMappingVOP(MI);
+ }
case AMDGPU::G_FMINIMUM:
case AMDGPU::G_FMAXIMUM: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a6dc58e6da263..ce776dba837f9 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -541,15 +541,35 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32},
Legal);
- setOperationAction(
- {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- {MVT::f32, MVT::f64}, Custom);
-
- // These are really only legal for ieee_mode functions. We should be avoiding
- // them for functions that don't have ieee_mode enabled, so just say they are
- // legal.
- setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE},
- {MVT::f32, MVT::f64}, Legal);
+ // Do not have s_{min|max}_*f64 instruction f64 will only be lowered to
+ // v_{min|max}_*f64
+ if (Subtarget->hasIEEEMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f64, Legal);
+ } else {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f64, Custom);
+ // These are really only legal for ieee_mode functions. We should be
+ // avoiding them for functions that don't have ieee_mode enabled, so just
+ // say they are legal.
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, MVT::f64, Legal);
+ }
+
+ // If has v_{min|max}_num_f32 but no s_{min|max}_num_f32, leave it for custom
+ // function
+ if (Subtarget->hasIEEEMinimumMaximumInsts() &&
+ Subtarget->hasSALUMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f32, Legal);
+ } else {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f32, Custom);
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, MVT::f32, Legal);
+ }
if (Subtarget->haveRoundOpsF64())
setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FROUNDEVEN}, MVT::f64,
@@ -818,20 +838,32 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
MVT::v8f16, MVT::v8bf16, MVT::v16f16, MVT::v16bf16,
MVT::v32f16, MVT::v32bf16},
Custom);
+ if (Subtarget->hasIEEEMinimumMaximumInsts() &&
+ Subtarget->hasSALUMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f16, Legal);
- setOperationAction(
- {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- MVT::f16, Custom);
- setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16, Legal);
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16}, Custom);
+ } else {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::f16, Custom);
- setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, ISD::FMINIMUMNUM,
- ISD::FMAXIMUMNUM},
- {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
- Custom);
+ setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16,
+ Legal);
- setOperationAction({ISD::FMINNUM, ISD::FMAXNUM},
- {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
- Expand);
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
+ ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
+ Custom);
+
+ setOperationAction({ISD::FMINNUM, ISD::FMAXNUM},
+ {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
+ Expand);
+ }
for (MVT Vec16 :
{MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16,
@@ -850,7 +882,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
MVT::v2i16, Legal);
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG, ISD::FABS,
- ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
ISD::FCANONICALIZE},
MVT::v2f16, Legal);
@@ -877,23 +908,33 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
ISD::FCANONICALIZE},
VT, Custom);
- setOperationAction(
- {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
- {MVT::v2f16, MVT::v4f16}, Custom);
+ if (Subtarget->hasIEEEMinimumMaximumInsts()) {
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ MVT::v2f16, Legal);
+ } else {
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, MVT::v2f16,
+ Legal);
+ setOperationAction(
+ {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
+ {MVT::v2f16, MVT::v4f16}, Custom);
+ }
setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16, MVT::v4bf16},
Custom);
if (Subtarget->hasBF16PackedInsts()) {
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMAXNUM, ISD::FMINNUM,
- ISD::FMA, ISD::FNEG, ISD::FABS, ISD::FCANONICALIZE},
+ ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM, ISD::FMA,
+ ISD::FNEG, ISD::FABS, ISD::FCANONICALIZE},
MVT::v2bf16, Legal);
for (MVT VT : {MVT::v4bf16, MVT::v8bf16, MVT::v16bf16, MVT::v32bf16})
// Split vector operations.
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE,
- ISD::FNEG, ISD::FABS},
+ ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM,
+ ISD::FMAXIMUMNUM, ISD::FNEG, ISD::FABS},
VT, Custom);
}
@@ -8682,16 +8723,20 @@ SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
const MachineFunction &MF = DAG.getMachineFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
bool IsIEEEMode = Info->getMode().IEEE;
+ bool IsDivergent = Op.getNode()->isDivergent();
+ bool NeedExpand = (IsDivergent && !Subtarget->hasIEEEMinimumMaximumInsts()) ||
+ (!IsDivergent && !Subtarget->hasSALUMinimumMaximumInsts());
// FIXME: Assert during selection that this is only selected for
// ieee_mode. Currently a combine can produce the ieee version for non-ieee
// mode functions, but this happens to be OK since it's only done in cases
// where there is known no sNaN.
- if (IsIEEEMode)
+ if (IsIEEEMode && NeedExpand)
return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
- VT == MVT::v16bf16)
+ VT == MVT::v32f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16 ||
+ VT == MVT::v16bf16 || VT == MVT::v32bf16)
return splitBinaryVectorOp(Op, DAG);
return Op;
}
@@ -8703,12 +8748,16 @@ SITargetLowering::lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op,
const MachineFunction &MF = DAG.getMachineFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
bool IsIEEEMode = Info->getMode().IEEE;
+ bool IsDivergent = Op.getNode()->isDivergent();
+ bool NeedExpand = (IsDivergent && !Subtarget->hasIEEEMinimumMaximumInsts()) ||
+ (!IsDivergent && !Subtarget->hasSALUMinimumMaximumInsts());
- if (IsIEEEMode)
+ if (IsIEEEMode && NeedExpand)
return expandFMINIMUMNUM_FMAXIMUMNUM(Op.getNode(), DAG);
if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
- VT == MVT::v16bf16)
+ VT == MVT::v32f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16 ||
+ VT == MVT::v16bf16 || VT == MVT::v32bf16)
return splitBinaryVectorOp(Op, DAG);
return Op;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index b4fa13c8ebae3..ae00c4d0c4919 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8693,6 +8693,8 @@ void SIInstrInfo::moveToVALUImpl(
}
fixImplicitOperands(*NewInstr);
+ removeFcanonicalize(*NewInstr);
+
legalizeOperandsVALUt16(*NewInstr, MRI);
// Legalize the operands
@@ -10322,6 +10324,121 @@ void SIInstrInfo::fixImplicitOperands(MachineInstr &MI) const {
}
}
+// fcanonicalize is selected as a self-max (SelectCanonicalizeAsMax), i.e.
+// V_MAX_F{16,32} src, src, so only these max opcodes can define a canonicalize.
+static bool isFPSelfMaxCanonicalizeOpc(unsigned Opc) {
+ switch (Opc) {
+ case AMDGPU::V_MAX_F16_e32:
+ case AMDGPU::V_MAX_F16_e64:
+ case AMDGPU::V_MAX_F16_t16_e32:
+ case AMDGPU::V_MAX_F16_t16_e64:
+ case AMDGPU::V_MAX_F16_fake16_e32:
+ case AMDGPU::V_MAX_F16_fake16_e64:
+ case AMDGPU::V_MAX_F32_e32:
+ case AMDGPU::V_MAX_F32_e64:
+ return true;
+ default:
+ return false;
+ }
+}
+
+// VALU FP min/max (f16/f32). On FeatureIEEEMinimumMaximumInsts targets these
+// print as v_{min,max}_num_f*, which canonicalize their inputs internally.
+static bool isFPMinMaxNumOpc(unsigned Opc) {
+ switch (Opc) {
+ case AMDGPU::V_MIN_F16_e32:
+ case AMDGPU::V_MIN_F16_e64:
+ case AMDGPU::V_MIN_F16_t16_e32:
+ case AMDGPU::V_MIN_F16_t16_e64:
+ case AMDGPU::V_MIN_F16_fake16_e32:
+ case AMDGPU::V_MIN_F16_fake16_e64:
+ case AMDGPU::V_MIN_F32_e32:
+ case AMDGPU::V_MIN_F32_e64:
+ return true;
+ default:
+ return isFPSelfMaxCanonicalizeOpc(Opc);
+ }
+}
+
+static bool isFPCanonicalizeSrcModifier(unsigned Mod) {
+ return !(Mod & ~(SISrcMods::NEG | SISrcMods::ABS));
+}
+
+/// On FeatureIEEEMinimumMaximumInsts targets a VALU FP min/max is printed as
+/// v_{min,max}_num_f*, which already canonicalizes its inputs, so feeding it an
+/// explicitly canonicalized operand is redundant.
+///
+/// A uniform llvm.minnum/maxnum on a target without scalar _num_ min/max is
+/// lowered to fcanonicalize(x)/fcanonicalize(y) feeding S_{MIN,MAX}_F*, where
+/// each fcanonicalize is selected as a self-max V_MAX_F*_e64 src_mods:src,
+/// src_mods:src. When SIFixSGPRCopies later moves that scalar op back to a
+/// VALU min/max, e.g.:
+///
+/// %10 = V_MAX_F32_e64 0, %9, 0, %9, 0, 0 ; fcanonicalize %9
+/// %11 = V_MAX_F32_e64 1, %8, 1, %8, 0, 0 ; fcanonicalize -%8
+/// %13 = COPY %11
+/// %14 = COPY %10
+/// %12 = S_MAX_F32 %13, %14 --> V_MAX_F32_e64 %10, %11
+///
+/// the self-max inputs become redundant once the user is a v_max_num, so fold
+/// them back to %9/-%8 and drop the now-dead canonicalizes.
+void SIInstrInfo::removeFcanonicalize(MachineInstr &MI) const {
+ if (!ST.hasIEEEMinimumMaximumInsts() || !isFPMinMaxNumOpc(MI.getOpcode()))
+ return;
+
+ MachineBasicBlock *MBB = MI.getParent();
+ if (!MBB)
+ return;
+ MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
+
+ SmallVector<MachineInstr *, 2> DefsToErase;
+ auto foldSelfMaxInput = [&](AMDGPU::OpName SrcName, AMDGPU::OpName ModsName) {
+ MachineOperand *Src = getNamedOperand(MI, SrcName);
+ MachineOperand *SrcMods = getNamedOperand(MI, ModsName);
+ if (!Src || !Src->isReg() || !SrcMods || !SrcMods->isImm() ||
+ SrcMods->getImm() != 0)
+ return;
+ Register SrcReg = Src->getReg();
+ if (!SrcReg.isVirtual() || !MRI.hasOneNonDBGUser(SrcReg))
+ return;
+
+ // Match a self-max canonicalize: V_MAX_F* src_mods:src, src_mods:src.
+ MachineInstr *Def = MRI.getVRegDef(SrcReg);
+ if (!Def || !isFPSelfMaxCanonicalizeOpc(Def->getOpcode()))
+ return;
+ MachineOperand *S0 = getNamedOperand(*Def, AMDGPU::OpName::src0);
+ MachineOperand *S1 = getNamedOperand(*Def, AMDGPU::OpName::src1);
+ if (!S0 || !S1 || !S0->isReg() || !S1->isReg() ||
+ S0->getReg() != S1->getReg() || S0->getSubReg() != S1->getSubReg())
+ return;
+
+ MachineOperand *S0Mods =
+ getNamedOperand(*Def, AMDGPU::OpName::src0_modifiers);
+ MachineOperand *S1Mods =
+ getNamedOperand(*Def, AMDGPU::OpName::src1_modifiers);
+ if (!S0Mods || !S1Mods || !S0Mods->isImm() || !S1Mods->isImm() ||
+ S0Mods->getImm() != S1Mods->getImm() ||
+ !isFPCanonicalizeSrcModifier(S0Mods->getImm()))
+ return;
+
+ Src->setReg(S0->getReg());
+ Src->setSubReg(S0->getSubReg());
+ Src->setIsUndef(S0->isUndef());
+ Src->setIsKill(false);
+ MRI.clearKillFlags(S0->getReg());
+ SrcMods->setImm(S0Mods->getImm());
+ if (!llvm::is_contained(DefsToErase, Def))
+ DefsToErase.push_back(Def);
+ };
+
+ foldSelfMaxInput(AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers);
+ foldSelfMaxInput(AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers);
+
+ for (MachineInstr *Def : DefsToErase)
+ if (MRI.use_nodbg_empty(Def->getOperand(0).getReg()))
+ Def->eraseFromParent();
+}
+
bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {
if (!isSMRD(MI))
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 93707db64990a..78b17c72396a5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1760,6 +1760,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
void fixImplicitOperands(MachineInstr &MI) const;
+ void removeFcanonicalize(MachineInstr &MI) const;
+
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
ArrayRef<unsigned> Ops, int FrameIndex,
MachineInstr *&CopyMI,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
index 1973dd8cb58ff..d705d6acd0e6b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
@@ -604,15 +604,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -760,21 +758,18 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB7_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1194,15 +1189,13 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1348,21 +1341,18 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1822,31 +1812,28 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: buffer_load_b64 v[2:3], v8, s[0:3], null offen
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
+; GFX12-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1
+; GFX12-NEXT: buffer_load_b64 v[0:1], v10, s[0:3], null offen
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s4, v2
-; GFX12-NEXT: v_readfirstlane_b32 s5, v3
+; GFX12-NEXT: v_readfirstlane_b32 s5, v1
+; GFX12-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-NEXT: v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2009,29 +1996,26 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v6, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
; GFX12-NEXT: buffer_load_b64 v[2:3], v6, s[0:3], null offen
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s4, v2
; GFX12-NEXT: v_readfirstlane_b32 s5, v3
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
+; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
+; GFX12-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[7:10], v6, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
index ea5a9b0d22a15..92f247797b247 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
@@ -604,15 +604,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -760,21 +758,18 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB7_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1194,15 +1189,13 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1348,21 +1341,18 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1822,31 +1812,28 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: buffer_load_b64 v[2:3], v8, s[0:3], null offen
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
+; GFX12-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1
+; GFX12-NEXT: buffer_load_b64 v[0:1], v10, s[0:3], null offen
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s4, v2
-; GFX12-NEXT: v_readfirstlane_b32 s5, v3
+; GFX12-NEXT: v_readfirstlane_b32 s5, v1
+; GFX12-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-NEXT: v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2009,29 +1996,26 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v6, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
; GFX12-NEXT: buffer_load_b64 v[2:3], v6, s[0:3], null offen
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s4, v2
; GFX12-NEXT: v_readfirstlane_b32 s5, v3
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
+; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
+; GFX12-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[7:10], v6, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
index 58aa951f73e2f..0cfebf52e3181 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
@@ -80,8 +80,6 @@ define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 {
; GFX1170-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -92,8 +90,6 @@ define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fmin = call float @llvm.minnum.f32(float %a, float 10.0)
@@ -204,8 +200,6 @@ define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false(float %a) #4 {
; GFX1170-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -216,8 +210,6 @@ define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false(float %a) #4 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fmin = call float @llvm.minnum.f32(float %a, float 10.0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
index 2056683315877..5ab7c915dd6ae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
@@ -92,8 +92,6 @@ define half @test_min_K1max_ValK0_f16(half %a) #0 {
; GFX1170-LABEL: test_min_K1max_ValK0_f16:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -104,8 +102,6 @@ define half @test_min_K1max_ValK0_f16(half %a) #0 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_med3_num_f16 v0.l, v0.l, 2.0, 4.0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -116,8 +112,6 @@ define half @test_min_K1max_ValK0_f16(half %a) #0 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%maxnum = call half @llvm.maxnum.f16(half %a, half 2.0)
@@ -608,8 +602,6 @@ define float @test_min_max_maybe_NaN_input_ieee_false(float %a) #1 {
; GFX1170-LABEL: test_min_max_maybe_NaN_input_ieee_false:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -620,8 +612,6 @@ define float @test_min_max_maybe_NaN_input_ieee_false(float %a) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%maxnum = call float @llvm.maxnum.f32(float %a, float 2.0)
@@ -647,8 +637,6 @@ define float @test_max_min_maybe_NaN_input_ieee_false(float %a) #1 {
; GFX1170-LABEL: test_max_min_maybe_NaN_input_ieee_false:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -659,8 +647,6 @@ define float @test_max_min_maybe_NaN_input_ieee_false(float %a) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%minnum = call float @llvm.minnum.f32(float %a, float 4.0)
@@ -687,8 +673,6 @@ define float @test_max_min_maybe_NaN_input_ieee_true(float %a) #0 {
; GFX1170-LABEL: test_max_min_maybe_NaN_input_ieee_true:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -699,8 +683,6 @@ define float @test_max_min_maybe_NaN_input_ieee_true(float %a) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%minnum = call float @llvm.minnum.f32(float %a, float 4.0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index a7cde45af2afe..251c54de9c12b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -18,9 +18,6 @@ define float @test_fmin3(float %a, float %b, float %c) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call float @llvm.minnum.f32(float %a, float %b)
@@ -45,19 +42,11 @@ define float @test_fmin3_inreg(float inreg %a, float inreg %b, float inreg %c) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-NEXT: v_max_num_f32_e64 v2, s2, s2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-NEXT: s_min_num_f32 s0, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
; GFX12-NEXT: s_min_num_f32 s0, s0, s2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call float @llvm.minnum.f32(float %a, float %b)
@@ -129,8 +118,6 @@ define float @test_fmin3_with_constants(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, 0x40e00000
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call float @llvm.minnum.f32(float %a, float %b)
@@ -154,11 +141,6 @@ define float @test_fmin3_with_constants_inreg(float inreg %a, float inreg %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-NEXT: s_min_num_f32 s0, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
@@ -236,9 +218,6 @@ define float @test_fmax3(float %a, float %b, float %c) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call float @llvm.maxnum.f32(float %a, float %b)
@@ -263,19 +242,11 @@ define float @test_fmax3_inreg(float inreg %a, float inreg %b, float inreg %c) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-NEXT: v_max_num_f32_e64 v2, s2, s2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-NEXT: s_max_num_f32 s0, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
; GFX12-NEXT: s_max_num_f32 s0, s0, s2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call float @llvm.maxnum.f32(float %a, float %b)
@@ -347,8 +318,6 @@ define float @test_fmax3_with_constants(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, 0x40e00000
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call float @llvm.maxnum.f32(float %a, float %b)
@@ -372,11 +341,6 @@ define float @test_fmax3_with_constants_inreg(float inreg %a, float inreg %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-NEXT: s_max_num_f32 s0, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
@@ -458,10 +422,6 @@ define <2 x float> @test_fmin3_v2f32(<2 x float> %a, <2 x float> %b, <2 x float>
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_min3_num_f32 v0, v0, v2, v4
; GFX12-NEXT: v_min3_num_f32 v1, v1, v3, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -491,10 +451,6 @@ define <2 x float> @test_fmax3_v2f32(<2 x float> %a, <2 x float> %b, <2 x float>
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max3_num_f32 v0, v0, v2, v4
; GFX12-NEXT: v_max3_num_f32 v1, v1, v3, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
index 39bc43af2462c..1a28051cbd251 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
@@ -201,12 +201,9 @@ define float @v_rsq_clamp_undef_f32() #0 {
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT: v_rsq_f32_e32 v0, s0
-; GFX1170-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
-; GFX1170-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-NEXT: s_min_f32 s0, s0, 0x7f7fffff
-; GFX1170-NEXT: s_max_f32 s0, s0, 0xff7fffff
-; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-NEXT: v_mov_b32_e32 v0, s0
+; GFX1170-NEXT: v_mov_b32_e32 v1, 0xff7fffff
+; GFX1170-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_rsq_clamp_undef_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll b/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
index d0e9b61cd8abd..6da8f03e53042 100644
--- a/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
@@ -845,42 +845,36 @@ define double @flat_system_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB38_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB38_4
-; GFX1250-NEXT: .LBB38_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB38_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_min_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB38_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_min_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB38_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB38_2
-; GFX1250-NEXT: .LBB38_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB38_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB38_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmin ptr %ptr, double %val monotonic
ret double %result
@@ -891,42 +885,36 @@ define double @flat_one_as_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB39_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB39_4
-; GFX1250-NEXT: .LBB39_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB39_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_min_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB39_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_min_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB39_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB39_2
-; GFX1250-NEXT: .LBB39_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB39_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB39_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmin ptr %ptr, double %val syncscope("one-as") monotonic
ret double %result
@@ -961,42 +949,36 @@ define double @flat_system_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB42_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB42_4
-; GFX1250-NEXT: .LBB42_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB42_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_max_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB42_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_max_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB42_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB42_2
-; GFX1250-NEXT: .LBB42_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB42_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB42_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmax ptr %ptr, double %val monotonic
ret double %result
@@ -1007,42 +989,36 @@ define double @flat_one_as_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
-; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1250-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v4
+; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1250-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB43_3
-; GFX1250-NEXT: ; %bb.1: ; %Flow
-; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execnz .LBB43_4
-; GFX1250-NEXT: .LBB43_2: ; %atomicrmw.phi
-; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-; GFX1250-NEXT: .LBB43_3: ; %atomicrmw.global
-; GFX1250-NEXT: flat_atomic_max_num_f64 v[0:1], v[4:5], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1250-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1250-NEXT: s_cbranch_execz .LBB43_2
+; GFX1250-NEXT: ; %bb.1: ; %atomicrmw.global
+; GFX1250-NEXT: flat_atomic_max_num_f64 v[4:5], v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX1250-NEXT: .LBB43_2: ; %Flow
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX1250-NEXT: s_cbranch_execz .LBB43_2
-; GFX1250-NEXT: .LBB43_4: ; %atomicrmw.private
-; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: s_cbranch_execz .LBB43_4
+; GFX1250-NEXT: ; %bb.3: ; %atomicrmw.private
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_subrev_nc_u32_e32 v0, src_flat_scratch_base_lo, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f64 v[2:3], v[2:3], v[2:3] :: v_dual_cndmask_b32 v6, -1, v0, vcc_lo
-; GFX1250-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX1250-NEXT: v_subrev_nc_u32_e32 v4, src_flat_scratch_base_lo, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
+; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
+; GFX1250-NEXT: .LBB43_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%result = atomicrmw fmax ptr %ptr, double %val syncscope("one-as") monotonic
ret double %result
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index 3d85bf7019426..bb4d388f169a0 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -1174,27 +1174,24 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1359,24 +1356,22 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
; GFX12-NEXT: v_mov_b32_e32 v6, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[2:3], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
-; GFX12-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[7:10], v6, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1560,17 +1555,15 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-NEXT: v_max_num_f64_e32 v[5:6], v[5:6], v[5:6]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB7_3: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Loop Header: Depth=1
; GFX12-NEXT: ; Child Loop BB7_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[13:14], v[13:14]
+; GFX12-NEXT: v_max_num_f64_e32 v[11:12], v[13:14], v[5:6]
; GFX12-NEXT: s_mov_b32 s2, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[11:12], v[0:1], v[5:6]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX12-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
@@ -1958,27 +1951,24 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2224,27 +2214,24 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2413,7 +2400,6 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2433,13 +2419,11 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2463,46 +2447,44 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], v4, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v3
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_grained_memory:
@@ -2868,7 +2850,6 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2888,13 +2869,11 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2917,39 +2896,37 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
@@ -3311,15 +3288,15 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-TRUE16-NEXT: s_mov_b32 s1, exec_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v9, 0xffff
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-TRUE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
@@ -3333,29 +3310,26 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_b32 v6, v10, s[4:7], null offen
+; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
; GFX12-TRUE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2:
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.l, v5.l
; GFX12-TRUE16-NEXT: s_mov_b32 s1, 0
; GFX12-TRUE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v9, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, 0
; GFX12-TRUE16-NEXT: s_mov_b32 s2, exec_lo
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v4.h, v4.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v9, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v11, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-TRUE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
@@ -3370,14 +3344,14 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[7:8], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
+; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-TRUE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v7, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3385,7 +3359,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v9, v7
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -3395,15 +3369,15 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s1, exec_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, -4, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v6, v7, 0xffff
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v9, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-FAKE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
@@ -3417,30 +3391,27 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
; GFX12-FAKE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2:
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v10, v5, v5
; GFX12-FAKE16-NEXT: s_mov_b32 s1, 0
; GFX12-FAKE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-FAKE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v7, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX12-FAKE16-NEXT: s_mov_b32 s2, exec_lo
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v10
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
+; GFX12-FAKE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
@@ -3455,14 +3426,14 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-FAKE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3470,7 +3441,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v7, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -6047,11 +6018,9 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s16
-; GFX12-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, s16
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v1, v1
; GFX12-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen offset:1024
; GFX12-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6059,9 +6028,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-NEXT: v_mov_b32_e32 v5, v0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX12-NEXT: v_pk_max_num_f16 v4, v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v2
; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -6353,23 +6320,22 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2f16__offset__amdgpu_no_fin
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v1, s16
-; GFX12-NEXT: v_pk_max_num_f16 v2, v0, v0
; GFX12-NEXT: v_mov_b32_e32 v3, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b32 v1, v1, s[0:3], null offen offset:1024
+; GFX12-NEXT: buffer_load_b32 v2, v1, s[0:3], null offen offset:1024
; GFX12-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v0, v1, v1
+; GFX12-NEXT: v_pk_max_num_f16 v1, v2, v0
+; GFX12-NEXT: v_mov_b32_e32 v5, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_mov_b32_e32 v4, v1
; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -6656,24 +6622,22 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
+; GFX12-NEXT: buffer_load_b32 v8, v4, s[4:7], null offen offset:1024
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-NEXT: v_pk_max_num_f16 v8, v5, v5
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_3: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Loop Header: Depth=1
; GFX12-NEXT: ; Child Loop BB18_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v5, v7, v7
+; GFX12-NEXT: v_pk_max_num_f16 v7, v8, v5
; GFX12-NEXT: s_mov_b32 s2, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v6, v5, v8
-; GFX12-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-NEXT: v_mov_b32_e32 v7, v8
; GFX12-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-NEXT: v_readfirstlane_b32 s4, v0
@@ -6688,14 +6652,14 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[6:7], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_4
; GFX12-NEXT: ; %bb.5: ; in Loop: Header=BB18_3 Depth=1
; GFX12-NEXT: s_mov_b32 exec_lo, s2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX12-NEXT: v_mov_b32_e32 v7, v5
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v6, v8
+; GFX12-NEXT: v_mov_b32_e32 v8, v6
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6703,7 +6667,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: v_mov_b32_e32 v0, v5
+; GFX12-NEXT: v_mov_b32_e32 v0, v6
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall__amdgpu_no_fine_grained_memory:
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 3f15d35320573..e425479b80081 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -1174,27 +1174,24 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1359,24 +1356,22 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
; GFX12-NEXT: v_mov_b32_e32 v6, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[2:3], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[0:1]
+; GFX12-NEXT: v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
-; GFX12-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[7:10], v6, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -1560,17 +1555,15 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-NEXT: v_max_num_f64_e32 v[5:6], v[5:6], v[5:6]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB7_3: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Loop Header: Depth=1
; GFX12-NEXT: ; Child Loop BB7_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[13:14], v[13:14]
+; GFX12-NEXT: v_min_num_f64_e32 v[11:12], v[13:14], v[5:6]
; GFX12-NEXT: s_mov_b32 s2, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[11:12], v[0:1], v[5:6]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX12-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
@@ -1958,27 +1951,24 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2224,27 +2214,24 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, s16
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
+; GFX12-NEXT: v_mov_b32_e32 v10, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b64 v[4:5], v2, s[0:3], null offen offset:2048
+; GFX12-NEXT: buffer_load_b64 v[8:9], v0, s[0:3], null offen offset:2048
; GFX12-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -2413,7 +2400,6 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2433,13 +2419,11 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2463,46 +2447,44 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], v4, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[3:4], v5, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v3
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_grained_memory:
@@ -2868,7 +2850,6 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2888,13 +2869,11 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2917,39 +2896,37 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
; GFX12-FAKE16-NEXT: s_mov_b32 s5, 0
; GFX12-FAKE16-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s4, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, s4, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
@@ -3311,15 +3288,15 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-TRUE16-NEXT: s_mov_b32 s1, exec_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v9, 0xffff
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-TRUE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
@@ -3333,29 +3310,26 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_b32 v6, v10, s[4:7], null offen
+; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
; GFX12-TRUE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2:
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.l, v5.l
; GFX12-TRUE16-NEXT: s_mov_b32 s1, 0
; GFX12-TRUE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v9, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, 0
; GFX12-TRUE16-NEXT: s_mov_b32 s2, exec_lo
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v4.h, v4.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v6.l, v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v9, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v11, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-TRUE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
@@ -3370,14 +3344,14 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[7:8], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
+; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-TRUE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v7, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3385,7 +3359,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v9, v7
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -3395,15 +3369,15 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x200, v4
+; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x200, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s1, exec_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 3, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, -4, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v10, -4, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v6, v7, 0xffff
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v9, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v11, v7
; GFX12-FAKE16-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
@@ -3417,30 +3391,27 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
+; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
; GFX12-FAKE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2:
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v10, v5, v5
; GFX12-FAKE16-NEXT: s_mov_b32 s1, 0
; GFX12-FAKE16-NEXT: .LBB12_3: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-FAKE16-NEXT: ; Child Loop BB12_4 Depth 2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v7, v6
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX12-FAKE16-NEXT: s_mov_b32 s2, exec_lo
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v4, v4, v10
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v6, v6, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, v4, v6
+; GFX12-FAKE16-NEXT: v_and_or_b32 v6, v7, v11, v6
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX12-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
@@ -3455,14 +3426,14 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
+; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_4
; GFX12-FAKE16-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v7
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3470,7 +3441,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v7, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v4, v8
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu_no_fine_grained_memory:
@@ -6047,11 +6018,9 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s16
-; GFX12-NEXT: v_mov_b32_e32 v3, s16
+; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, s16
+; GFX12-NEXT: v_mov_b32_e32 v0, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v1, v1
; GFX12-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen offset:1024
; GFX12-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6059,9 +6028,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-NEXT: v_mov_b32_e32 v5, v0
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX12-NEXT: v_pk_min_num_f16 v4, v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v4, v5, v2
; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -6353,23 +6320,22 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2f16__offset__amdgpu_no_fin
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v1, s16
-; GFX12-NEXT: v_pk_max_num_f16 v2, v0, v0
; GFX12-NEXT: v_mov_b32_e32 v3, s16
; GFX12-NEXT: s_mov_b32 s4, 0
-; GFX12-NEXT: buffer_load_b32 v1, v1, s[0:3], null offen offset:1024
+; GFX12-NEXT: buffer_load_b32 v2, v1, s[0:3], null offen offset:1024
; GFX12-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v0, v1, v1
+; GFX12-NEXT: v_pk_min_num_f16 v1, v2, v0
+; GFX12-NEXT: v_mov_b32_e32 v5, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_mov_b32_e32 v4, v1
; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
-; GFX12-NEXT: v_mov_b32_e32 v1, v4
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -6656,24 +6622,22 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
+; GFX12-NEXT: buffer_load_b32 v8, v4, s[4:7], null offen offset:1024
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-NEXT: v_pk_max_num_f16 v8, v5, v5
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_3: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Loop Header: Depth=1
; GFX12-NEXT: ; Child Loop BB18_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v5, v7, v7
+; GFX12-NEXT: v_pk_min_num_f16 v7, v8, v5
; GFX12-NEXT: s_mov_b32 s2, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v6, v5, v8
-; GFX12-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-NEXT: v_mov_b32_e32 v7, v8
; GFX12-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-NEXT: v_readfirstlane_b32 s4, v0
@@ -6688,14 +6652,14 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
+; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[6:7], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_4
; GFX12-NEXT: ; %bb.5: ; in Loop: Header=BB18_3 Depth=1
; GFX12-NEXT: s_mov_b32 exec_lo, s2
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
-; GFX12-NEXT: v_mov_b32_e32 v7, v5
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v6, v8
+; GFX12-NEXT: v_mov_b32_e32 v8, v6
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6703,7 +6667,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: v_mov_b32_e32 v0, v5
+; GFX12-NEXT: v_mov_b32_e32 v0, v6
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall__amdgpu_no_fine_grained_memory:
diff --git a/llvm/test/CodeGen/AMDGPU/clamp.ll b/llvm/test/CodeGen/AMDGPU/clamp.ll
index e566d6291624f..45a9abf4a595c 100644
--- a/llvm/test/CodeGen/AMDGPU/clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/clamp.ll
@@ -415,12 +415,11 @@ define amdgpu_kernel void @v_clamp_negzero_maybe_snan_f32(ptr addrspace(1) %out,
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: v_maxmin_num_f32 v1, v1, 0x80000000, 1.0
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
@@ -520,9 +519,7 @@ define amdgpu_kernel void @v_clamp_multi_use_max_f32(ptr addrspace(1) %out, ptr
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: v_max_num_f32_e32 v1, 0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v2, 1.0, v1
; GFX12-NEXT: global_store_b32 v0, v2, s[0:1]
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3267,9 +3264,7 @@ define amdgpu_kernel void @v_clamp_v2f16_not_zero(ptr addrspace(1) %out, ptr add
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 2.0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel_hi:[1,0]
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
@@ -3374,9 +3369,7 @@ define amdgpu_kernel void @v_clamp_v2f16_not_one(ptr addrspace(1) %out, ptr addr
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel:[0,1] op_sel_hi:[1,0]
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 4e3d7947bfbbd..f7dddd1b5a92b 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -2802,29 +2802,27 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2833,7 +2831,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB18_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -2842,16 +2840,14 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
@@ -3192,7 +3188,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3218,9 +3213,8 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3240,13 +3234,11 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3604,7 +3596,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3630,9 +3621,8 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3652,13 +3642,11 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4017,7 +4005,6 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4033,20 +4020,18 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB21_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4055,19 +4040,17 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4403,14 +4386,13 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4422,20 +4404,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4443,20 +4423,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4808,14 +4786,13 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4827,20 +4804,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4848,20 +4823,18 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5214,29 +5187,27 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5245,7 +5216,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB24_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5254,16 +5225,14 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
@@ -5638,29 +5607,27 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5669,7 +5636,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB25_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5678,16 +5645,14 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -6033,9 +5998,8 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6050,11 +6014,9 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6079,9 +6041,8 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6095,12 +6056,11 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6421,35 +6381,30 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6460,7 +6415,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -6473,15 +6428,13 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6489,12 +6442,11 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6827,35 +6779,30 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6866,7 +6813,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -6879,15 +6826,13 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6895,12 +6840,11 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7235,9 +7179,8 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7251,10 +7194,9 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7279,9 +7221,8 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7294,12 +7235,10 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7611,37 +7550,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7658,37 +7593,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8005,37 +7936,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8052,37 +7979,33 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8401,7 +8324,6 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8409,9 +8331,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8436,17 +8356,15 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8702,15 +8620,13 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v2.h, v2.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8734,24 +8650,21 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8993,36 +8906,31 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -9033,7 +8941,7 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -9046,15 +8954,13 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9062,12 +8968,11 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -9404,38 +9309,34 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -9452,38 +9353,34 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14191,15 +14088,13 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_memo
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14422,15 +14317,13 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14658,15 +14551,13 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14908,21 +14799,18 @@ define void @flat_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15129,21 +15017,18 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15357,21 +15242,18 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15605,15 +15487,13 @@ define <2 x half> @flat_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_f
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -15844,22 +15724,19 @@ define void @flat_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 40f58f5ce5902..5065995a703bd 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -2802,29 +2802,27 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2833,7 +2831,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB18_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -2842,16 +2840,14 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
@@ -3192,7 +3188,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3218,9 +3213,8 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3240,13 +3234,11 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3604,7 +3596,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3630,9 +3621,8 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[8:9], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[4:5], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3652,13 +3642,11 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
-; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4017,7 +4005,6 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4033,20 +4020,18 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB21_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4055,19 +4040,17 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4403,14 +4386,13 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4422,20 +4404,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4443,20 +4423,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4808,14 +4786,13 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4827,20 +4804,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[6:7], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4848,20 +4823,18 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5214,29 +5187,27 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5245,7 +5216,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB24_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5254,16 +5225,14 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
@@ -5638,29 +5607,27 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5669,7 +5636,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB25_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -5678,16 +5645,14 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -6033,9 +5998,8 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6050,11 +6014,9 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6079,9 +6041,8 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
@@ -6095,12 +6056,11 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6421,35 +6381,30 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6460,7 +6415,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -6473,15 +6428,13 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6489,12 +6442,11 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6827,35 +6779,30 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -6866,7 +6813,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -6879,15 +6826,13 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6895,12 +6840,11 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7235,9 +7179,8 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7251,10 +7194,9 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7279,9 +7221,8 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
@@ -7294,12 +7235,10 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7611,37 +7550,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7658,37 +7593,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8005,37 +7936,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8052,37 +7979,33 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8401,7 +8324,6 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8409,9 +8331,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8436,17 +8356,15 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8702,15 +8620,13 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v2.h, v2.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -8734,24 +8650,21 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1] offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1] offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8993,36 +8906,31 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v5, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -9033,7 +8941,7 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -9046,15 +8954,13 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: flat_load_b32 v5, v[0:1]
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9062,12 +8968,11 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -9404,38 +9309,34 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: flat_load_b32 v6, v[3:4]
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v5, v[3:4], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -9452,38 +9353,34 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: flat_load_b32 v4, v[0:1]
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14191,15 +14088,13 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_memo
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14422,15 +14317,13 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14658,15 +14551,13 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_fi
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14908,21 +14799,18 @@ define void @flat_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1]
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15129,21 +15017,18 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15357,21 +15242,18 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15605,15 +15487,13 @@ define <2 x half> @flat_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_f
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -15844,22 +15724,19 @@ define void @flat_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: flat_load_b32 v3, v[0:1] offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: flat_load_b32 v4, v[0:1] offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index 199a65b52a858..71ef9bb11e780 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -12336,13 +12336,10 @@ define double @flat_atomic_fmax_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: .LBB112_3: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB112_4: ; %atomicrmw.end
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
@@ -12375,13 +12372,10 @@ define double @flat_atomic_fmax_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-GISEL-NEXT: s_sub_co_i32 s0, s2, src_flat_scratch_base_lo
; GFX1250-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_cselect_b32 s0, s0, -1
; GFX1250-GISEL-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB112_4: ; %atomicrmw.end
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
@@ -12487,12 +12481,9 @@ define void @flat_atomic_fmax_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: .LBB113_4: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
@@ -12523,12 +12514,9 @@ define void @flat_atomic_fmax_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-GISEL-NEXT: s_sub_co_i32 s0, s2, src_flat_scratch_base_lo
; GFX1250-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_cselect_b32 s0, s0, -1
; GFX1250-GISEL-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB113_4: ; %atomicrmw.phi
@@ -12628,13 +12616,10 @@ define double @flat_atomic_fmin_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: .LBB114_3: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB114_4: ; %atomicrmw.end
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
@@ -12667,13 +12652,10 @@ define double @flat_atomic_fmin_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-GISEL-NEXT: s_sub_co_i32 s0, s2, src_flat_scratch_base_lo
; GFX1250-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_cselect_b32 s0, s0, -1
; GFX1250-GISEL-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB114_4: ; %atomicrmw.end
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
@@ -12779,12 +12761,9 @@ define void @flat_atomic_fmin_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: .LBB115_4: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
@@ -12815,12 +12794,9 @@ define void @flat_atomic_fmin_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-GISEL-NEXT: s_sub_co_i32 s0, s2, src_flat_scratch_base_lo
; GFX1250-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_cselect_b32 s0, s0, -1
; GFX1250-GISEL-NEXT: scratch_load_b64 v[2:3], off, s0
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB115_4: ; %atomicrmw.phi
@@ -13274,29 +13250,27 @@ define <2 x half> @flat_atomic_fmax_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, 0
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-NEXT: flat_load_b32 v0, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
; GFX1250-NEXT: .LBB124_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v5, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX1250-NEXT: v_pk_max_num_f16 v4, v0, v1
+; GFX1250-NEXT: v_mov_b32_e32 v5, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_pk_max_num_f16 v4, v5, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v5
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v5
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_cbranch_execnz .LBB124_1
; GFX1250-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1250-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX950-SDAG-LABEL: flat_atomic_fmax_v2f16_saddr_rtn:
@@ -13358,22 +13332,19 @@ define void @flat_atomic_fmax_v2f16_saddr_nortn(ptr inreg %ptr, <2 x half> %data
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: v_pk_max_num_f16 v3, v0, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v3, v1, s[0:1] offset:40
; GFX1250-NEXT: .LBB125_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v1, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v3
+; GFX1250-NEXT: v_pk_max_num_f16 v2, v3, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v2, v1, v[2:3], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_mov_b32_e32 v1, v0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_mov_b32_e32 v3, v2
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
@@ -13441,29 +13412,27 @@ define <2 x half> @flat_atomic_fmin_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, 0
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-NEXT: flat_load_b32 v0, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
; GFX1250-NEXT: .LBB126_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v5, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v5, v5
-; GFX1250-NEXT: v_pk_min_num_f16 v4, v0, v1
+; GFX1250-NEXT: v_mov_b32_e32 v5, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_pk_min_num_f16 v4, v5, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v2, v[4:5], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v5
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v5
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1250-NEXT: s_cbranch_execnz .LBB126_1
; GFX1250-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1250-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX950-SDAG-LABEL: flat_atomic_fmin_v2f16_saddr_rtn:
@@ -13525,22 +13494,19 @@ define void @flat_atomic_fmin_v2f16_saddr_nortn(ptr inreg %ptr, <2 x half> %data
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: v_pk_max_num_f16 v3, v0, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: flat_load_b32 v1, v2, s[0:1] offset:40
+; GFX1250-NEXT: flat_load_b32 v3, v1, s[0:1] offset:40
; GFX1250-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v1, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_min_num_f16 v0, v0, v3
+; GFX1250-NEXT: v_pk_min_num_f16 v2, v3, v0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] offset:40 th:TH_ATOMIC_RETURN
+; GFX1250-NEXT: flat_atomic_cmpswap_b32 v2, v1, v[2:3], s[0:1] offset:40 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_mov_b32_e32 v1, v0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_mov_b32_e32 v3, v2
; GFX1250-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_not1_b32 exec_lo, exec_lo, s2
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
index 1c4c59855ea98..c76d1742d99f4 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
@@ -1239,12 +1239,9 @@ define <2 x half> @v_max3_v2f16_maximumnum_maximumnum__v_v_v_0(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-NEXT: v_pk_max_num_f16 v1, v2, v2
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %a, <2 x half> %b)
%max3 = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %tmp0, <2 x half> %c)
@@ -1411,18 +1408,11 @@ define <3 x half> @v_max3_v3f16_maximumnum_maximumnum__v_v_v_0(<3 x half> %a, <3
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <3 x half> @llvm.maximumnum.v3f16(<3 x half> %a, <3 x half> %b)
%max3 = call <3 x half> @llvm.maximumnum.v3f16(<3 x half> %tmp0, <3 x half> %c)
@@ -1621,18 +1611,11 @@ define <4 x half> @v_max3_v4f16_maximumnum_maximumnum__v_v_v_0(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %a, <4 x half> %b)
%max3 = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %tmp0, <4 x half> %c)
@@ -1718,11 +1701,8 @@ define double @v_max3_f64_maximumnum_maximumnum__v_v_v_0(double %a, double %b, d
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call double @llvm.maximumnum.f64(double %a, double %b)
@@ -3192,11 +3172,7 @@ define float @v_min3_f32_maximumnum_neg_maximumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: v_minmax_num_f32 v0, v0, -v1, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.maximumnum.f32(float %neg.a, float %b)
@@ -3280,13 +3256,9 @@ define float @v_min3_f32_maximumnum_fabs_maximumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, |v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.maximumnum.f32(float %neg.a, float %b)
@@ -3370,13 +3342,9 @@ define float @v_min3_f32_maximumnum_fneg_fabs_maximumnum__v_v_v_0(float %a, floa
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e64 v0, -|v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.maximumnum.f32(float %neg.a, float %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index 48b334233a075..4bd537d708b11 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -58,36 +58,17 @@ define amdgpu_kernel void @test_fmax_f32_ieee_mode_on(ptr addrspace(1) %out, flo
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: test_fmax_f32_ieee_mode_on:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: test_fmax_f32_ieee_mode_on:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: s_max_num_f32 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: test_fmax_f32_ieee_mode_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f32 s2, s2, s3
+; GFX12-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: s_mov_b32 s2, -1
+; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float %a, float %b) #1
store float %val, ptr addrspace(1) %out, align 4
ret void
@@ -185,12 +166,10 @@ define amdgpu_kernel void @test_fmax_v2f32(ptr addrspace(1) %out, <2 x float> %a
; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v0 :: v_dual_max_num_f32 v0, v3, v2
+; GFX12-SDAG-NEXT: s_max_num_f32 s0, s0, s2
+; GFX12-SDAG-NEXT: s_max_num_f32 s1, s1, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -202,20 +181,9 @@ define amdgpu_kernel void @test_fmax_v2f32(ptr addrspace(1) %out, <2 x float> %a
; GFX12-GISEL-NEXT: s_mov_b32 s6, -1
; GFX12-GISEL-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s1, s1
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
-; GFX12-GISEL-NEXT: s_max_num_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_max_num_f32 s1, s2, s3
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: s_max_num_f32 s0, s0, s2
+; GFX12-GISEL-NEXT: s_max_num_f32 s1, s1, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
; GFX12-GISEL-NEXT: s_endpgm
@@ -306,18 +274,15 @@ define amdgpu_kernel void @test_fmax_v3f32(ptr addrspace(1) %out, <3 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s8, s12
+; GFX12-SDAG-NEXT: s_max_num_f32 s3, s9, s13
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s10, s14
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s4
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s8, s8
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v1, v0 :: v_dual_max_num_f32 v1, v4, v3
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v6, v5
; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -326,25 +291,13 @@ define amdgpu_kernel void @test_fmax_v3f32(ptr addrspace(1) %out, <3 x float> %a
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s13, s13
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s14, s14
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
-; GFX12-GISEL-NEXT: s_max_num_f32 s4, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_max_num_f32 s5, s5, s6
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_max_num_f32 s6, s7, s8
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s8, s12
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s9, s13
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s10, s14
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
@@ -448,20 +401,16 @@ define amdgpu_kernel void @test_fmax_v4f32(ptr addrspace(1) %out, <4 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s8, s12
+; GFX12-SDAG-NEXT: s_max_num_f32 s3, s9, s13
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s10, s14
+; GFX12-SDAG-NEXT: s_max_num_f32 s5, s11, s15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s8, s8
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v6, v5 :: v_dual_max_num_f32 v0, v8, v7
; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -470,32 +419,16 @@ define amdgpu_kernel void @test_fmax_v4f32(ptr addrspace(1) %out, <4 x float> %a
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s13, s13
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s14, s14
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s15, s15
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
-; GFX12-GISEL-NEXT: s_max_num_f32 s4, s2, s3
-; GFX12-GISEL-NEXT: s_max_num_f32 s5, s5, s6
-; GFX12-GISEL-NEXT: s_max_num_f32 s6, s7, s8
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_max_num_f32 s7, s9, s10
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s8, s12
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s9, s13
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s10, s14
+; GFX12-GISEL-NEXT: s_max_num_f32 s7, s11, s15
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
@@ -649,33 +582,24 @@ define amdgpu_kernel void @test_fmax_v8f32(ptr addrspace(1) %out, <8 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s9, s17
+; GFX12-SDAG-NEXT: s_max_num_f32 s5, s8, s16
+; GFX12-SDAG-NEXT: s_max_num_f32 s6, s12, s20
+; GFX12-SDAG-NEXT: s_max_num_f32 s7, s13, s21
+; GFX12-SDAG-NEXT: s_max_num_f32 s8, s14, s22
+; GFX12-SDAG-NEXT: s_max_num_f32 s9, s15, s23
+; GFX12-SDAG-NEXT: s_max_num_f32 s2, s11, s19
+; GFX12-SDAG-NEXT: s_max_num_f32 s3, s10, s18
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s4
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, s2
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s19, s19
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s18, s18
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s17, s17
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v15, s20, s20
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s8, s8
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v6, v5 :: v_dual_max_num_f32 v6, v12, v11
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v7, v10, v7 :: v_dual_max_num_f32 v0, v9, v8
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v14, v13 :: v_dual_max_num_f32 v4, v16, v15
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmax_v8f32:
@@ -683,54 +607,21 @@ define amdgpu_kernel void @test_fmax_v8f32(ptr addrspace(1) %out, <8 x float> %a
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s16, s16
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s17, s17
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s18, s18
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s19, s19
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s20, s20
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s13, s13
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s21, s21
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v12, s14, s14
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v13, s22, s22
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v14, s15, s15
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v15, s23, s23
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v8
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v9
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v10
-; GFX12-GISEL-NEXT: s_max_num_f32 s4, s2, s3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v11
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v12
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v13
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v14
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v15
-; GFX12-GISEL-NEXT: s_max_num_f32 s5, s5, s6
-; GFX12-GISEL-NEXT: s_max_num_f32 s6, s7, s8
-; GFX12-GISEL-NEXT: s_max_num_f32 s7, s9, s10
-; GFX12-GISEL-NEXT: s_max_num_f32 s8, s11, s12
-; GFX12-GISEL-NEXT: s_max_num_f32 s9, s13, s2
-; GFX12-GISEL-NEXT: s_max_num_f32 s10, s3, s14
-; GFX12-GISEL-NEXT: s_max_num_f32 s11, s15, s16
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s8, s16
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s9, s17
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s10, s18
+; GFX12-GISEL-NEXT: s_max_num_f32 s7, s11, s19
+; GFX12-GISEL-NEXT: s_max_num_f32 s8, s12, s20
+; GFX12-GISEL-NEXT: s_max_num_f32 s9, s13, s21
+; GFX12-GISEL-NEXT: s_max_num_f32 s10, s14, s22
+; GFX12-GISEL-NEXT: s_max_num_f32 s11, s15, s23
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
@@ -992,162 +883,76 @@ define amdgpu_kernel void @test_fmax_v16f32(ptr addrspace(1) %out, <16 x float>
; GFX12-SDAG-LABEL: test_fmax_v16f32:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x2
-; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s39, s39
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s38, s38
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s37, s37
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s43, s43
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s42, s42
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s41, s41
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s47, s47
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s19, s19
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v1, v0 :: v_dual_max_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v7, v8, v7
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s46, s46
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s18, s18
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v1, v6, v5
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v6, v10, v9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s45, s45
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s17, s17
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v5, v12, v11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v18, s40, s40
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v19, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v10, v4, v0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v9, v9, v8
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s51, s51
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s50, s50
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v20, s49, s49
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v21, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v22, s48, s48
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v23, s20, s20
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v11, v14, v13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s44, s44
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v24, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s36, s36
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v17, s8, s8
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v15, v8, v4
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v14, v13, v12
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v13, v21, v20 :: v_dual_max_num_f32 v12, v23, v22
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v8, v24, v0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v4, v19, v18
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v17, v16
+; GFX12-SDAG-NEXT: s_max_num_f32 s4, s11, s39
+; GFX12-SDAG-NEXT: s_max_num_f32 s5, s10, s38
+; GFX12-SDAG-NEXT: s_max_num_f32 s6, s9, s37
+; GFX12-SDAG-NEXT: s_max_num_f32 s7, s8, s36
+; GFX12-SDAG-NEXT: s_max_num_f32 s8, s15, s43
+; GFX12-SDAG-NEXT: s_max_num_f32 s9, s14, s42
+; GFX12-SDAG-NEXT: s_max_num_f32 s10, s13, s41
+; GFX12-SDAG-NEXT: s_max_num_f32 s11, s12, s40
+; GFX12-SDAG-NEXT: s_max_num_f32 s12, s19, s47
+; GFX12-SDAG-NEXT: s_max_num_f32 s13, s18, s46
+; GFX12-SDAG-NEXT: s_max_num_f32 s14, s17, s45
+; GFX12-SDAG-NEXT: s_max_num_f32 s15, s16, s44
+; GFX12-SDAG-NEXT: s_max_num_f32 s16, s20, s48
+; GFX12-SDAG-NEXT: s_max_num_f32 s17, s21, s49
+; GFX12-SDAG-NEXT: s_max_num_f32 s18, s22, s50
+; GFX12-SDAG-NEXT: s_max_num_f32 s19, s23, s51
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s15 :: v_dual_mov_b32 v5, s14
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s13 :: v_dual_mov_b32 v7, s12
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, s10
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v11, s8
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v13, s6
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v15, s4
; GFX12-SDAG-NEXT: s_clause 0x3
-; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
-; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:48
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:32
+; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmax_v16f32:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_clause 0x2
-; GFX12-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x64
-; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0xa4
+; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s36, s36
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s37, s37
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s38, s38
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s39, s39
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s11, s11
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s40, s40
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s13, s13
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v5
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v6
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v7
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v8
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s24, v9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s42, s42
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s14, s14
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s43, s43
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s15, s15
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s44, s44
-; GFX12-GISEL-NEXT: s_max_num_f32 s8, s2, s3
-; GFX12-GISEL-NEXT: s_max_num_f32 s9, s4, s5
-; GFX12-GISEL-NEXT: s_max_num_f32 s10, s6, s7
-; GFX12-GISEL-NEXT: s_max_num_f32 s11, s11, s12
-; GFX12-GISEL-NEXT: s_max_num_f32 s4, s13, s24
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s16, s16
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s45, s45
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s17, s17
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s46, s46
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s18, s18
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s47, s47
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s19, s19
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s48, s48
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s20, s20
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s49, s49
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s41, s41
-; GFX12-GISEL-NEXT: s_max_num_f32 s6, s2, s3
-; GFX12-GISEL-NEXT: s_max_num_f32 s7, s7, s12
-; GFX12-GISEL-NEXT: s_max_num_f32 s12, s13, s14
-; GFX12-GISEL-NEXT: s_max_num_f32 s13, s15, s16
-; GFX12-GISEL-NEXT: s_max_num_f32 s14, s17, s18
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s21, s21
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s50, s50
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s22, s22
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s51, s51
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s23, s23
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s25, v10
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s26, v11
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s19, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s20, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s21, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s22, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s23, v4
-; GFX12-GISEL-NEXT: s_max_num_f32 s5, s25, s26
-; GFX12-GISEL-NEXT: s_max_num_f32 s15, s2, s3
-; GFX12-GISEL-NEXT: s_max_num_f32 s16, s16, s17
-; GFX12-GISEL-NEXT: s_max_num_f32 s17, s18, s19
-; GFX12-GISEL-NEXT: s_max_num_f32 s18, s20, s21
-; GFX12-GISEL-NEXT: s_max_num_f32 s19, s22, s23
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-GISEL-NEXT: s_max_num_f32 s4, s8, s36
+; GFX12-GISEL-NEXT: s_max_num_f32 s5, s9, s37
+; GFX12-GISEL-NEXT: s_max_num_f32 s6, s10, s38
+; GFX12-GISEL-NEXT: s_max_num_f32 s7, s11, s39
+; GFX12-GISEL-NEXT: s_max_num_f32 s8, s12, s40
+; GFX12-GISEL-NEXT: s_max_num_f32 s9, s13, s41
+; GFX12-GISEL-NEXT: s_max_num_f32 s10, s14, s42
+; GFX12-GISEL-NEXT: s_max_num_f32 s11, s15, s43
+; GFX12-GISEL-NEXT: s_max_num_f32 s12, s16, s44
+; GFX12-GISEL-NEXT: s_max_num_f32 s13, s17, s45
+; GFX12-GISEL-NEXT: s_max_num_f32 s14, s18, s46
+; GFX12-GISEL-NEXT: s_max_num_f32 s15, s19, s47
+; GFX12-GISEL-NEXT: s_max_num_f32 s16, s20, s48
+; GFX12-GISEL-NEXT: s_max_num_f32 s17, s21, s49
+; GFX12-GISEL-NEXT: s_max_num_f32 s18, s22, s50
+; GFX12-GISEL-NEXT: s_max_num_f32 s19, s23, s51
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19
; GFX12-GISEL-NEXT: s_clause 0x3
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
@@ -1825,35 +1630,16 @@ define <3 x float> @test_func_fmax_v3f32(<3 x float> %a, <3 x float> %b) #0 {
; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: test_func_fmax_v3f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v2, v2, v5
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_func_fmax_v3f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v5
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_func_fmax_v3f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
+; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %val
}
@@ -1915,38 +1701,18 @@ define amdgpu_kernel void @test_fmax_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX9-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: test_fmax_f16_v_ieee_on:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: test_fmax_f16_v_ieee_on:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1.l, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: s_max_num_f16 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: test_fmax_f16_v_ieee_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_max_num_f16 s2, s2, s3
+; GFX12-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-NEXT: s_mov_b32 s2, -1
+; GFX12-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-NEXT: s_endpgm
%val = call half @llvm.maxnum.f16(half %a, half %b)
store half %val, ptr addrspace(1) %out, align 2
ret void
@@ -2039,12 +1805,11 @@ define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_max_num_f16 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2055,15 +1820,9 @@ define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-GISEL-NEXT: s_load_u16 s3, s[4:5], 0x2e
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1.l, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-NEXT: s_max_num_f16 s2, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
@@ -2148,36 +1907,17 @@ define amdgpu_kernel void @test_fmax_f32_s_ieee_on(ptr addrspace(1) %out, float
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: test_fmax_f32_s_ieee_on:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: test_fmax_f32_s_ieee_on:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: s_max_num_f32 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: test_fmax_f32_s_ieee_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f32 s2, s2, s3
+; GFX12-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: s_mov_b32 s2, -1
+; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-NEXT: s_endpgm
%val = call float @llvm.maxnum.f32(float %a, float %b)
store float %val, ptr addrspace(1) %out, align 4
ret void
@@ -2281,12 +2021,9 @@ define amdgpu_kernel void @test_fmax_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2294,12 +2031,9 @@ define amdgpu_kernel void @test_fmax_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -2409,26 +2143,22 @@ define amdgpu_kernel void @test_fmax_v2f16_s_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG-LABEL: test_fmax_v2f16_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s2, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX12-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmax_v2f16_s_ieee_on:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -2536,15 +2266,12 @@ define amdgpu_kernel void @test_fmax_f64_v_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmax_f64_v_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2554,12 +2281,9 @@ define amdgpu_kernel void @test_fmax_f64_v_ieee_on(ptr addrspace(1) %out, double
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call double @llvm.maxnum.f64(double %a, double %b)
@@ -2649,15 +2373,12 @@ define amdgpu_kernel void @test_fmax_f64_s_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmax_f64_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2667,12 +2388,9 @@ define amdgpu_kernel void @test_fmax_f64_s_ieee_on(ptr addrspace(1) %out, double
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call double @llvm.maxnum.f64(double %a, double %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
index 6e124f6620b5e..bb34d552f6058 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
@@ -1239,12 +1239,9 @@ define <2 x half> @v_min3_v2f16_minimumnum_minimumnum__v_v_v_0(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-NEXT: v_pk_max_num_f16 v1, v2, v2
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %a, <2 x half> %b)
%min3 = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %tmp0, <2 x half> %c)
@@ -1411,18 +1408,11 @@ define <3 x half> @v_min3_v3f16_minimumnum_minimumnum__v_v_v_0(<3 x half> %a, <3
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <3 x half> @llvm.minimumnum.v3f16(<3 x half> %a, <3 x half> %b)
%min3 = call <3 x half> @llvm.minimumnum.v3f16(<3 x half> %tmp0, <3 x half> %c)
@@ -1621,18 +1611,11 @@ define <4 x half> @v_min3_v4f16_minimumnum_minimumnum__v_v_v_0(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_max_num_f16 v2, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v4, v5, v5
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %a, <4 x half> %b)
%min3 = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %tmp0, <4 x half> %c)
@@ -1718,11 +1701,8 @@ define double @v_min3_f64_minimumnum_minimumnum__v_v_v_0(double %a, double %b, d
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call double @llvm.minimumnum.f64(double %a, double %b)
@@ -3197,11 +3177,7 @@ define float @v_min3_f32_minimumnum_neg_minimumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: v_maxmin_num_f32 v0, v0, -v1, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.minimumnum.f32(float %neg.a, float %b)
@@ -3285,13 +3261,9 @@ define float @v_min3_f32_minimumnum_fabs_minimumnum__v_v_v_0(float %a, float %b,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX12-NEXT: v_min_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, |v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.minimumnum.f32(float %neg.a, float %b)
@@ -3375,13 +3347,9 @@ define float @v_min3_f32_minimumnum_fneg_fabs_minimumnum__v_v_v_0(float %a, floa
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
-; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX12-NEXT: v_min_num_f32_e64 v0, -v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e64 v0, -|v0|, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%tmp0 = call float @llvm.minimumnum.f32(float %neg.a, float %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll
index 0744b4cce087c..e23c47e26807b 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll
@@ -1413,18 +1413,17 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: buffer_load_b64 v[2:3], off, s[16:19], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: s_mov_b32 s12, s6
-; GFX1170-NEXT: s_mov_b32 s13, s7
+; GFX1170-NEXT: s_mov_b32 s4, s6
+; GFX1170-NEXT: s_mov_b32 s5, s7
+; GFX1170-NEXT: s_mov_b32 s6, s10
+; GFX1170-NEXT: s_mov_b32 s7, s11
; GFX1170-NEXT: s_mov_b32 s8, s0
-; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[12:15], 0 glc dlc
+; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[4:7], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: s_mov_b32 s9, s1
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[4:5], v[4:5]
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX1170-NEXT: s_endpgm
;
@@ -1446,18 +1445,17 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[16:19], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_mov_b32 s12, s6
-; GFX12-NEXT: s_mov_b32 s13, s7
+; GFX12-NEXT: s_mov_b32 s4, s6
+; GFX12-NEXT: s_mov_b32 s5, s7
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
; GFX12-NEXT: s_mov_b32 s8, s0
-; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_mov_b32 s9, s1
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-NEXT: s_endpgm
;
@@ -1486,12 +1484,9 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
; GFX1250-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_mov_b32 s1, s9
-; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX1250-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1250-NEXT: s_endpgm
%a = load volatile double, ptr addrspace(1) %aptr, align 4
@@ -1656,18 +1651,17 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: buffer_load_b64 v[2:3], off, s[16:19], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: s_mov_b32 s12, s6
-; GFX1170-NEXT: s_mov_b32 s13, s7
+; GFX1170-NEXT: s_mov_b32 s4, s6
+; GFX1170-NEXT: s_mov_b32 s5, s7
+; GFX1170-NEXT: s_mov_b32 s6, s10
+; GFX1170-NEXT: s_mov_b32 s7, s11
; GFX1170-NEXT: s_mov_b32 s8, s0
-; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[12:15], 0 glc dlc
+; GFX1170-NEXT: buffer_load_b64 v[4:5], off, s[4:7], 0 glc dlc
; GFX1170-NEXT: s_waitcnt vmcnt(0)
; GFX1170-NEXT: s_mov_b32 s9, s1
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-NEXT: v_max_num_f64 v[2:3], v[4:5], v[4:5]
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[4:5], v[0:1]
; GFX1170-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX1170-NEXT: s_endpgm
;
@@ -1689,18 +1683,17 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[16:19], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_mov_b32 s12, s6
-; GFX12-NEXT: s_mov_b32 s13, s7
+; GFX12-NEXT: s_mov_b32 s4, s6
+; GFX12-NEXT: s_mov_b32 s5, s7
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
; GFX12-NEXT: s_mov_b32 s8, s0
-; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_mov_b32 s9, s1
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-NEXT: s_endpgm
;
@@ -1729,12 +1722,9 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
; GFX1250-NEXT: buffer_load_b64 v[4:5], off, s[4:7], null scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_mov_b32 s1, s9
-; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
; GFX1250-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1250-NEXT: s_endpgm
%a = load volatile double, ptr addrspace(1) %aptr, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index 2444f7dee860b..c7bd92ee37612 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -58,36 +58,17 @@ define amdgpu_kernel void @test_fmin_f32_ieee_mode_on(ptr addrspace(1) %out, flo
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: test_fmin_f32_ieee_mode_on:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: test_fmin_f32_ieee_mode_on:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: s_min_num_f32 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: test_fmin_f32_ieee_mode_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f32 s2, s2, s3
+; GFX12-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: s_mov_b32 s2, -1
+; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float %a, float %b)
store float %val, ptr addrspace(1) %out, align 4
ret void
@@ -230,12 +211,10 @@ define amdgpu_kernel void @test_fmin_v2f32(ptr addrspace(1) %out, <2 x float> %a
; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v3, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v1, v0 :: v_dual_min_num_f32 v0, v3, v2
+; GFX12-SDAG-NEXT: s_min_num_f32 s0, s0, s2
+; GFX12-SDAG-NEXT: s_min_num_f32 s1, s1, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -247,20 +226,9 @@ define amdgpu_kernel void @test_fmin_v2f32(ptr addrspace(1) %out, <2 x float> %a
; GFX12-GISEL-NEXT: s_mov_b32 s6, -1
; GFX12-GISEL-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s1, s1
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3
-; GFX12-GISEL-NEXT: s_min_num_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_min_num_f32 s1, s2, s3
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: s_min_num_f32 s0, s0, s2
+; GFX12-GISEL-NEXT: s_min_num_f32 s1, s1, s3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[4:7], null
; GFX12-GISEL-NEXT: s_endpgm
@@ -363,20 +331,16 @@ define amdgpu_kernel void @test_fmin_v4f32(ptr addrspace(1) %out, <4 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_min_num_f32 s2, s8, s12
+; GFX12-SDAG-NEXT: s_min_num_f32 s3, s9, s13
+; GFX12-SDAG-NEXT: s_min_num_f32 s4, s10, s14
+; GFX12-SDAG-NEXT: s_min_num_f32 s5, s11, s15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s8, s8
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v6, v5 :: v_dual_min_num_f32 v0, v8, v7
; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -385,32 +349,16 @@ define amdgpu_kernel void @test_fmin_v4f32(ptr addrspace(1) %out, <4 x float> %a
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s13, s13
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s14, s14
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s15, s15
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
-; GFX12-GISEL-NEXT: s_min_num_f32 s4, s2, s3
-; GFX12-GISEL-NEXT: s_min_num_f32 s5, s5, s6
-; GFX12-GISEL-NEXT: s_min_num_f32 s6, s7, s8
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_min_num_f32 s7, s9, s10
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_min_num_f32 s4, s8, s12
+; GFX12-GISEL-NEXT: s_min_num_f32 s5, s9, s13
+; GFX12-GISEL-NEXT: s_min_num_f32 s6, s10, s14
+; GFX12-GISEL-NEXT: s_min_num_f32 s7, s11, s15
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
@@ -564,33 +512,24 @@ define amdgpu_kernel void @test_fmin_v8f32(ptr addrspace(1) %out, <8 x float> %a
; GFX12-SDAG-NEXT: s_clause 0x1
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_min_num_f32 s4, s9, s17
+; GFX12-SDAG-NEXT: s_min_num_f32 s5, s8, s16
+; GFX12-SDAG-NEXT: s_min_num_f32 s6, s12, s20
+; GFX12-SDAG-NEXT: s_min_num_f32 s7, s13, s21
+; GFX12-SDAG-NEXT: s_min_num_f32 s8, s14, s22
+; GFX12-SDAG-NEXT: s_min_num_f32 s9, s15, s23
+; GFX12-SDAG-NEXT: s_min_num_f32 s2, s11, s19
+; GFX12-SDAG-NEXT: s_min_num_f32 s3, s10, s18
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s4
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, s2
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s19, s19
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s18, s18
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s17, s17
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v15, s20, s20
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s12, s12
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s8, s8
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v1, v6, v5 :: v_dual_min_num_f32 v6, v12, v11
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v7, v10, v7 :: v_dual_min_num_f32 v0, v9, v8
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v5, v14, v13 :: v_dual_min_num_f32 v4, v16, v15
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmin_v8f32:
@@ -598,54 +537,21 @@ define amdgpu_kernel void @test_fmin_v8f32(ptr addrspace(1) %out, <8 x float> %a
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s16, s16
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s17, s17
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s18, s18
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s11, s11
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s19, s19
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s20, s20
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s13, s13
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s21, s21
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v12, s14, s14
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v13, s22, s22
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v14, s15, s15
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v15, s23, s23
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v5
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v6
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v7
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v8
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v9
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v10
-; GFX12-GISEL-NEXT: s_min_num_f32 s4, s2, s3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v11
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v12
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v13
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v14
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v15
-; GFX12-GISEL-NEXT: s_min_num_f32 s5, s5, s6
-; GFX12-GISEL-NEXT: s_min_num_f32 s6, s7, s8
-; GFX12-GISEL-NEXT: s_min_num_f32 s7, s9, s10
-; GFX12-GISEL-NEXT: s_min_num_f32 s8, s11, s12
-; GFX12-GISEL-NEXT: s_min_num_f32 s9, s13, s2
-; GFX12-GISEL-NEXT: s_min_num_f32 s10, s3, s14
-; GFX12-GISEL-NEXT: s_min_num_f32 s11, s15, s16
+; GFX12-GISEL-NEXT: s_min_num_f32 s4, s8, s16
+; GFX12-GISEL-NEXT: s_min_num_f32 s5, s9, s17
+; GFX12-GISEL-NEXT: s_min_num_f32 s6, s10, s18
+; GFX12-GISEL-NEXT: s_min_num_f32 s7, s11, s19
+; GFX12-GISEL-NEXT: s_min_num_f32 s8, s12, s20
+; GFX12-GISEL-NEXT: s_min_num_f32 s9, s13, s21
+; GFX12-GISEL-NEXT: s_min_num_f32 s10, s14, s22
+; GFX12-GISEL-NEXT: s_min_num_f32 s11, s15, s23
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_clause 0x1
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX12-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
@@ -907,162 +813,76 @@ define amdgpu_kernel void @test_fmin_v16f32(ptr addrspace(1) %out, <16 x float>
; GFX12-SDAG-LABEL: test_fmin_v16f32:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x2
-; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-SDAG-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s39, s39
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s11, s11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v2, s38, s38
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s10, s10
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v5, s37, s37
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v6, s9, s9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v7, s43, s43
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s15, s15
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s42, s42
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v10, s14, s14
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v11, s41, s41
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s13, s13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s47, s47
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v14, s19, s19
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v3, v1, v0 :: v_dual_min_num_f32 v2, v4, v2
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v7, v8, v7
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s46, s46
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s18, s18
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v1, v6, v5
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v6, v10, v9
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s45, s45
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v9, s17, s17
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v5, v12, v11
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v18, s40, s40
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v19, s12, s12
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v10, v4, v0
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v9, v9, v8
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v4, s51, s51
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v8, s23, s23
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v12, s50, s50
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v20, s49, s49
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v21, s21, s21
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v22, s48, s48
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v23, s20, s20
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v11, v14, v13
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v13, s22, s22
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s44, s44
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v24, s16, s16
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v16, s36, s36
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v17, s8, s8
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v15, v8, v4
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v14, v13, v12
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v13, v21, v20 :: v_dual_min_num_f32 v12, v23, v22
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v8, v24, v0
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v4, v19, v18
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v17, v16
+; GFX12-SDAG-NEXT: s_min_num_f32 s4, s11, s39
+; GFX12-SDAG-NEXT: s_min_num_f32 s5, s10, s38
+; GFX12-SDAG-NEXT: s_min_num_f32 s6, s9, s37
+; GFX12-SDAG-NEXT: s_min_num_f32 s7, s8, s36
+; GFX12-SDAG-NEXT: s_min_num_f32 s8, s15, s43
+; GFX12-SDAG-NEXT: s_min_num_f32 s9, s14, s42
+; GFX12-SDAG-NEXT: s_min_num_f32 s10, s13, s41
+; GFX12-SDAG-NEXT: s_min_num_f32 s11, s12, s40
+; GFX12-SDAG-NEXT: s_min_num_f32 s12, s19, s47
+; GFX12-SDAG-NEXT: s_min_num_f32 s13, s18, s46
+; GFX12-SDAG-NEXT: s_min_num_f32 s14, s17, s45
+; GFX12-SDAG-NEXT: s_min_num_f32 s15, s16, s44
+; GFX12-SDAG-NEXT: s_min_num_f32 s16, s20, s48
+; GFX12-SDAG-NEXT: s_min_num_f32 s17, s21, s49
+; GFX12-SDAG-NEXT: s_min_num_f32 s18, s22, s50
+; GFX12-SDAG-NEXT: s_min_num_f32 s19, s23, s51
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s15 :: v_dual_mov_b32 v5, s14
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s13 :: v_dual_mov_b32 v7, s12
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, s10
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v11, s8
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v13, s6
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v15, s4
; GFX12-SDAG-NEXT: s_clause 0x3
-; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null offset:48
-; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:32
-; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:16
-; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
+; GFX12-SDAG-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:48
+; GFX12-SDAG-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null offset:32
+; GFX12-SDAG-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null offset:16
+; GFX12-SDAG-NEXT: buffer_store_b128 v[12:15], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmin_v16f32:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_clause 0x2
-; GFX12-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x64
-; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0xa4
+; GFX12-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x64
+; GFX12-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0xa4
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s36, s36
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s8, s8
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s37, s37
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s9, s9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s38, s38
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v5, s10, s10
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v6, s39, s39
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v7, s11, s11
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v8, s40, s40
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v9, s12, s12
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v11, s13, s13
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v4
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v5
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v6
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v7
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v8
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s24, v9
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s42, s42
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s14, s14
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s43, s43
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s15, s15
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s44, s44
-; GFX12-GISEL-NEXT: s_min_num_f32 s8, s2, s3
-; GFX12-GISEL-NEXT: s_min_num_f32 s9, s4, s5
-; GFX12-GISEL-NEXT: s_min_num_f32 s10, s6, s7
-; GFX12-GISEL-NEXT: s_min_num_f32 s11, s11, s12
-; GFX12-GISEL-NEXT: s_min_num_f32 s4, s13, s24
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s12, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s13, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s16, s16
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s45, s45
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s17, s17
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s46, s46
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s18, s18
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s14, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s15, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s47, s47
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s19, s19
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s48, s48
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s20, s20
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s49, s49
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v10, s41, s41
-; GFX12-GISEL-NEXT: s_min_num_f32 s6, s2, s3
-; GFX12-GISEL-NEXT: s_min_num_f32 s7, s7, s12
-; GFX12-GISEL-NEXT: s_min_num_f32 s12, s13, s14
-; GFX12-GISEL-NEXT: s_min_num_f32 s13, s15, s16
-; GFX12-GISEL-NEXT: s_min_num_f32 s14, s17, s18
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s16, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s17, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s18, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s21, s21
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s50, s50
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v2, s22, s22
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v3, s51, s51
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v4, s23, s23
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s25, v10
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s26, v11
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s19, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s20, v1
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s21, v2
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s22, v3
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s23, v4
-; GFX12-GISEL-NEXT: s_min_num_f32 s5, s25, s26
-; GFX12-GISEL-NEXT: s_min_num_f32 s15, s2, s3
-; GFX12-GISEL-NEXT: s_min_num_f32 s16, s16, s17
-; GFX12-GISEL-NEXT: s_min_num_f32 s17, s18, s19
-; GFX12-GISEL-NEXT: s_min_num_f32 s18, s20, s21
-; GFX12-GISEL-NEXT: s_min_num_f32 s19, s22, s23
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-GISEL-NEXT: s_min_num_f32 s4, s8, s36
+; GFX12-GISEL-NEXT: s_min_num_f32 s5, s9, s37
+; GFX12-GISEL-NEXT: s_min_num_f32 s6, s10, s38
+; GFX12-GISEL-NEXT: s_min_num_f32 s7, s11, s39
+; GFX12-GISEL-NEXT: s_min_num_f32 s8, s12, s40
+; GFX12-GISEL-NEXT: s_min_num_f32 s9, s13, s41
+; GFX12-GISEL-NEXT: s_min_num_f32 s10, s14, s42
+; GFX12-GISEL-NEXT: s_min_num_f32 s11, s15, s43
+; GFX12-GISEL-NEXT: s_min_num_f32 s12, s16, s44
+; GFX12-GISEL-NEXT: s_min_num_f32 s13, s17, s45
+; GFX12-GISEL-NEXT: s_min_num_f32 s14, s18, s46
+; GFX12-GISEL-NEXT: s_min_num_f32 s15, s19, s47
+; GFX12-GISEL-NEXT: s_min_num_f32 s16, s20, s48
+; GFX12-GISEL-NEXT: s_min_num_f32 s17, s21, s49
+; GFX12-GISEL-NEXT: s_min_num_f32 s18, s22, s50
+; GFX12-GISEL-NEXT: s_min_num_f32 s19, s23, s51
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19
; GFX12-GISEL-NEXT: s_clause 0x3
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
@@ -1738,35 +1558,16 @@ define <3 x float> @test_func_fmin_v3f32(<3 x float> %a, <3 x float> %b) nounwin
; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: test_func_fmin_v3f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v2, v2, v5
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_func_fmin_v3f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v5
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_func_fmin_v3f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX12-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call <3 x float> @llvm.minnum.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %val
}
@@ -1828,38 +1629,18 @@ define amdgpu_kernel void @test_fmin_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX9-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: test_fmin_f16_v_ieee_on:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: test_fmin_f16_v_ieee_on:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1.l, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: s_min_num_f16 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: test_fmin_f16_v_ieee_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_lshr_b32 s3, s2, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_min_num_f16 s2, s2, s3
+; GFX12-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-NEXT: s_mov_b32 s2, -1
+; GFX12-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX12-NEXT: s_endpgm
%val = call half @llvm.minnum.f16(half %a, half %b)
store half %val, ptr addrspace(1) %out, align 2
ret void
@@ -1952,12 +1733,11 @@ define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_min_num_f16 s2, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -1968,15 +1748,9 @@ define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-GISEL-NEXT: s_load_u16 s3, s[4:5], 0x2e
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1.l, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-NEXT: s_min_num_f16 s2, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
@@ -2061,36 +1835,17 @@ define amdgpu_kernel void @test_fmin_f32_s_ieee_on(ptr addrspace(1) %out, float
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: test_fmin_f32_s_ieee_on:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s3, s3
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: test_fmin_f32_s_ieee_on:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s2, s2
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s3, s3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-GISEL-NEXT: s_min_num_f32 s2, s2, s3
-; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: test_fmin_f32_s_ieee_on:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f32 s2, s2, s3
+; GFX12-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: s_mov_b32 s2, -1
+; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-NEXT: s_endpgm
%val = call float @llvm.minnum.f32(float %a, float %b)
store float %val, ptr addrspace(1) %out, align 4
ret void
@@ -2194,12 +1949,9 @@ define amdgpu_kernel void @test_fmin_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
+; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, s2, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0
; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2207,12 +1959,9 @@ define amdgpu_kernel void @test_fmin_v2f16_v_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -2322,26 +2071,22 @@ define amdgpu_kernel void @test_fmin_v2f16_s_ieee_on(ptr addrspace(1) %out, <2 x
; GFX12-SDAG-LABEL: test_fmin_v2f16_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX12-SDAG-NEXT: s_mov_b32 s6, -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, s3, s3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, s2, s2
-; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0
-; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, s2, s3
+; GFX12-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX12-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX12-SDAG-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: test_fmin_v2f16_s_ieee_on:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, s2, s2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, s3, s3
+; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, s2, s3
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-GISEL-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -2449,15 +2194,12 @@ define amdgpu_kernel void @test_fmin_f64_v_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmin_f64_v_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2467,12 +2209,9 @@ define amdgpu_kernel void @test_fmin_f64_v_ieee_on(ptr addrspace(1) %out, double
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: v_min_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call double @llvm.minnum.f64(double %a, double %b)
@@ -2562,15 +2301,12 @@ define amdgpu_kernel void @test_fmin_f64_s_ieee_on(ptr addrspace(1) %out, double
; GFX12-SDAG-LABEL: test_fmin_f64_s_ieee_on:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: s_clause 0x1
-; GFX12-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[6:7], s[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-SDAG-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2580,12 +2316,9 @@ define amdgpu_kernel void @test_fmin_f64_s_ieee_on(ptr addrspace(1) %out, double
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[4:5]
+; GFX12-GISEL-NEXT: v_min_num_f64_e64 v[0:1], s[2:3], s[4:5]
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
%val = call double @llvm.minnum.f64(double %a, double %b)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 93443914d3f97..170e6b3404d4d 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -3015,15 +3015,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3188,15 +3186,13 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3362,15 +3358,13 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3535,21 +3529,18 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3698,21 +3689,18 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:2040
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3864,21 +3852,18 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4031,15 +4016,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4279,15 +4262,13 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4456,9 +4437,8 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4473,11 +4453,9 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4502,9 +4480,8 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4518,12 +4495,11 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4892,35 +4868,30 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -4931,7 +4902,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -4944,15 +4915,13 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4960,12 +4929,11 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5348,35 +5316,30 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -5387,7 +5350,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -5400,15 +5363,13 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5416,12 +5377,11 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5806,9 +5766,8 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5822,10 +5781,9 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5850,9 +5808,8 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5865,12 +5822,10 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6230,37 +6185,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6277,37 +6228,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6673,37 +6620,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6720,37 +6663,33 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7118,7 +7057,6 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7126,9 +7064,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7153,17 +7089,15 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7458,15 +7392,13 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v2.h, v2.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7490,24 +7422,21 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7785,36 +7714,31 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -7825,7 +7749,7 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -7838,15 +7762,13 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7854,12 +7776,11 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -8246,38 +8167,34 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8294,38 +8211,34 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13580,15 +13493,13 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_me
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -13862,15 +13773,13 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -14146,15 +14055,13 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -14437,21 +14344,18 @@ define void @global_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14706,21 +14610,18 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14978,21 +14879,18 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15259,15 +15157,13 @@ define <2 x half> @global_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -15546,22 +15442,19 @@ define void @global_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fin
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index b8217cf862b3a..6050a495b723d 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -3015,15 +3015,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3188,15 +3186,13 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3362,15 +3358,13 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3535,21 +3529,18 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3698,21 +3689,18 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:2040
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:2040
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:2040 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -3864,21 +3852,18 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off offset:-2048
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
+; GFX12-NEXT: global_load_b64 v[6:7], v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4031,15 +4016,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4279,15 +4262,13 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b64 v[4:5], v[0:1], off
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
-; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4456,9 +4437,8 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4473,11 +4453,9 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v2.h, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4502,9 +4480,8 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -4518,12 +4495,11 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -4892,35 +4868,30 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -4931,7 +4902,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -4944,15 +4915,13 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4960,12 +4929,11 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5348,35 +5316,30 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -5387,7 +5350,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grained_memory:
@@ -5400,15 +5363,13 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5416,12 +5377,11 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5806,9 +5766,8 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5822,10 +5781,9 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -5850,9 +5808,8 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
@@ -5865,12 +5822,10 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -6230,37 +6185,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6277,37 +6228,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6673,37 +6620,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6720,37 +6663,33 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7118,7 +7057,6 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7126,9 +7064,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v2.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7153,17 +7089,15 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v4, v4
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7458,15 +7392,13 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v2.h, v2.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -7490,24 +7422,21 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v2, v2
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off offset:2046
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v3, v3
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v4, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7785,36 +7714,31 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v5, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v6, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-TRUE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
@@ -7825,7 +7749,7 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v1, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grained_memory:
@@ -7838,15 +7762,13 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX12-FAKE16-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7854,12 +7776,11 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v4, v5
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
@@ -8246,38 +8167,34 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
+; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX12-TRUE16-NEXT: global_load_b32 v6, v[3:4], off
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v1, 0xffff
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_not_b32_e32 v2, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-TRUE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-TRUE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v1, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v5.l, v5.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v0.h, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v1, v5
-; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -8294,38 +8211,34 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
+; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 3, v3
+; GFX12-FAKE16-NEXT: global_load_b32 v4, v[0:1], off
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 3, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v5, 0xffff
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v6, v3
; GFX12-FAKE16-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v6, v3
; GFX12-FAKE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13580,15 +13493,13 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_me
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -13862,15 +13773,13 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -14146,15 +14055,13 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -14437,21 +14344,18 @@ define void @global_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14706,21 +14610,18 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14978,21 +14879,18 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:-2048
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:-2048
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -15259,15 +15157,13 @@ define <2 x half> @global_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v4, v4
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -15546,22 +15442,19 @@ define void @global_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fin
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_b32 v3, v[0:1], off offset:2044
-; GFX12-NEXT: v_pk_max_num_f16 v4, v2, v2
+; GFX12-NEXT: global_load_b32 v4, v[0:1], off offset:2044
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v4
+; GFX12-NEXT: v_pk_min_num_f16 v3, v4, v2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX12-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[3:4], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: v_mov_b32_e32 v3, v2
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_mov_b32_e32 v4, v3
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 43d77d0afa8c6..2af2849248a6a 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -790,11 +790,9 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, 4.0, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
@@ -821,29 +819,28 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, -4, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: ds_load_b32 v3, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
+; GFX12-FAKE16-NEXT: ds_load_b32 v2, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v0, 0xffff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 24, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v3, v3
; GFX12-FAKE16-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v0, v4
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v0, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
+; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v2, v1, v2, v4
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -851,7 +848,7 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v2
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: local_atomic_fmax_ret_f16:
@@ -1182,11 +1179,9 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, 4.0, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v4
@@ -1226,12 +1221,11 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v4
@@ -1585,11 +1579,9 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, 4.0, v4.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v1, v4, v2
@@ -1626,12 +1618,11 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v4, v1, v4, v2
@@ -1966,10 +1957,9 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, 4.0, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v4, v3
@@ -2008,12 +1998,10 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v4, v3
@@ -2351,9 +2339,7 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, 4.0, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:65534
@@ -2384,10 +2370,9 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, 4.0, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:65534
@@ -2656,10 +2641,9 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, 4.0, v1.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, 4.0, v2.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v1 offset:65534
@@ -2688,11 +2672,9 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v1, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, 4.0, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v1 offset:65534
@@ -5508,15 +5490,13 @@ define <2 x half> @local_atomic_fmax_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -5771,15 +5751,13 @@ define <2 x half> @local_atomic_fmax_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3 offset:65532
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -6036,14 +6014,11 @@ define void @local_atomic_fmax_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -6285,14 +6260,11 @@ define void @local_atomic_fmax_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2 offset:65532
; GFX12-NEXT: s_wait_dscnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 1759a212c6ea3..56c15ba92c8ca 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -790,11 +790,9 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, 4.0, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
@@ -821,29 +819,28 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, -4, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
-; GFX12-FAKE16-NEXT: ds_load_b32 v3, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
+; GFX12-FAKE16-NEXT: ds_load_b32 v2, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e64 v3, v0, 0xffff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 24, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_not_b32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_not_b32_e32 v3, v3
; GFX12-FAKE16-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v0, v4
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v0, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v3, v1, v3, v4
+; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v2, v1, v2, v4
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
-; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -851,7 +848,7 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, v0, v2
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: local_atomic_fmin_ret_f16:
@@ -1182,11 +1179,9 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v3.l, 4.0, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v4
@@ -1226,12 +1221,11 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v1, v4
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v3, 4.0, v3
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v1, v3
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v3, v4, v2, v3
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v4
@@ -1585,11 +1579,9 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v4.l, 4.0, v4.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v1, v4, v2
@@ -1626,12 +1618,11 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v0, v2
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v2, v3, v4
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v4, v1, v4, v2
@@ -1966,10 +1957,9 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v4.l, 4.0, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v4, v3
@@ -2008,12 +1998,10 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v4, 4.0, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v4, v3, v2, v4
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v4, v3
@@ -2351,9 +2339,7 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, 4.0, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, 4.0, v2.l
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:65534
@@ -2384,10 +2370,9 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v2
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, 4.0, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v1, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v2, v1
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:65534
@@ -2656,10 +2641,9 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.l, 4.0, v1.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v2.l, 4.0, v2.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v1 offset:65534
@@ -2688,11 +2672,9 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v1, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, 4.0, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v2, 4.0, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v1, v2
; GFX12-FAKE16-NEXT: s_wait_storecnt 0x0
; GFX12-FAKE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v1 offset:65534
@@ -5508,15 +5490,13 @@ define <2 x half> @local_atomic_fmin_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -5771,15 +5751,13 @@ define <2 x half> @local_atomic_fmin_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_pk_max_num_f16 v2, v3, v3
-; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_num_f16 v2, v3, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v2, v0, v2, v3 offset:65532
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -6036,14 +6014,11 @@ define void @local_atomic_fmin_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_min_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -6285,14 +6260,11 @@ define void @local_atomic_fmin_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ds_load_b32 v2, v0 offset:65532
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
; GFX12-NEXT: s_mov_b32 s0, 0
; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v2, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v1
+; GFX12-NEXT: v_pk_min_num_f16 v3, v2, v1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: ds_cmpstore_rtn_b32 v3, v0, v3, v2 offset:65532
; GFX12-NEXT: s_wait_dscnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.ll
index c0f80363e6850..a37678dfe5404 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.ll
@@ -135,93 +135,37 @@ define half @v_maximumnum_f16(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_maximumnum_f16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half %y)
ret half %result
}
@@ -359,16 +303,12 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX1170-TRUE16-LABEL: v_maximumnum_f16_1.0:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, 1.0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_maximumnum_f16_1.0:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, 1.0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -379,8 +319,6 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, 1.0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -391,8 +329,6 @@ define half @v_maximumnum_f16_1.0(half %x) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, 1.0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half 1.0)
@@ -480,45 +416,21 @@ define float @v_maximumnum_f32(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
}
@@ -656,49 +568,21 @@ define double @v_maximumnum_f64(double %x, double %y) #1 {
; GFX11-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %result
}
@@ -793,8 +677,6 @@ define float @v_maximumnum_f32_1.0(float %x) #1 {
; GFX1170-LABEL: v_maximumnum_f32_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, 1.0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -805,8 +687,6 @@ define float @v_maximumnum_f32_1.0(float %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, 1.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float 1.0)
@@ -857,7 +737,7 @@ define float @v_maximumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_rhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX1170-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -869,7 +749,7 @@ define float @v_maximumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -922,7 +802,7 @@ define float @v_maximumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_maximumnum_f32_lhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -934,7 +814,7 @@ define float @v_maximumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1049,8 +929,6 @@ define double @v_maximumnum_f64_1.0(double %x) #1 {
; GFX1170-LABEL: v_maximumnum_f64_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], 1.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -1061,8 +939,6 @@ define double @v_maximumnum_f64_1.0(double %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double 1.0)
@@ -1188,93 +1064,37 @@ define half @v_maximumnum_f16_s_v(half inreg %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v1, v0
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_s_v:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_s_v:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_s_v:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_s_v:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_s_v:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_s_v:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_s_v:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_s_v:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_s_v:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_s_v:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_s_v:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_s_v:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half %y)
ret half %result
}
@@ -1398,93 +1218,37 @@ define half @v_maximumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_v_s:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_v_s:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_v_s:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_v_s:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_v_s:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_v_s:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_v_s:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_v_s:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_v_s:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_v_s:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_v_s:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, s0, v0.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_v_s:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, s0, v0
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half %y)
ret half %result
}
@@ -1620,99 +1384,27 @@ define half @v_maximumnum_f16_s_s(half inreg %x, half inreg %y) #1 {
; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_s_s:
; GFX1170-TRUE16-GISEL: ; %bb.0:
; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, s0, s0
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v1.l, s1, s1
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1170-TRUE16-GISEL-NEXT: s_max_f16 s0, s0, s1
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, s0, s1
; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_s_s:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_s_s:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, s0, s0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s1, s1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_max_f16 s0, s0, s1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-FAKE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_s_s:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_s_s:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, s0, s0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v1.l, s1, s1
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-TRUE16-GISEL-NEXT: s_max_num_f16 s0, s0, s1
-; GFX12-TRUE16-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_s_s:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v1, v0
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_s_s:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, s0, s0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s1, s1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-FAKE16-GISEL-NEXT: s_max_num_f16 s0, s0, s1
-; GFX12-FAKE16-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-FAKE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_s_s:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, s0, s1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f16_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f16 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half %y)
ret half %result
}
@@ -1816,49 +1508,21 @@ define float @v_maximumnum_f32_s_v(float inreg %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_s_v:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_s_v:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_s_v:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_s_v:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_s_v:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e32 v0, s0, v0
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_s_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e32 v0, s0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
}
@@ -1962,49 +1626,21 @@ define float @v_maximumnum_f32_v_s(float %x, float inreg %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_v_s:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_v_s:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_v_s:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_v_s:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_v_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e32 v0, s0, v0
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_v_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e32 v0, s0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
}
@@ -2108,58 +1744,24 @@ define float @v_maximumnum_f32_s_s(float inreg %x, float inreg %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_s_s:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_s_s:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1170-GISEL-NEXT: s_max_f32 s0, s0, s1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_s_s:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_s_s:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-GISEL-NEXT: s_max_num_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_s_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e64 v0, s0, s1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
}
@@ -2249,10 +1851,7 @@ define double @v_maximumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64_s_v:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: v_max_num_f64 v[0:1], s[0:1], v[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f64_s_v:
@@ -2262,10 +1861,7 @@ define double @v_maximumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %result
@@ -2356,10 +1952,7 @@ define double @v_maximumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX1170-LABEL: v_maximumnum_f64_v_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], s[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximumnum_f64_v_s:
@@ -2369,10 +1962,7 @@ define double @v_maximumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %result
@@ -2477,49 +2067,21 @@ define double @v_maximumnum_f64_s_s(double inreg %x, double inreg %y) #1 {
; GFX11-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f64_s_s:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], s[2:3], s[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[2:3], v[0:1]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f64_s_s:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], s[0:1], s[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], s[2:3], s[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f64_s_s:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f64_s_s:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f64_s_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], s[0:1], s[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f64_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %result
}
@@ -2607,49 +2169,21 @@ define float @v_maximumnum_f32_fabs_rhs(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_fabs_rhs:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_fabs_rhs:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_fabs_rhs:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_fabs_rhs:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_fabs_rhs:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e64 v0, v0, |v1|
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_fabs_rhs:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, v0, |v1|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%result = call float @llvm.maximumnum.f32(float %x, float %fabs.y)
ret float %result
@@ -2738,49 +2272,21 @@ define float @v_maximumnum_f32_fneg_fabs_rhs(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e64 v0, v0, -|v1|
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_fneg_fabs_rhs:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, v0, -|v1|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%fneg.fabs.y = fneg float %fabs.y
%result = call float @llvm.maximumnum.f32(float %x, float %fneg.fabs.y)
@@ -2870,49 +2376,21 @@ define float @v_maximumnum_f32_fabs(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_fabs:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_fabs:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_fabs:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_fabs:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_fabs:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e64 v0, |v0|, |v1|
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_fabs:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, |v0|, |v1|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
%result = call float @llvm.maximumnum.f32(float %fabs.x, float %fabs.y)
@@ -3002,49 +2480,21 @@ define float @v_maximumnum_f32_fneg(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_fneg:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_fneg:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_fneg:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_fneg:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_fneg:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e64 v0, -v0, -v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_fneg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, -v0, -v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg float %x
%fneg.y = fneg float %y
%result = call float @llvm.maximumnum.f32(float %fneg.x, float %fneg.y)
@@ -3154,93 +2604,37 @@ define half @v_maximumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, |v1.l|
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, |v1|
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, |v1.l|
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, |v1|
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call half @llvm.fabs.f16(half %y)
%result = call half @llvm.maximumnum.f16(half %x, half %fabs.y)
ret half %result
@@ -3349,93 +2743,37 @@ define half @v_maximumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, -|v1.l|
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, -|v1|
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, v0.l, -|v1.l|
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, v0, -|v1|
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call half @llvm.fabs.f16(half %y)
%fneg.fabs.y = fneg half %fabs.y
%result = call half @llvm.maximumnum.f16(half %x, half %fneg.fabs.y)
@@ -3545,93 +2883,37 @@ define half @v_maximumnum_f16_fabs(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_fabs:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fabs:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v1.l|
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_fabs:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fabs:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v1|
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_fabs:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_fabs:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_fabs:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_fabs:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_fabs:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_fabs:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fabs:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v1.l|
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fabs:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, |v0|, |v1|
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
%result = call half @llvm.maximumnum.f16(half %fabs.x, half %fabs.y)
@@ -3741,93 +3023,37 @@ define half @v_maximumnum_f16_fneg(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_fneg:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_fneg:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v1.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_fneg:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_fneg:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_fneg:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_fneg:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_fneg:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_fneg:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_fneg:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_fneg:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fneg:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v1.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fneg:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e64 v0, -v0, -v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg half %x
%fneg.y = fneg half %y
%result = call half @llvm.maximumnum.f16(half %fneg.x, half %fneg.y)
@@ -3917,49 +3143,21 @@ define double @v_maximumnum_f64_fneg(double %x, double %y) #1 {
; GFX11-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f64_fneg:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], -v[2:3], -v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f64_fneg:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], -v[2:3], -v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f64_fneg:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f64_fneg:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f64_fneg:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f64_fneg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg double %x
%fneg.y = fneg double %y
%result = call double @llvm.maximumnum.f64(double %fneg.x, double %fneg.y)
@@ -4093,49 +3291,21 @@ define <2 x half> @v_maximumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v2f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v2f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v2f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v2f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v2f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v2f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -4381,61 +3551,23 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v3f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v3f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v3f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v3f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v3f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v3f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x half> @llvm.maximumnum.v3f16(<3 x half> %x, <3 x half> %y)
ret <3 x half> %result
}
@@ -4739,61 +3871,23 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v4f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v4f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v4f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v4f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v4f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v4f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %x, <4 x half> %y)
ret <4 x half> %result
}
@@ -5172,73 +4266,25 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v2, v2, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v6f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v5
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v6f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v5
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v6f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v5
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v6f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v5
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v6f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v3
+; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v4
+; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v5
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v6f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v3
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v4
+; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x half> @llvm.maximumnum.v6f16(<6 x half> %x, <6 x half> %y)
ret <6 x half> %result
}
@@ -5556,85 +4602,27 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v3, v3, v7
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v8f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v7
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v8f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v7
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v8f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v7
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v8f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v7
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v8f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v8f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x half> @llvm.maximumnum.v8f16(<8 x half> %x, <8 x half> %y)
ret <8 x half> %result
}
@@ -6198,129 +5186,35 @@ define <16 x half> @v_maximumnum_v16f16(<16 x half> %x, <16 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v7, v7, v12
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v16f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v12
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v16f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v12
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v16f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v12
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v16f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v10
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v10
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v11
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v12
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v16f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v8
+; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v9
+; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v10
+; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v11
+; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v12
+; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v13
+; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v14
+; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v15
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v16f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v8
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v9
+; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v10
+; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v11
+; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v12
+; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v13
+; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v14
+; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v15
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x half> @llvm.maximumnum.v16f16(<16 x half> %x, <16 x half> %y)
ret <16 x half> %result
}
@@ -7441,237 +6335,55 @@ define <32 x half> @v_maximumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_max_f16 v15, v15, v16
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v32f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v16
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v17
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v18
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v19
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v20
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v21
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v22
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v23
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v24
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v25
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v26
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v11, v11, v27
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v12, v12, v28
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v13, v13, v29
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v14, v14, v30
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v15, v15, v16
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v32f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v16
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v17
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v18
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v19
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v20
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v21
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v22
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v23
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v24
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v25
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v26
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v11, v11, v27
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v12, v12, v28
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v13, v13, v29
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v14, v14, v30
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v15, v15, v16
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v32f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v16
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v17
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v18
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v19
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v20
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v21
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v22
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v23
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v24
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v25
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v26
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v11, v11, v27
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v12, v12, v28
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v13, v13, v29
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v14, v14, v30
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v15, v15, v16
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v32f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v16
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v17
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v18
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v19
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v20
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v21
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v22
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v23
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v24
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v25
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v26
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v11, v11, v27
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v12, v12, v28
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v13, v13, v29
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v14, v14, v30
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v15, v15, v16
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v32f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: scratch_load_b32 v31, off, s32
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v16
+; GFX1170-NEXT: v_pk_max_num_f16 v1, v1, v17
+; GFX1170-NEXT: v_pk_max_num_f16 v2, v2, v18
+; GFX1170-NEXT: v_pk_max_num_f16 v3, v3, v19
+; GFX1170-NEXT: v_pk_max_num_f16 v4, v4, v20
+; GFX1170-NEXT: v_pk_max_num_f16 v5, v5, v21
+; GFX1170-NEXT: v_pk_max_num_f16 v6, v6, v22
+; GFX1170-NEXT: v_pk_max_num_f16 v7, v7, v23
+; GFX1170-NEXT: v_pk_max_num_f16 v8, v8, v24
+; GFX1170-NEXT: v_pk_max_num_f16 v9, v9, v25
+; GFX1170-NEXT: v_pk_max_num_f16 v10, v10, v26
+; GFX1170-NEXT: v_pk_max_num_f16 v11, v11, v27
+; GFX1170-NEXT: v_pk_max_num_f16 v12, v12, v28
+; GFX1170-NEXT: v_pk_max_num_f16 v13, v13, v29
+; GFX1170-NEXT: v_pk_max_num_f16 v14, v14, v30
+; GFX1170-NEXT: s_waitcnt vmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v15, v15, v31
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v32f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: scratch_load_b32 v31, off, s32
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v16
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v17
+; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v18
+; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v19
+; GFX12-NEXT: v_pk_max_num_f16 v4, v4, v20
+; GFX12-NEXT: v_pk_max_num_f16 v5, v5, v21
+; GFX12-NEXT: v_pk_max_num_f16 v6, v6, v22
+; GFX12-NEXT: v_pk_max_num_f16 v7, v7, v23
+; GFX12-NEXT: v_pk_max_num_f16 v8, v8, v24
+; GFX12-NEXT: v_pk_max_num_f16 v9, v9, v25
+; GFX12-NEXT: v_pk_max_num_f16 v10, v10, v26
+; GFX12-NEXT: v_pk_max_num_f16 v11, v11, v27
+; GFX12-NEXT: v_pk_max_num_f16 v12, v12, v28
+; GFX12-NEXT: v_pk_max_num_f16 v13, v13, v29
+; GFX12-NEXT: v_pk_max_num_f16 v14, v14, v30
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v15, v15, v31
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <32 x half> @llvm.maximumnum.v32f16(<32 x half> %x, <32 x half> %y)
ret <32 x half> %result
}
@@ -7783,49 +6495,21 @@ define <2 x float> @v_maximumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_max_f32 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v2f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v2f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v2f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v2f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v2f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v2f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x float> @llvm.maximumnum.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %result
}
@@ -8019,57 +6703,23 @@ define <3 x float> @v_maximumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v2, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v3f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v2, v2, v5
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v3f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v5
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v3f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v2, v2, v5
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v3f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v5
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v3f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
+; GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v3f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v3 :: v_dual_max_num_f32 v1, v1, v4
+; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x float> @llvm.maximumnum.v3f32(<3 x float> %x, <3 x float> %y)
ret <3 x float> %result
}
@@ -8296,61 +6946,23 @@ define <4 x float> @v_maximumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v6 :: v_dual_max_f32 v3, v3, v7
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v4f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v4f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v4f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v4f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v4f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
+; GFX1170-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v4f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v4 :: v_dual_max_num_f32 v1, v1, v5
+; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v6 :: v_dual_max_num_f32 v3, v3, v7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %result
}
@@ -8555,61 +7167,23 @@ define <2 x double> @v_maximumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX11-GISEL-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v2f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[6:7]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v2f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[6:7]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v2f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v2f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v2f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[6:7]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v2f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.maximumnum.v2f64(<2 x double> %x, <2 x double> %y)
ret <2 x double> %result
}
@@ -8842,73 +7416,25 @@ define <3 x double> @v_maximumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX11-GISEL-NEXT: v_max_f64 v[4:5], v[4:5], v[10:11]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v3f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[10:11]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v3f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[10:11]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v3f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[10:11]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v3f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[10:11]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v3f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[8:9]
+; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[10:11]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v3f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[8:9]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[10:11]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.maximumnum.v3f64(<3 x double> %x, <3 x double> %y)
ret <3 x double> %result
}
@@ -9184,85 +7710,27 @@ define <4 x double> @v_maximumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX11-GISEL-NEXT: v_max_f64 v[6:7], v[6:7], v[14:15]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v4f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[14:15]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v4f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[12:13]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[14:15]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v4f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v4f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v4f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-NEXT: v_max_num_f64 v[2:3], v[2:3], v[10:11]
+; GFX1170-NEXT: v_max_num_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-NEXT: v_max_num_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v4f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[10:11]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[12:13]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[14:15]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x double> @llvm.maximumnum.v4f64(<4 x double> %x, <4 x double> %y)
ret <4 x double> %result
}
@@ -9387,93 +7855,37 @@ define half @v_maximumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_maximumnum_f16_no_ieee:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_maximumnum_f16_no_ieee:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_maximumnum_f16_no_ieee:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_maximumnum_f16_no_ieee:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_no_ieee:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_maximumnum_f16_no_ieee:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_maximumnum_f16_no_ieee:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_maximumnum_f16_no_ieee:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_maximumnum_f16_no_ieee:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_maximumnum_f16_no_ieee:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_maximumnum_f16_no_ieee:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_no_ieee:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.maximumnum.f16(half %x, half %y)
ret half %result
}
@@ -9593,45 +8005,21 @@ define float @v_maximumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f32_no_ieee:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f32_no_ieee:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f32_no_ieee:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f32_no_ieee:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f32_no_ieee:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
}
@@ -9717,49 +8105,21 @@ define double @v_maximumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_f64_no_ieee:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_f64_no_ieee:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_f64_no_ieee:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_f64_no_ieee:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_f64_no_ieee:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_f64_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %result
}
@@ -9883,49 +8243,21 @@ define <2 x half> @v_maximumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX11-NEXT: v_pk_max_f16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_maximumnum_v2f16_no_ieee:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_maximumnum_v2f16_no_ieee:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_maximumnum_v2f16_no_ieee:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_maximumnum_v2f16_no_ieee:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_maximumnum_v2f16_no_ieee:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_maximumnum_v2f16_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -10255,5 +8587,15 @@ attributes #0 = { "amdgpu-ieee"="false" nounwind }
attributes #1 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1170-FAKE16-GISEL: {{.*}}
+; GFX1170-FAKE16-SDAG: {{.*}}
+; GFX1170-GISEL: {{.*}}
+; GFX1170-SDAG: {{.*}}
+; GFX12-FAKE16-GISEL: {{.*}}
+; GFX12-FAKE16-SDAG: {{.*}}
+; GFX12-GISEL: {{.*}}
+; GFX12-SDAG: {{.*}}
+; GFX12-TRUE16-GISEL: {{.*}}
+; GFX12-TRUE16-SDAG: {{.*}}
; GFX900: {{.*}}
; GFX950: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
index 18ea5e2dd0e6c..bb64e69f5be17 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
@@ -135,93 +135,37 @@ define half @v_minimumnum_f16(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_minimumnum_f16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -359,16 +303,12 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX1170-TRUE16-LABEL: v_minimumnum_f16_1.0:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, 1.0, v0.l
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_minimumnum_f16_1.0:
; GFX1170-FAKE16: ; %bb.0:
; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -379,8 +319,6 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, 1.0, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -391,8 +329,6 @@ define half @v_minimumnum_f16_1.0(half %x) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half 1.0)
@@ -480,45 +416,21 @@ define float @v_minimumnum_f32(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -656,49 +568,21 @@ define double @v_minimumnum_f64(double %x, double %y) #1 {
; GFX11-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -793,8 +677,6 @@ define float @v_minimumnum_f32_1.0(float %x) #1 {
; GFX1170-LABEL: v_minimumnum_f32_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, 1.0, v0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -805,8 +687,6 @@ define float @v_minimumnum_f32_1.0(float %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, 1.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float 1.0)
@@ -857,7 +737,7 @@ define float @v_minimumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_rhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX1170-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -869,7 +749,7 @@ define float @v_minimumnum_f32_rhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -922,7 +802,7 @@ define float @v_minimumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX1170-LABEL: v_minimumnum_f32_lhs_not_snan:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-NEXT: s_setpc_b64 s[30:31]
@@ -934,7 +814,7 @@ define float @v_minimumnum_f32_lhs_not_snan(float %x, float %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1049,8 +929,6 @@ define double @v_minimumnum_f64_1.0(double %x) #1 {
; GFX1170-LABEL: v_minimumnum_f64_1.0:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], 1.0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -1061,8 +939,6 @@ define double @v_minimumnum_f64_1.0(double %x) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double 1.0)
@@ -1188,93 +1064,37 @@ define half @v_minimumnum_f16_v_s(half %x, half inreg %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16_v_s:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16_v_s:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, s0, v0.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_v_s:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_v_s:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, s0, v0
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_v_s:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, s0, v0.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_v_s:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_v_s:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_v_s:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_v_s:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_v_s:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_v_s:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_v_s:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, s0, v0
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -1410,99 +1230,27 @@ define half @v_minimumnum_f16_s_s(half inreg %x, half inreg %y) #1 {
; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_s_s:
; GFX1170-TRUE16-GISEL: ; %bb.0:
; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, s0, s0
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v1.l, s1, s1
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1170-TRUE16-GISEL-NEXT: s_min_f16 s0, s0, s1
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e64 v0.l, s0, s1
; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_s_s:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v1, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_s_s:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, s0, s0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s1, s1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_min_f16 s0, s0, s1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-FAKE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_s_s:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, s1, s1
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, s0, s0
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_s_s:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, s0, s0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v1.l, s1, s1
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-TRUE16-GISEL-NEXT: s_min_num_f16 s0, s0, s1
-; GFX12-TRUE16-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_s_s:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, s1, s1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, s0, s0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v1, v0
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_s_s:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, s0, s0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, s1, s1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-FAKE16-GISEL-NEXT: s_min_num_f16 s0, s0, s1
-; GFX12-FAKE16-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-FAKE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_s_s:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, s0, s1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f16_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f16 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -1606,49 +1354,21 @@ define float @v_minimumnum_f32_s_v(float inreg %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_s_v:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_s_v:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_s_v:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_s_v:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_s_v:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e32 v0, s0, v0
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_s_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e32 v0, s0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -1752,49 +1472,21 @@ define float @v_minimumnum_f32_v_s(float %x, float inreg %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_v_s:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_v_s:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_v_s:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_v_s:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_v_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e32 v0, s0, v0
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_v_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e32 v0, s0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -1898,58 +1590,24 @@ define float @v_minimumnum_f32_s_s(float inreg %x, float inreg %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_s_s:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_s_s:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1170-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1170-GISEL-NEXT: s_min_f32 s0, s0, s1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1170-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_s_s:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, s1, s1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, s0, s0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v1, v0
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_s_s:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, s0, s0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, s1, s1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-GISEL-NEXT: s_min_num_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_s_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e64 v0, s0, s1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -2039,10 +1697,7 @@ define double @v_minimumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64_s_v:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[2:3], v[0:1]
+; GFX1170-NEXT: v_min_num_f64 v[0:1], s[0:1], v[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f64_s_v:
@@ -2052,10 +1707,7 @@ define double @v_minimumnum_f64_s_v(double inreg %x, double %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
@@ -2146,10 +1798,7 @@ define double @v_minimumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX1170-LABEL: v_minimumnum_f64_v_s:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], s[0:1]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimumnum_f64_v_s:
@@ -2159,10 +1808,7 @@ define double @v_minimumnum_f64_v_s(double %x, double inreg %y) #1 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
@@ -2267,49 +1913,21 @@ define double @v_minimumnum_f64_s_s(double inreg %x, double inreg %y) #1 {
; GFX11-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f64_s_s:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], s[2:3], s[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], s[0:1], s[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[2:3], v[0:1]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f64_s_s:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], s[0:1], s[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], s[2:3], s[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f64_s_s:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], s[2:3], s[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f64_s_s:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f64_s_s:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], s[0:1], s[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f64_s_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e64 v[0:1], s[0:1], s[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -2397,49 +2015,21 @@ define float @v_minimumnum_f32_fabs_rhs(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_fabs_rhs:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_fabs_rhs:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_fabs_rhs:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_fabs_rhs:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_fabs_rhs:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e64 v0, v0, |v1|
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_fabs_rhs:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e64 v0, v0, |v1|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%result = call float @llvm.minimumnum.f32(float %x, float %fabs.y)
ret float %result
@@ -2528,49 +2118,21 @@ define float @v_minimumnum_f32_fneg_fabs_rhs(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e64 v0, v0, -|v1|
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e64 v0, v0, -|v1|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%fneg.fabs.y = fneg float %fabs.y
%result = call float @llvm.minimumnum.f32(float %x, float %fneg.fabs.y)
@@ -2660,49 +2222,21 @@ define float @v_minimumnum_f32_fabs(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_fabs:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_fabs:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_fabs:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_fabs:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_fabs:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e64 v0, |v0|, |v1|
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_fabs:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e64 v0, |v0|, |v1|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
%result = call float @llvm.minimumnum.f32(float %fabs.x, float %fabs.y)
@@ -2792,49 +2326,21 @@ define float @v_minimumnum_f32_fneg(float %x, float %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_fneg:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX1170-SDAG-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_fneg:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX1170-GISEL-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_fneg:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-SDAG-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_fneg:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v0, -v0, -v0
-; GFX12-GISEL-NEXT: v_max_num_f32_e64 v1, -v1, -v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_fneg:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e64 v0, -v0, -v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_fneg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e64 v0, -v0, -v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg float %x
%fneg.y = fneg float %y
%result = call float @llvm.minimumnum.f32(float %fneg.x, float %fneg.y)
@@ -2944,93 +2450,37 @@ define half @v_minimumnum_f16_fabs_rhs(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, |v1.l|
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, |v1|
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, |v1.l|
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, |v1|
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call half @llvm.fabs.f16(half %y)
%result = call half @llvm.minimumnum.f16(half %x, half %fabs.y)
ret half %result
@@ -3139,93 +2589,37 @@ define half @v_minimumnum_f16_fneg_fabs_rhs(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, -|v1.l|
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, -|v1|
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, v0.l, -|v1.l|
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, v0, -|v1|
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call half @llvm.fabs.f16(half %y)
%fneg.fabs.y = fneg half %fabs.y
%result = call half @llvm.minimumnum.f16(half %x, half %fneg.fabs.y)
@@ -3335,93 +2729,37 @@ define half @v_minimumnum_f16_fabs(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16_fabs:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fabs:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, |v0.l|, |v1.l|
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_fabs:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fabs:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, |v0|, |v1|
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_fabs:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_fabs:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_fabs:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_fabs:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_fabs:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_fabs:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fabs:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, |v0.l|, |v1.l|
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fabs:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, |v0|, |v1|
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
%result = call half @llvm.minimumnum.f16(half %fabs.x, half %fabs.y)
@@ -3531,93 +2869,37 @@ define half @v_minimumnum_f16_fneg(half %x, half %y) #1 {
; GFX11-FAKE16-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16_fneg:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16_fneg:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e64 v0.l, -v0.l, -v1.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_fneg:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_fneg:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e64 v0, -v0, -v1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fneg:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e64 v0.l, -v0.l, -v1.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_fneg:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_fneg:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_fneg:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_fneg:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_fneg:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_fneg:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fneg:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e64 v0, -v0, -v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg half %x
%fneg.y = fneg half %y
%result = call half @llvm.minimumnum.f16(half %fneg.x, half %fneg.y)
@@ -3707,49 +2989,21 @@ define double @v_minimumnum_f64_fneg(double %x, double %y) #1 {
; GFX11-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f64_fneg:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], -v[2:3], -v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f64_fneg:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], -v[0:1], -v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], -v[2:3], -v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f64_fneg:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f64_fneg:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f64_fneg:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], -v[0:1], -v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f64_fneg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e64 v[0:1], -v[0:1], -v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg double %x
%fneg.y = fneg double %y
%result = call double @llvm.minimumnum.f64(double %fneg.x, double %fneg.y)
@@ -3883,49 +3137,21 @@ define <2 x half> @v_minimumnum_v2f16(<2 x half> %x, <2 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v2f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v2f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v2f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v2f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v2f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v2f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -4171,61 +3397,23 @@ define <3 x half> @v_minimumnum_v3f16(<3 x half> %x, <3 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v3f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v3f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v3f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v3f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v3f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v3f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x half> @llvm.minimumnum.v3f16(<3 x half> %x, <3 x half> %y)
ret <3 x half> %result
}
@@ -4529,61 +3717,23 @@ define <4 x half> @v_minimumnum_v4f16(<4 x half> %x, <4 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v4f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v4f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v4f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v4f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v4f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v4f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %x, <4 x half> %y)
ret <4 x half> %result
}
@@ -4962,73 +4112,25 @@ define <6 x half> @v_minimumnum_v6f16(<6 x half> %x, <6 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v2, v2, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v6f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v4
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v5
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v6f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v4
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v5
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v6f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v4
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v5
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v6f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v4
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v5
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v6f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v3
+; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v5
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v6f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v3
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x half> @llvm.minimumnum.v6f16(<6 x half> %x, <6 x half> %y)
ret <6 x half> %result
}
@@ -5346,85 +4448,27 @@ define <8 x half> @v_minimumnum_v8f16(<8 x half> %x, <8 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v3, v3, v7
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v8f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v7
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v8f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v7
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v8f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v7
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v8f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v7
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v8f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX1170-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v8f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x half> @llvm.minimumnum.v8f16(<8 x half> %x, <8 x half> %y)
ret <8 x half> %result
}
@@ -5988,129 +5032,35 @@ define <16 x half> @v_minimumnum_v16f16(<16 x half> %x, <16 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v7, v7, v12
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v16f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v7, v7, v12
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v16f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v7, v7, v12
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v16f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v7, v7, v12
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v16f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v11, v11
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v10
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v12, v12
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v13, v13
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v11, v14, v14
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v12, v15, v15
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v8
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v4, v4, v9
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v5, v5, v10
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v6, v6, v11
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v7, v7, v12
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v16f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v8
+; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v9
+; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v10
+; GFX1170-NEXT: v_pk_min_num_f16 v3, v3, v11
+; GFX1170-NEXT: v_pk_min_num_f16 v4, v4, v12
+; GFX1170-NEXT: v_pk_min_num_f16 v5, v5, v13
+; GFX1170-NEXT: v_pk_min_num_f16 v6, v6, v14
+; GFX1170-NEXT: v_pk_min_num_f16 v7, v7, v15
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v16f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v8
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v9
+; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v10
+; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v11
+; GFX12-NEXT: v_pk_min_num_f16 v4, v4, v12
+; GFX12-NEXT: v_pk_min_num_f16 v5, v5, v13
+; GFX12-NEXT: v_pk_min_num_f16 v6, v6, v14
+; GFX12-NEXT: v_pk_min_num_f16 v7, v7, v15
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x half> @llvm.minimumnum.v16f16(<16 x half> %x, <16 x half> %y)
ret <16 x half> %result
}
@@ -7231,237 +6181,55 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) #1 {
; GFX11-GISEL-NEXT: v_pk_min_f16 v15, v15, v16
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v32f16:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v16
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v17
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v18
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v19
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v4, v4, v20
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v5, v5, v21
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v6, v6, v22
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v7, v7, v23
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v8, v8, v24
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v9, v9, v25
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v10, v10, v26
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v11, v11, v27
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v12, v12, v28
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v13, v13, v29
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v14, v14, v30
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v15, v15, v16
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v32f16:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v16
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v17
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v18
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v19
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v4, v4, v20
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v5, v5, v21
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v6, v6, v22
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v7, v7, v23
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v8, v8, v24
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v9, v9, v25
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v10, v10, v26
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v11, v11, v27
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v12, v12, v28
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v13, v13, v29
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v14, v14, v30
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v15, v15, v16
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v32f16:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v16
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v17
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v18
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v19
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v4, v4, v20
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v5, v5, v21
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v6, v6, v22
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v7, v7, v23
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v8, v8, v24
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v9, v9, v25
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v10, v10, v26
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v11, v11, v27
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v12, v12, v28
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v13, v13, v29
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v14, v14, v30
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v15, v15, v16
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v32f16:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v16, v16, v16
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v17, v17, v17
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v18, v18, v18
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v19, v19, v19
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v20, v20, v20
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v21, v21, v21
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v22, v22, v22
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v23, v23, v23
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v8, v8, v8
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v24, v24, v24
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v9, v9, v9
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v25, v25, v25
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v10, v10, v10
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v26, v26, v26
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v11, v11, v11
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v27, v27, v27
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v12, v12, v12
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v28, v28, v28
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v13, v13, v13
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v29, v29, v29
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v14, v14, v14
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v30, v30, v30
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v15, v15, v15
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v16
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v17
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v18
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v19
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v4, v4, v20
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v5, v5, v21
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v6, v6, v22
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v7, v7, v23
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v8, v8, v24
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v9, v9, v25
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v10, v10, v26
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v11, v11, v27
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v12, v12, v28
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v13, v13, v29
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v14, v14, v30
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v16, v31, v31
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v15, v15, v16
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v32f16:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: scratch_load_b32 v31, off, s32
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v16
+; GFX1170-NEXT: v_pk_min_num_f16 v1, v1, v17
+; GFX1170-NEXT: v_pk_min_num_f16 v2, v2, v18
+; GFX1170-NEXT: v_pk_min_num_f16 v3, v3, v19
+; GFX1170-NEXT: v_pk_min_num_f16 v4, v4, v20
+; GFX1170-NEXT: v_pk_min_num_f16 v5, v5, v21
+; GFX1170-NEXT: v_pk_min_num_f16 v6, v6, v22
+; GFX1170-NEXT: v_pk_min_num_f16 v7, v7, v23
+; GFX1170-NEXT: v_pk_min_num_f16 v8, v8, v24
+; GFX1170-NEXT: v_pk_min_num_f16 v9, v9, v25
+; GFX1170-NEXT: v_pk_min_num_f16 v10, v10, v26
+; GFX1170-NEXT: v_pk_min_num_f16 v11, v11, v27
+; GFX1170-NEXT: v_pk_min_num_f16 v12, v12, v28
+; GFX1170-NEXT: v_pk_min_num_f16 v13, v13, v29
+; GFX1170-NEXT: v_pk_min_num_f16 v14, v14, v30
+; GFX1170-NEXT: s_waitcnt vmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v15, v15, v31
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v32f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: scratch_load_b32 v31, off, s32
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v16
+; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v17
+; GFX12-NEXT: v_pk_min_num_f16 v2, v2, v18
+; GFX12-NEXT: v_pk_min_num_f16 v3, v3, v19
+; GFX12-NEXT: v_pk_min_num_f16 v4, v4, v20
+; GFX12-NEXT: v_pk_min_num_f16 v5, v5, v21
+; GFX12-NEXT: v_pk_min_num_f16 v6, v6, v22
+; GFX12-NEXT: v_pk_min_num_f16 v7, v7, v23
+; GFX12-NEXT: v_pk_min_num_f16 v8, v8, v24
+; GFX12-NEXT: v_pk_min_num_f16 v9, v9, v25
+; GFX12-NEXT: v_pk_min_num_f16 v10, v10, v26
+; GFX12-NEXT: v_pk_min_num_f16 v11, v11, v27
+; GFX12-NEXT: v_pk_min_num_f16 v12, v12, v28
+; GFX12-NEXT: v_pk_min_num_f16 v13, v13, v29
+; GFX12-NEXT: v_pk_min_num_f16 v14, v14, v30
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v15, v15, v31
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <32 x half> @llvm.minimumnum.v32f16(<32 x half> %x, <32 x half> %y)
ret <32 x half> %result
}
@@ -7573,49 +6341,21 @@ define <2 x float> @v_minimumnum_v2f32(<2 x float> %x, <2 x float> %y) #1 {
; GFX11-GISEL-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v2f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v2f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v2f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v2f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v2f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v2f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x float> @llvm.minimumnum.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %result
}
@@ -7809,57 +6549,23 @@ define <3 x float> @v_minimumnum_v3f32(<3 x float> %x, <3 x float> %y) #1 {
; GFX11-GISEL-NEXT: v_min_f32_e32 v2, v2, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v3f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v2, v2, v5
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v3f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v5
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v3f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v2, v2, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v2, v2, v5
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v3f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v5
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v3f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX1170-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v3f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX12-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x float> @llvm.minimumnum.v3f32(<3 x float> %x, <3 x float> %y)
ret <3 x float> %result
}
@@ -8086,61 +6792,23 @@ define <4 x float> @v_minimumnum_v4f32(<4 x float> %x, <4 x float> %y) #1 {
; GFX11-GISEL-NEXT: v_dual_min_f32 v2, v2, v6 :: v_dual_min_f32 v3, v3, v7
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v4f32:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
-; GFX1170-SDAG-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v4f32:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v4f32:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
-; GFX12-SDAG-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v4f32:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v4f32:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
+; GFX1170-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v4f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
+; GFX12-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x float> @llvm.minimumnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %result
}
@@ -8345,61 +7013,23 @@ define <2 x double> @v_minimumnum_v2f64(<2 x double> %x, <2 x double> %y) #1 {
; GFX11-GISEL-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v2f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[2:3], v[2:3], v[6:7]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v2f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[2:3], v[6:7]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v2f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v2f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v2f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-NEXT: v_min_num_f64 v[2:3], v[2:3], v[6:7]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v2f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> %y)
ret <2 x double> %result
}
@@ -8632,73 +7262,25 @@ define <3 x double> @v_minimumnum_v3f64(<3 x double> %x, <3 x double> %y) #1 {
; GFX11-GISEL-NEXT: v_min_f64 v[4:5], v[4:5], v[10:11]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v3f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[2:3], v[2:3], v[8:9]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[4:5], v[4:5], v[10:11]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v3f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[2:3], v[8:9]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[4:5], v[4:5], v[10:11]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v3f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v3f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v3f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-NEXT: v_min_num_f64 v[2:3], v[2:3], v[8:9]
+; GFX1170-NEXT: v_min_num_f64 v[4:5], v[4:5], v[10:11]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v3f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.minimumnum.v3f64(<3 x double> %x, <3 x double> %y)
ret <3 x double> %result
}
@@ -8974,85 +7556,27 @@ define <4 x double> @v_minimumnum_v4f64(<4 x double> %x, <4 x double> %y) #1 {
; GFX11-GISEL-NEXT: v_min_f64 v[6:7], v[6:7], v[14:15]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v4f64:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[2:3], v[2:3], v[10:11]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[4:5], v[4:5], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[6:7], v[6:7], v[14:15]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v4f64:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[2:3], v[10:11]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[4:5], v[4:5], v[12:13]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[6:7], v[6:7], v[14:15]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v4f64:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v4f64:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[10:11]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v4f64:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-NEXT: v_min_num_f64 v[2:3], v[2:3], v[10:11]
+; GFX1170-NEXT: v_min_num_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-NEXT: v_min_num_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v4f64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[10:11]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
+; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> %x, <4 x double> %y)
ret <4 x double> %result
}
@@ -9177,93 +7701,37 @@ define half @v_minimumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX11-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-SDAG-LABEL: v_minimumnum_f16_no_ieee:
-; GFX1170-TRUE16-SDAG: ; %bb.0:
-; GFX1170-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: v_minimumnum_f16_no_ieee:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-TRUE16-GISEL-LABEL: v_minimumnum_f16_no_ieee:
-; GFX1170-TRUE16-GISEL: ; %bb.0:
-; GFX1170-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: v_minimumnum_f16_no_ieee:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_no_ieee:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-FAKE16-SDAG-LABEL: v_minimumnum_f16_no_ieee:
-; GFX1170-FAKE16-SDAG: ; %bb.0:
-; GFX1170-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-FAKE16-GISEL-LABEL: v_minimumnum_f16_no_ieee:
-; GFX1170-FAKE16-GISEL: ; %bb.0:
-; GFX1170-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-SDAG-LABEL: v_minimumnum_f16_no_ieee:
-; GFX12-TRUE16-SDAG: ; %bb.0:
-; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-TRUE16-GISEL-LABEL: v_minimumnum_f16_no_ieee:
-; GFX12-TRUE16-GISEL: ; %bb.0:
-; GFX12-TRUE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-GISEL-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-SDAG-LABEL: v_minimumnum_f16_no_ieee:
-; GFX12-FAKE16-SDAG: ; %bb.0:
-; GFX12-FAKE16-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-SDAG-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-SDAG-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-GISEL-LABEL: v_minimumnum_f16_no_ieee:
-; GFX12-FAKE16-GISEL: ; %bb.0:
-; GFX12-FAKE16-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-FAKE16-GISEL-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_no_ieee:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -9383,45 +7851,21 @@ define float @v_minimumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f32_no_ieee:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f32_no_ieee:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f32_no_ieee:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f32_no_ieee:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f32_no_ieee:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f32_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -9507,49 +7951,21 @@ define double @v_minimumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_f64_no_ieee:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_f64_no_ieee:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_f64_no_ieee:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_f64_no_ieee:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_f64_no_ieee:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_f64_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -9673,49 +8089,21 @@ define <2 x half> @v_minimumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX11-NEXT: v_pk_min_f16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: v_minimumnum_v2f16_no_ieee:
-; GFX1170-SDAG: ; %bb.0:
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: v_minimumnum_v2f16_no_ieee:
-; GFX1170-GISEL: ; %bb.0:
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: v_minimumnum_v2f16_no_ieee:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: v_minimumnum_v2f16_no_ieee:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: v_minimumnum_v2f16_no_ieee:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_minimumnum_v2f16_no_ieee:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -10045,5 +8433,15 @@ attributes #0 = { "amdgpu-ieee"="false" nounwind }
attributes #1 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1170-FAKE16-GISEL: {{.*}}
+; GFX1170-FAKE16-SDAG: {{.*}}
+; GFX1170-GISEL: {{.*}}
+; GFX1170-SDAG: {{.*}}
+; GFX12-FAKE16-GISEL: {{.*}}
+; GFX12-FAKE16-SDAG: {{.*}}
+; GFX12-GISEL: {{.*}}
+; GFX12-SDAG: {{.*}}
+; GFX12-TRUE16-GISEL: {{.*}}
+; GFX12-TRUE16-SDAG: {{.*}}
; GFX900: {{.*}}
; GFX950: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index 9599e09ab54cc..d688e3b56ef2b 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -563,63 +563,28 @@ define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) {
; GISEL-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX1170-LABEL: test_minmax_f32_ieee_true:
-; SDAG-GFX1170: ; %bb.0:
-; SDAG-GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v2
-; SDAG-GFX1170-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
-; SDAG-GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_minmax_f32_ieee_true:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1170-LABEL: test_minmax_f32_ieee_true:
-; GISEL-GFX1170: ; %bb.0:
-; GISEL-GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GISEL-GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GISEL-GFX1170-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
-; GISEL-GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_minmax_f32_ieee_true:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX12-LABEL: test_minmax_f32_ieee_true:
-; SDAG-GFX12: ; %bb.0:
-; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
-; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
-; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
-; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
-; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX12-LABEL: test_minmax_f32_ieee_true:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL-GFX12-NEXT: s_wait_expcnt 0x0
-; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0
-; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
-; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GISEL-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
-; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1250-LABEL: test_minmax_f32_ieee_true:
-; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; SDAG-GFX1250-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v2
-; SDAG-GFX1250-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
-; SDAG-GFX1250-NEXT: s_set_pc_i64 s[30:31]
-;
-; GISEL-GFX1250-LABEL: test_minmax_f32_ieee_true:
-; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL-GFX1250-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GISEL-GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GISEL-GFX1250-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
-; GISEL-GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: test_minmax_f32_ieee_true:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max = call float @llvm.maxnum.f32(float %a, float %b)
%minmax = call float @llvm.minnum.f32(float %max, float %c)
ret float %minmax
@@ -754,63 +719,28 @@ define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) {
; GISEL-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX1170-LABEL: test_maxmin_f32_ieee_true:
-; SDAG-GFX1170: ; %bb.0:
-; SDAG-GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v2
-; SDAG-GFX1170-NEXT: v_minmax_num_f32 v0, v0, v1, v2
-; SDAG-GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_maxmin_f32_ieee_true:
+; GFX1170: ; %bb.0:
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_minmax_num_f32 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1170-LABEL: test_maxmin_f32_ieee_true:
-; GISEL-GFX1170: ; %bb.0:
-; GISEL-GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GISEL-GFX1170-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GISEL-GFX1170-NEXT: v_minmax_num_f32 v0, v0, v1, v2
-; GISEL-GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_maxmin_f32_ieee_true:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX12-LABEL: test_maxmin_f32_ieee_true:
-; SDAG-GFX12: ; %bb.0:
-; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
-; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
-; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
-; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; SDAG-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
-; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX12-LABEL: test_maxmin_f32_ieee_true:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL-GFX12-NEXT: s_wait_expcnt 0x0
-; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0
-; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
-; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GISEL-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
-; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1250-LABEL: test_maxmin_f32_ieee_true:
-; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; SDAG-GFX1250-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; SDAG-GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v2
-; SDAG-GFX1250-NEXT: v_minmax_num_f32 v0, v0, v1, v2
-; SDAG-GFX1250-NEXT: s_set_pc_i64 s[30:31]
-;
-; GISEL-GFX1250-LABEL: test_maxmin_f32_ieee_true:
-; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL-GFX1250-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GISEL-GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GISEL-GFX1250-NEXT: v_minmax_num_f32 v0, v0, v1, v2
-; GISEL-GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: test_maxmin_f32_ieee_true:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_minmax_num_f32 v0, v0, v1, v2
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%min = call float @llvm.minnum.f32(float %a, float %b)
%maxmin = call float @llvm.maxnum.f32(float %min, float %c)
ret float %maxmin
@@ -1224,36 +1154,24 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1170-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
; SDAG-GFX1170-TRUE16: ; %bb.0:
; SDAG-GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1170-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; SDAG-GFX1170-FAKE16: ; %bb.0:
; SDAG-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1170-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1170-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
; GISEL-GFX1170-TRUE16: ; %bb.0:
; GISEL-GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GISEL-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1170-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; GISEL-GFX1170-FAKE16: ; %bb.0:
; GISEL-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1170-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1264,10 +1182,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1277,9 +1192,6 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1290,10 +1202,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1303,9 +1212,6 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1313,19 +1219,13 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1250-TRUE16: ; %bb.0:
; SDAG-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; SDAG-GFX1250-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; SDAG-GFX1250-FAKE16: ; %bb.0:
; SDAG-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1333,19 +1233,13 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1250-TRUE16: ; %bb.0:
; GISEL-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GISEL-GFX1250-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
; GISEL-GFX1250-FAKE16: ; %bb.0:
; GISEL-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %b)
@@ -1482,36 +1376,24 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1170-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; SDAG-GFX1170-TRUE16: ; %bb.0:
; SDAG-GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1170-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; SDAG-GFX1170-FAKE16: ; %bb.0:
; SDAG-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1170-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1170-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; GISEL-GFX1170-TRUE16: ; %bb.0:
; GISEL-GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GISEL-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1170-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; GISEL-GFX1170-FAKE16: ; %bb.0:
; GISEL-GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GISEL-GFX1170-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1170-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1522,10 +1404,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
@@ -1535,9 +1414,6 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1548,10 +1424,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GISEL-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
@@ -1561,9 +1434,6 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1571,19 +1441,13 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; SDAG-GFX1250-TRUE16: ; %bb.0:
; SDAG-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; SDAG-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; SDAG-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; SDAG-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; SDAG-GFX1250-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; SDAG-GFX1250-FAKE16: ; %bb.0:
; SDAG-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; SDAG-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; SDAG-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1591,19 +1455,13 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1250-TRUE16: ; %bb.0:
; GISEL-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
-; GISEL-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GISEL-GFX1250-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
; GISEL-GFX1250-FAKE16: ; %bb.0:
; GISEL-GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GISEL-GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GISEL-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %b)
diff --git a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
index a8f5d1d1bc4b4..f5f3ddf880987 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
@@ -22,9 +22,8 @@ define float @v_max3_maxnum_tree4_f32(float %a, float %b, float %c, float %d) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v3, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v3
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call float @llvm.maxnum.f32(float %a, float %b)
%max.cd = call float @llvm.maxnum.f32(float %c, float %d)
@@ -50,10 +49,9 @@ define float @v_max3_maxnum_tree8_f32(float %a, float %b, float %c, float %d,
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: v_max3_num_f32 v1, v4, v5, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v3, v1
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v7, v7
-; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v7
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
float %e, float %f, float %g, float %h) {
%ab = call float @llvm.maxnum.f32(float %a, float %b)
@@ -193,9 +191,8 @@ define float @v_min3_minnum_tree4_f32(float %a, float %b, float %c, float %d) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v3, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1250-NEXT: v_min_num_f32_e32 v0, v0, v3
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%min.ab = call float @llvm.minnum.f32(float %a, float %b)
%min.cd = call float @llvm.minnum.f32(float %c, float %d)
@@ -345,9 +342,8 @@ define float @v_max3_maxnum_tree4_multi_use(float %a, float %b, float %c, float
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_max_num_f32 v3, v3, v3 :: v_dual_max_num_f32 v2, v2, v2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
@@ -431,9 +427,8 @@ define half @v_max3_maxnum_tree4_f16(half %a, half %b, half %c, half %d) {
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v2
-; GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v1, v3, v3
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v3
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-REAL16-LABEL: v_max3_maxnum_tree4_f16:
@@ -441,9 +436,8 @@ define half @v_max3_maxnum_tree4_f16(half %a, half %b, half %c, half %d) {
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v2.l
-; GFX1250-REAL16-NEXT: v_max_num_f16_e32 v0.h, v3.l, v3.l
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1250-REAL16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v3.l
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call half @llvm.maxnum.f16(half %a, half %b)
%max.cd = call half @llvm.maxnum.f16(half %c, half %d)
@@ -469,11 +463,6 @@ define double @v_no_max3_maxnum_tree4_f64(double %a, double %b, double %c, doubl
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX1250-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX1250-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -624,11 +613,9 @@ define <2 x float> @v_max3_maxnum_tree4_v2f32(<2 x float> %a, <2 x float> %b, <2
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v2, v4
-; GFX1250-NEXT: v_max_num_f32_e32 v2, v6, v6
; GFX1250-NEXT: v_max3_num_f32 v1, v1, v3, v5
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_max_num_f32 v3, v7, v7 :: v_dual_max_num_f32 v0, v0, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v1, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_max_num_f32 v0, v0, v6 :: v_dual_max_num_f32 v1, v1, v7
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
%max.cd = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %c, <2 x float> %d)
@@ -698,9 +685,8 @@ define <2 x half> @v_max3_maxnum_tree4_v2f16(<2 x half> %a, <2 x half> %b, <2 x
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_pk_max3_num_f16 v0, v0, v1, v2
-; GFX1250-NEXT: v_pk_max_num_f16 v1, v3, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v3
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%max.ab = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
%max.cd = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %d)
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll b/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
index f21bd9784c66f..2bf24014cbab3 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
@@ -313,31 +313,13 @@ define <4 x half> @fminnum_v4f16_neg(<4 x half> %first, <4 x half> %second) {
; GFX950-GISEL-NEXT: v_pk_min_f16 v1, v1, v2
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-SDAG-LABEL: fminnum_v4f16_neg:
-; GFX1250-SDAG: ; %bb.0:
-; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
-;
-; GFX1250-GISEL-LABEL: fminnum_v4f16_neg:
-; GFX1250-GISEL: ; %bb.0:
-; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1250-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: fminnum_v4f16_neg:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_pk_min_num_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_min_num_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%neg = fneg <4 x half> %second
%fmin = tail call <4 x half> @llvm.minnum.v4f16(<4 x half> %first, <4 x half> %neg)
ret <4 x half> %fmin
@@ -380,43 +362,15 @@ define <8 x half> @fminnum_v8f16_neg(<8 x half> %first, <8 x half> %second) {
; GFX950-GISEL-NEXT: v_pk_min_f16 v3, v3, v4
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-SDAG-LABEL: fminnum_v8f16_neg:
-; GFX1250-SDAG: ; %bb.0:
-; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-SDAG-NEXT: v_pk_min_num_f16 v3, v3, v7
-; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
-;
-; GFX1250-GISEL-LABEL: fminnum_v8f16_neg:
-; GFX1250-GISEL: ; %bb.0:
-; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v4
-; GFX1250-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v5
-; GFX1250-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v6
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v7
-; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: fminnum_v8f16_neg:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_pk_min_num_f16 v0, v0, v4 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_min_num_f16 v1, v1, v5 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_min_num_f16 v2, v2, v6 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_min_num_f16 v3, v3, v7 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%neg = fneg <8 x half> %second
%fmin = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> %first, <8 x half> %neg)
ret <8 x half> %fmin
@@ -447,31 +401,13 @@ define <4 x half> @fmaxnum_v4f16_neg(<4 x half> %first, <4 x half> %second) {
; GFX950-GISEL-NEXT: v_pk_max_f16 v1, v1, v2
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-SDAG-LABEL: fmaxnum_v4f16_neg:
-; GFX1250-SDAG: ; %bb.0:
-; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
-;
-; GFX1250-GISEL-LABEL: fmaxnum_v4f16_neg:
-; GFX1250-GISEL: ; %bb.0:
-; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: fmaxnum_v4f16_neg:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_max_num_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%neg = fneg <4 x half> %second
%fmax = tail call <4 x half> @llvm.maxnum.v4f16(<4 x half> %first, <4 x half> %neg)
ret <4 x half> %fmax
@@ -514,44 +450,19 @@ define <8 x half> @fmaxnum_v8f16_neg(<8 x half> %first, <8 x half> %second) {
; GFX950-GISEL-NEXT: v_pk_max_f16 v3, v3, v4
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-SDAG-LABEL: fmaxnum_v8f16_neg:
-; GFX1250-SDAG: ; %bb.0:
-; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v4, v4, v4 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v5, v5, v5 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v6, v6, v6 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v7, v7, v7 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-SDAG-NEXT: v_pk_max_num_f16 v3, v3, v7
-; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
-;
-; GFX1250-GISEL-LABEL: fmaxnum_v8f16_neg:
-; GFX1250-GISEL: ; %bb.0:
-; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v4, v4, v4 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v5, v5, v5 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v6, v6, v6 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v7, v7, v7 neg_lo:[1,1] neg_hi:[1,1]
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v0, v0, v4
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v1, v1, v5
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v2, v2, v6
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-GISEL-NEXT: v_pk_max_num_f16 v3, v3, v7
-; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: fmaxnum_v8f16_neg:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v4 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_max_num_f16 v1, v1, v5 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_max_num_f16 v2, v2, v6 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: v_pk_max_num_f16 v3, v3, v7 neg_lo:[0,1] neg_hi:[0,1]
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%neg = fneg <8 x half> %second
%fmax = tail call <8 x half> @llvm.maxnum.v8f16(<8 x half> %first, <8 x half> %neg)
ret <8 x half> %fmax
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250-GISEL: {{.*}}
+; GFX1250-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index 643e4daa913e3..5eff29747519a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -130,9 +130,6 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -140,18 +137,13 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -159,9 +151,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -172,9 +162,6 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -186,9 +173,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -199,9 +184,6 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -213,9 +195,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -347,9 +327,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7e00
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xfe00
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
@@ -358,10 +336,9 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0x7e00
+; GFX1170-SDAG-FAKE16-NEXT: s_mov_b32 s0, 0xfe00
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -371,10 +348,6 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -382,10 +355,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -396,9 +366,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7e00
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xfe00
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
@@ -411,13 +379,13 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0x7e00
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_mov_b32 s0, 0xfe00
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -428,10 +396,6 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -443,10 +407,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -611,34 +572,25 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -647,11 +599,6 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
@@ -664,10 +611,8 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -678,12 +623,9 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -694,12 +636,8 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -712,11 +650,6 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v2
; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
@@ -984,51 +917,37 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v4
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v5
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v4
+; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1036,23 +955,16 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v7
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v5, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v5
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v6, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v7, v3
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1064,11 +976,6 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1083,11 +990,6 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1104,19 +1006,11 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1128,23 +1022,16 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v7
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v5, v3
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v4
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v5
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v6, v1
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v7, v3
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1602,19 +1489,17 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v2.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v4.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v5.h
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v5.h
; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1622,59 +1507,41 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v8
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v9
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v8
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v2
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v5, v1
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v6, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v7, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v5.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v5.h, v7.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.l, v4.l, v4.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.l, v4.l, v4.h, v5.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.h, v6.l, v6.h, v5.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v2.l, v2.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v3.l, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1682,41 +1549,25 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v4
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v11
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v13
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v4, v4, v12, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v5, v6, v11, v7
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v9
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v12
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v4, v4, v13, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v5, v6, v14, v7
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v8, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v10, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v4, v5
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v2
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1727,20 +1578,16 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v2.h
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v4.h
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v5.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v6.h
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1750,29 +1597,18 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v9
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v2
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v5, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v6, v2
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_num_f16 v0, v0, v7, v1
+; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1782,32 +1618,17 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v5.h, v7.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.l, v4.l, v4.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.l, v4.l, v4.h, v5.l
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.h, v6.l, v6.h, v5.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v2.l, v2.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1819,41 +1640,25 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v4
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v10
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v11
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v11
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v13
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v4, v4, v12, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v5, v6, v11, v7
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v9
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v12
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v4, v4, v13, v5
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v5, v6, v14, v7
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v8, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v10, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v4, v5
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v2
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -1942,45 +1747,21 @@ define float @test_vector_reduce_fmax_v2float(<2 x float> %v) {
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v2float:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v2float:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v2float:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v2float:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmax_v2float:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmax_v2float:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmax.v2float(<2 x float> %v)
ret float %res
@@ -2062,43 +1843,21 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v3float:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v3float:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v3float:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v3float:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmax_v3float:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmax_v3float:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmax.v3float(<3 x float> %v)
ret float %res
@@ -2207,19 +1966,16 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v4float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2230,9 +1986,8 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2243,10 +1998,8 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2402,27 +2155,22 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v8float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_max_num_f32 v5, v6, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v3, v4, v5
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v3, v6, v7
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2434,12 +2182,11 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2450,15 +2197,11 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_max_num_f32 v5, v6, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: v_max3_num_f32 v1, v3, v4, v5
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v3, v6, v7
+; GFX12-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2699,43 +2442,34 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v16float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v8, v9
-; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v12, v13
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max3_num_f32 v0, v0, v14, v15
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_max_num_f32 v2, v2, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v3, v3, v6
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v10, v10, v11
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v11, v14, v15
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v3, v6, v7
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v10
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v7, v12, v13, v11
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_max_num_f32 v11, v11, v14
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v7
; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
-; GFX1170-GISEL-NEXT: v_max3_num_f32 v7, v10, v12, v11
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v6, v7
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2747,18 +2481,17 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v4, v5
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v8, v9
-; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v12, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_num_f32 v0, v0, v14, v15
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2769,26 +2502,18 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_max_num_f32 v2, v2, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v3, v3, v6
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v10, v10, v11
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v11, v14, v15
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v3, v6, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_max_num_f32 v11, v11, v14
+; GFX12-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v10
+; GFX12-GISEL-NEXT: v_max3_num_f32 v7, v12, v13, v11
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v7
-; GFX12-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
-; GFX12-GISEL-NEXT: v_max3_num_f32 v7, v10, v12, v11
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v6, v7
+; GFX12-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2880,49 +2605,21 @@ define double @test_vector_reduce_fmax_v2double(<2 x double> %v) {
; GFX11-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v2double:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v2double:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v2double:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v2double:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmax_v2double:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmax_v2double:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmax.v2double(<2 x double> %v)
ret double %res
@@ -3031,57 +2728,25 @@ define double @test_vector_reduce_fmax_v3double(<3 x double> %v) {
; GFX11-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v3double:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v3double:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v3double:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v3double:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmax_v3double:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmax_v3double:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmax.v3double(<3 x double> %v)
ret double %res
@@ -3215,25 +2880,15 @@ define double @test_vector_reduce_fmax_v4double(<4 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v4double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v4double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[4:5], v[6:7]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3247,15 +2902,10 @@ define double @test_vector_reduce_fmax_v4double(<4 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v4double:
@@ -3265,11 +2915,6 @@ define double @test_vector_reduce_fmax_v4double(<4 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3490,46 +3135,29 @@ define double @test_vector_reduce_fmax_v8double(<8 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v8double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[14:15]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v8double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[4:5], v[6:7]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[8:9], v[10:11]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[12:13], v[14:15]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3540,25 +3168,16 @@ define double @test_vector_reduce_fmax_v8double(<8 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[14:15]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v8double:
@@ -3568,22 +3187,14 @@ define double @test_vector_reduce_fmax_v8double(<8 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[10:11]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[12:13], v[14:15]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3985,67 +3596,36 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v16double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[16:17], v[16:17]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[18:19], v[18:19]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[20:21], v[20:21]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[22:23], v[22:23]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[24:25], v[24:25]
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[26:27], v[26:27]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[28:29], v[28:29]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[16:17]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[18:19]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[20:21]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[22:23]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[24:25]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[26:27]
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[28:29]
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[30:31], v[30:31]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[30:31]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v16double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[16:17], v[16:17], v[16:17]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[18:19], v[18:19], v[18:19]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[20:21], v[20:21], v[20:21]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[22:23], v[22:23], v[22:23]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[24:25], v[24:25], v[24:25]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[26:27], v[26:27], v[26:27]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[28:29], v[28:29], v[28:29]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[4:5], v[6:7]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[8:9], v[10:11]
@@ -4059,12 +3639,11 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[8:9], v[10:11]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[30:31], v[30:31], v[30:31]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[28:29], v[30:31]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[12:13], v[14:15]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[12:13], v[14:15]
; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -4075,46 +3654,30 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[16:17], v[16:17]
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[18:19], v[18:19]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[20:21], v[20:21]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[22:23], v[22:23]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[24:25], v[24:25]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[26:27], v[26:27]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[28:29], v[28:29]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[14:15]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[16:17]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[18:19]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[20:21]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[22:23]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[24:25]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[26:27]
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[28:29]
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[30:31], v[30:31]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[30:31]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v16double:
@@ -4125,21 +3688,6 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[16:17], v[16:17], v[16:17]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[18:19], v[18:19], v[18:19]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[20:21], v[20:21], v[20:21]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[22:23], v[22:23], v[22:23]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[24:25], v[24:25], v[24:25]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[26:27], v[26:27], v[26:27]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[28:29], v[28:29], v[28:29]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[10:11]
@@ -4153,12 +3701,11 @@ define double @test_vector_reduce_fmax_v16double(<16 x double> %v) {
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[10:11]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[30:31], v[30:31], v[30:31]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[28:29], v[30:31]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[12:13], v[14:15]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[12:13], v[14:15]
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4184,7 +3731,5 @@ declare double @llvm.vector.reduce.fmax.v16double(<16 x double>)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX10: {{.*}}
; GFX11: {{.*}}
-; GFX1170: {{.*}}
-; GFX12: {{.*}}
; GFX8: {{.*}}
; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index c574bf0fbe86e..fba8151605380 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -130,9 +130,6 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -140,18 +137,13 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -159,9 +151,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -172,9 +162,6 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -186,9 +173,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -199,9 +184,6 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -213,9 +195,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -348,8 +328,6 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7e00
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
@@ -358,10 +336,9 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0x7e00
+; GFX1170-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7e00
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -371,10 +348,6 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -382,10 +355,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -397,8 +367,6 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7e00
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
@@ -411,13 +379,13 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0x7e00
-; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7e00
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -428,10 +396,6 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -443,10 +407,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -611,34 +572,25 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -647,11 +599,6 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v2
; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
@@ -664,10 +611,8 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -678,12 +623,9 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -694,12 +636,8 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -712,11 +650,6 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v2
; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
@@ -984,51 +917,37 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v4
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v5
+; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v4
+; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1036,23 +955,16 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v7
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v5, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v5
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v6, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v7, v3
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1064,11 +976,6 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1083,11 +990,6 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1104,19 +1006,11 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1128,23 +1022,16 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v7
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v1
-; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v5, v3
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v4
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v5
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v6, v1
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v7, v3
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1602,19 +1489,17 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v2.h
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v4.h
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v5.h
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v5.h
; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1622,59 +1507,41 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v8
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v9
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v8
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v2
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v5, v1
; GFX1170-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v6, v2
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v7, v1
; GFX1170-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v5.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v7.l, v7.h
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.h, v3.h, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v5.h, v7.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v1.h, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.l, v4.l, v4.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.l, v4.l, v4.h, v5.l
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.h, v6.l, v6.h, v5.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v2.l, v2.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v3.l, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1682,41 +1549,25 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v4
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v11
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v13
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v4, v4, v12, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v5, v6, v11, v7
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v9
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v12
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v4, v4, v13, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v5, v6, v14, v7
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v8, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v10, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v4, v5
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v2
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1727,20 +1578,16 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v2.h
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v4.h
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v5.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v6.h
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1750,29 +1597,18 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v9
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v8
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v2
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v5, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v6, v2
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_num_f16 v0, v0, v7, v1
+; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1782,32 +1618,17 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.l, v5.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v7.l, v7.h
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.h, v3.h, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v5.h, v7.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v1.h, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.l, v4.l, v4.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.l, v4.l, v4.h, v5.l
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.h, v6.l, v6.h, v5.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v2.l, v2.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1819,41 +1640,25 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v4
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v10
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v11
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v11
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v13
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v9
-; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v4, v4, v12, v5
-; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v5, v6, v11, v7
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v9
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v12
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v4, v4, v13, v5
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v5, v6, v14, v7
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v8, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v10, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v4, v5
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v2
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -1942,45 +1747,21 @@ define float @test_vector_reduce_fmin_v2float(<2 x float> %v) {
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v2float:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v2float:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v2float:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v2float:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmin_v2float:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmin_v2float:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmin.v2float(<2 x float> %v)
ret float %res
@@ -2062,43 +1843,21 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v3float:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v3float:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v3float:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v3float:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmin_v3float:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmin_v3float:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmin.v3float(<3 x float> %v)
ret float %res
@@ -2207,19 +1966,16 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v4float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2230,9 +1986,8 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2243,10 +1998,8 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2402,27 +2155,22 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v8float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_min_num_f32 v5, v6, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v3, v4, v5
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v3, v6, v7
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2434,12 +2182,11 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2450,15 +2197,11 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_min_num_f32 v5, v6, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: v_min3_num_f32 v1, v3, v4, v5
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v3, v6, v7
+; GFX12-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2699,43 +2442,34 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v16float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v8, v9
-; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v12, v13
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min3_num_f32 v0, v0, v14, v15
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_min_num_f32 v2, v2, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v3, v3, v6
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v10, v10, v11
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v11, v14, v15
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v3, v6, v7
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v10
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v7, v12, v13, v11
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_min_num_f32 v11, v11, v14
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v7
; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
-; GFX1170-GISEL-NEXT: v_min3_num_f32 v7, v10, v12, v11
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v6, v7
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2747,18 +2481,17 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v2, v3
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v4, v5
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v6, v7
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v8, v9
-; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v10, v11
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v12, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_num_f32 v0, v0, v14, v15
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2769,26 +2502,18 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_min_num_f32 v2, v2, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v3, v3, v6
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v10, v10, v11
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v11, v14, v15
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v3, v6, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_min_num_f32 v11, v11, v14
+; GFX12-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v10
+; GFX12-GISEL-NEXT: v_min3_num_f32 v7, v12, v13, v11
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v7
-; GFX12-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
-; GFX12-GISEL-NEXT: v_min3_num_f32 v7, v10, v12, v11
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v6, v7
+; GFX12-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2879,49 +2604,21 @@ define double @test_vector_reduce_fmin_v2double(<2 x double> %v) {
; GFX11-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v2double:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v2double:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v2double:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v2double:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmin_v2double:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmin_v2double:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmin.v2double(<2 x double> %v)
ret double %res
@@ -3030,57 +2727,25 @@ define double @test_vector_reduce_fmin_v3double(<3 x double> %v) {
; GFX11-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v3double:
-; GFX1170-SDAG: ; %bb.0: ; %entry
-; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v3double:
-; GFX1170-GISEL: ; %bb.0: ; %entry
-; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v3double:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v3double:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-LABEL: test_vector_reduce_fmin_v3double:
+; GFX1170: ; %bb.0: ; %entry
+; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_vector_reduce_fmin_v3double:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmin.v3double(<3 x double> %v)
ret double %res
@@ -3214,25 +2879,15 @@ define double @test_vector_reduce_fmin_v4double(<4 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v4double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v4double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[4:5], v[6:7]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3246,15 +2901,10 @@ define double @test_vector_reduce_fmin_v4double(<4 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v4double:
@@ -3264,11 +2914,6 @@ define double @test_vector_reduce_fmin_v4double(<4 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3489,46 +3134,29 @@ define double @test_vector_reduce_fmin_v8double(<8 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v8double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[14:15]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v8double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[4:5], v[6:7]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[4:5], v[8:9], v[10:11]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[6:7], v[12:13], v[14:15]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3539,25 +3167,16 @@ define double @test_vector_reduce_fmin_v8double(<8 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[14:15]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v8double:
@@ -3567,22 +3186,14 @@ define double @test_vector_reduce_fmin_v8double(<8 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[4:5], v[8:9], v[10:11]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[6:7], v[12:13], v[14:15]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3984,67 +3595,36 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v16double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[6:7], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[8:9], v[8:9]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[10:11], v[10:11]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[12:13], v[12:13]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[14:15], v[14:15]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[16:17], v[16:17]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[18:19], v[18:19]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[20:21], v[20:21]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[22:23], v[22:23]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[24:25], v[24:25]
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[26:27], v[26:27]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[4:5], v[28:29], v[28:29]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[10:11]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[12:13]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[16:17]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[18:19]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[20:21]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[22:23]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[24:25]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[26:27]
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[28:29]
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: v_max_num_f64 v[2:3], v[30:31], v[30:31]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_min_num_f64 v[0:1], v[0:1], v[30:31]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v16double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[0:1], v[0:1], v[0:1]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[2:3], v[2:3], v[2:3]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[4:5], v[4:5], v[4:5]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[6:7], v[6:7], v[6:7]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[8:9], v[8:9], v[8:9]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[10:11], v[10:11], v[10:11]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[12:13], v[12:13], v[12:13]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[14:15], v[14:15], v[14:15]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[16:17], v[16:17], v[16:17]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[18:19], v[18:19], v[18:19]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[20:21], v[20:21], v[20:21]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[22:23], v[22:23], v[22:23]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[24:25], v[24:25], v[24:25]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[26:27], v[26:27], v[26:27]
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[28:29], v[28:29], v[28:29]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[4:5], v[6:7]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[4:5], v[8:9], v[10:11]
@@ -4058,12 +3638,11 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX1170-GISEL-NEXT: v_min_num_f64 v[4:5], v[8:9], v[10:11]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-GISEL-NEXT: v_max_num_f64 v[30:31], v[30:31], v[30:31]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[14:15], v[28:29], v[30:31]
-; GFX1170-GISEL-NEXT: v_min_num_f64 v[6:7], v[12:13], v[14:15]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_min_num_f64 v[6:7], v[12:13], v[14:15]
; GFX1170-GISEL-NEXT: v_min_num_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -4074,46 +3653,30 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[8:9], v[8:9]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[10:11], v[10:11]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[12:13], v[12:13]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[14:15], v[14:15]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[16:17], v[16:17]
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[18:19], v[18:19]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[20:21], v[20:21]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[22:23], v[22:23]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[24:25], v[24:25]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[26:27], v[26:27]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[28:29], v[28:29]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[10:11]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[12:13]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[14:15]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[16:17]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[18:19]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[20:21]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[22:23]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[24:25]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[26:27]
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[28:29]
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[30:31], v[30:31]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[30:31]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v16double:
@@ -4124,21 +3687,6 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[16:17], v[16:17], v[16:17]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[18:19], v[18:19], v[18:19]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[20:21], v[20:21], v[20:21]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[22:23], v[22:23], v[22:23]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[24:25], v[24:25], v[24:25]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[26:27], v[26:27], v[26:27]
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[28:29], v[28:29], v[28:29]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[6:7]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[4:5], v[8:9], v[10:11]
@@ -4152,12 +3700,11 @@ define double @test_vector_reduce_fmin_v16double(<16 x double> %v) {
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[4:5], v[8:9], v[10:11]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_max_num_f64_e32 v[30:31], v[30:31], v[30:31]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[14:15], v[28:29], v[30:31]
-; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[6:7], v[12:13], v[14:15]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[6:7], v[12:13], v[14:15]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4183,7 +3730,5 @@ declare double @llvm.vector.reduce.fmin.v16double(<16 x double>)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX10: {{.*}}
; GFX11: {{.*}}
-; GFX1170: {{.*}}
-; GFX12: {{.*}}
; GFX8: {{.*}}
; GFX9: {{.*}}
More information about the llvm-commits
mailing list